Sliding-Mode Control of the PWM Audio Amplifier

The filter output voltage v₀, divided by the amplifier gain (l/k_v), must follow a reference v_or. Defining the output error as e_v0 = v_or –k_vv₀, and also using its time derivatives (e_θ,e_γ,e_β) as a new state vector ε = [e_v0, e_θ, e_γ, e_β], the system equations, in the phase canonical (or controllability) form, can be written in the form as follows

(36.128)

Sliding-mode control of the output voltage will enable a robust and reduced-order dynamics, independent of semiconductors, power supply, filter, and load parameters. According to Eqs. (36.91) and (36.128), the sliding surface is

(36.129)

In sliding mode, Eq. (36.129) confirms the amplifier gain (v_o/v_or = 1/k_v). To obtain a stable system and the smallest possible response time t_r, a pole placement according to a third-order Bessel polynomial is used. Taking t_r inversely proportional to a frequency just below the lowest cutoff frequency (ω₁) of the double LC filter (t_r ≈ 2.8/ω₁ ≈ 2.8/(2π 21 kHz) ≈ 20 μs) and using Eq. (36.88) with m = 3, the characteristic polynomial Eq. (36.130), verifying the Routh-Hurwitz criterion, is obtained.

(36.130)

From Eq. (36.97), the switching law for the control input at time t_k, γ(t_k) must be

(36.131)

To ensure reaching and existence conditions, the power supply voltage V_dd must be greater than the maximum required mean value of the output voltage in a switching period V_dd > . The sliding-mode controller (Fig. 36.41) is obtained from Eqs. (36.129) to (36.131) with k_θ = t_r,k_γ = 6t²_r/15,k = t³_r/15. The derivatives can be approximated by the block diagram of Fig. 36.41b, where h is the oversampling period.

FIGURE 36.41 (a) Sliding-mode controller for the PWM audio amplifier and (b) implementation of the derivative blocks.

Figure 36.42a shows the v_PWM> v_or, v₀/10, and the error 10 × (v_or –v₀/10) waveforms for a 20 kHz sine input. The overall behavior is much better than the obtained with the sigma-delta controllers (Figs. 36.43 and 36.44) explained below for comparison purposes. There is no 0.5 dB loss or phase delay over the entire audio band; the Chebyshev filter behaves as a maximally flat filter, with higher stopband attenuation. Figure 36.42b shows v_PWM,v_0r> and 10 × (v_or –v₀/10) with a 1 kHz square input. There is almost no steady-state error and almost no overshoot on the speaker voltage v₀, attesting to the speed of response (t ≈ 20 μs as designed since, in contrast to Example 36.12, no derivatives were neglected). The stability, the system order reduction, and the sliding-mode controller usefulness for the PWM audio amplifier are also shown.

FIGURE 36.42 Sliding-mode controlled audio power amplifier performance (upper graphs show v_PWM,lower graph trace 1 show , lower graph trace 2 show v_o/10, and lower graph trace 3 show : (a) response to a 20 kHz sine input, at 55 W output power and (b) response to 1 kHz square wave input, at 100 W output power.

FIGURE 36.43 (a) First-order sigma-delta modulator and (b) second-order sigma-delta modulator.

FIGURE 36.44 First-order sigma-delta audio amplifier performance (upper graphs show v_PWM, lower graphs trace 1 show , lower graphs trace 2 shows v_o/10, and lower graphs trace 3 show : (a) response to a 20 kHz sine input, at 55 W output power and (b) response to 1 kHz square wave input, at 100 W output power.

Sigma-Delta-Controlled PWM Audio Amplifier

Assume now the fourth-order Chebyshev low-pass filter, as an ideal filter removing the high-frequency content of the v_PWM voltage. Then, the v_PWM voltage can be considered the amplifier output. However, the discontinuous voltage v_PWM = γ V_dd is not a state variable and cannot follow the almost continuous reference v_PMWr. The new error variable e_vPWM = v_PMWr–k_vγ V_dd is always far from the zero value. Given this nonzero error, the approach outlined in Section 36.3.4 can be used. The switching law remains Eq. (36.131), but the new control law Eq. (36.132) is

(36.132)

The κ parameter is calculated to impose the maximum switching frequency f_PWM Since dt = 2ε we obtain

(36.133)

Assuming that v_PWMr is nearly constant over the switching period 1/f_PWM, Eq. (36.132) confirms the amplifier gain since

Practical implementation of this control strategy can be done using an integrator with gain κ(κ ≈ 1800) and a comparator with hysteresis e(e ≈ 6 mV), Fig. 36.43a. Such an arrangement is called a first-order sigma-delta (SΔ) modulator.

Figure 36.44a shows the v_PWM, v_or and v_o/10 waveforms for a 20 kHz sine input. The overall behavior is as expected because the practical filter and loudspeaker are not ideal, but notice the 0.5 dB loss and phase delay of the speaker voltage v_o, mainly due to the output filter and speaker inductance. In Fig. 36.44b, the v_PWM, v_or, v_o/10, and error 10 × (v_or –v_o/10) for a 1 kHz square input are shown. Note the oscillations and steady-state error of the speaker voltage v_o due to the filter dynamics and double termination.

A second-order sigma-delta modulator is a better compromise between circuit complexity and signal-to-quantization noise ratio. As the switching frequency of the two power MOSFET (Fig. 36.40) cannot be further increased, the second-order structure named “cascaded integrators with feedback” (Fig. 36.43b) was selected and designed to eliminate the step response overshoot found in Fig. 36.44b.

Figure 36.45a, for 1 kHz square input shows much less overshoot and oscillations than Fig. 36.44b. However, the v_PWM, v_or, and v_o/10 waveforms, for a 20 kHz sine input presented in Fig. 36.45b, show increased output voltage loss, compared to the first-order sigma-delta modulator, since the second-order modulator was designed to eliminate the v_o output voltage ringing (therefore reducing the amplifier bandwidth). The obtained performances with these and other sigma-delta structures are inferior to the sliding-mode performances (Fig. 36.42). Sliding mode brings definite advantages as the system order is reduced, flatter passbands are obtained, power supply rejection ratio is increased, and the nonlinear effects, together with the frequency-dependent phase delays, are cancelled out.

FIGURE 36.45 Second-order sigma-delta audio amplifier performance (upper graphs show v_PWM, lower graphs trace 1 show v_or ≡ v_i, lower graphs trace 2 show v_o/10, and lower graphs trace 3 show : (a) response to 1-kHz square wave input, at 100 W output power and (b) response to a 20-kHz sine input, at 55 W output power.

EXAMPLE 36.14 Sliding-mode control of near unity power factor PWM three-phase rectifiers

Boost-type voltage-sourced three-phase rectifiers (Fig. 36.46) are multiple-input multiple-output (MIMO) systems capable of bidirectional power flow, near unity power factor operation, and almost sinusoidal input currents, and can behave as ac/dc power supplies or power factor compensators.

The fast power semiconductors used (usually MOS-FETs or IGBTs) can switch at frequencies much higher than the mains frequency, enabling the voltage controller to provide an output voltage with fast dynamic response.

FIGURE 36.46 Voltage-sourced three-phase PWM rectifier with IGBTs and test load.

Modeling the Three-Phase PWM Boost Rectifier

Neglecting switch delays and dead times, the states of the switches of the kth inverter leg (Fig. 36.46) can be represented by the time-dependent nonlinear variables γ_k, defined as

(36.134)

Consider the displayed variables of the circuit (Fig. 36.46), where L is the value of the boost inductors, R their resistance, C the value of the output capacitor, and R_c its equivalent series resistance (ESR). Neglecting semiconductor voltage drops, leakage currents, and auxiliary networks, the application of Kirchhoff laws (taking the load current i₀ as a time-dependent perturbation) yields the following switched state-space model of the boost rectifier:

(36.135)

where .

Since the input voltage sources have no neutral connection, the preceding model can be simplified, eliminating one equation. Using the relationship (36.136) between the fixed frames x_1,2,3 and xα,β in Eq. (36.135), the state-space model (36.137), in the α,β frame, is obtained.

(36.136)

(36.137)

where .

Sliding-Mode Control of the PWM Rectifier

The model (36.137) is nonlinear and time variant. Applying the Park transformation (36.138), using a frequency ω rotating reference frame synchronized with the mains (with the q component of the supply voltages equal to zero), the nonlinear, time-invariant model (36.139) is written:

(36.138)

(36.139)

where .

This state-space model can be used to obtain the feedback controllers for the PWM boost rectifier. Considering the output voltage v_o and the i_q current as the controlled outputs and γ_d, γ_q the control inputs (MIMO system), the input–output linearization of Eq. (36.72) gives the state-space equations in the controllability canonical form (36.140):

(36.140)

where

Using the rectifier overall power balance (from Tellegen's theorem, the converter is conservative, i.e. the power delivered to the load or dissipated in the converter intrinsic devices equals the input power) and neglecting the switching and output capacitor losses, . Supposing unity power factor (i_qr ≈ 0), and the output v_o at steady state, Then, from Eqs. (36.140) and (36.91), the following two sliding surfaces can be derived:

(36.141)

(36.142)

where β_{− 1} is the time constant of the desired first-order response of output voltage v_o(β T > 0). For the synthesis of the closed-loop control system, notice that the terms of Eq. (36.142) inside the square brackets can be assumed as the id reference current i_dr. Furthermore, from Eqs. (36.141) and (36.142), it is seen that the current control loops for i_d and i_q are needed. Considering Eqs. (36.138) and (36.136), the two sliding surfaces can be written

(36.143)

(36.144)

The switching laws relating the sliding surfaces (36.143, 36.144) with the switching variables γ_k are

(36.145)

The practical implementation of this switching strategy could be accomplished using three independent two-level hysteresis comparators. However, this might introduce limit cycles as only two line currents are independent. Therefore, the control laws (36.143, 36.144) can be implemented using the block diagram of Fig. 36.47a, with d, q/αβ [from Eq. (36.138)] and 1,2,3/αβ (from Eq. (36.136)) transformations and two 3-level hysteretic comparators with equivalent hysteresis e and p to limit the maximum switching frequency. A limiter is included to bound the i_d reference current to i_dmax, keeping the input line currents within a safe value. This helps to eliminate the nonminimum-phase behavior (outside sliding mode) when large transients are present while providing short-circuit proof operation.

FIGURE 36.47 (a) Sliding-mode PWM controller modulator for the unity power factor three-phase PWM rectifier and (b) α, β space vector representation of the PWM bridge rectifier leg voltages.

α, β Space Vector Current Modulator

Depending on the values of γ_k,the bridge rectifier leg output voltages can assume only eight possible distinct states represented as voltage vectors in the α, β reference frame (Fig. 36.47b) for sources with isolated neutral.

With only two independent currents, two 3-level hysteresis comparators, for the current errors, must be used in order to accurately select all eight available voltage vectors. Each three-level comparator can be obtained by summing the outputs of two comparators with two levels each. One of these two comparators (δ_Lα, δ_Lβ) has a wide hysteresis width and the other (δ_Nα δ_Nβ) has a narrower hysteresis width. The hysteresis bands are represented by e and ρ. Table 36.1 represents all possible output combinations of the resulting four two-level comparators, their sums giving the two 3-level comparators (δ_α, δ), P^lUS the voltage vector needed to accomplish the current tracking strategy (i_α,r –i_{α, β}) = 0 (ensuring (i_α,r –i_{α, β}) d(i_α,r –i_{α, β})/dt < 0, plus the γ_k variables and the α, β voltage components.

From the analysis of the PWM boost rectifier it is concluded that, if, for example, the voltage vector 2 is applied (γ₁ = 1, γ₂ = 1, γ₃ = 0), in boost operation, the currents i_α and i will both decrease. On the contrary, if the voltage vector 5(γ₁ = 0, γ₂ = 0, γ₃ = 0) is applied, the currents i_α and i will both increase. Therefore, vector 2 should be selected when both i_α and i currents are above their respective references, that is for δ_α = –1, δ = –1, whereas vector 5 must be chosen when both i_α and i currents are under their respective references, or for δ_α = 1, δ = 1. Nearly, all the outputs of Table 36.2 can be filled using this kind of reasoning.

TABLE 36.2 Two-level and three-level comparator results, showing corresponding vector choice, corresponding γ_k and vector α,β component voltages; vectors are mapped in Fig. 36.47b

The cases where δ_α = 0, δ_β = –1, the vector is selected upon the value of the i_α current error (if δ_Lα > 0 and δ_Nα < 0, then vector 2; if δ_Lα < 0 and δ_Nα > 0, then vector 3). When δ_α = 0, δ = 1, if δ_Lα > 0 and δ_Nα α 0, then vector 6, else if δ_Lα < 0 and δ_Nα > 0, then vector 5. The vectors 0 and 7 are selected in order to minimize the switching frequency (if two of the three upper switches are on, then vector 7, otherwise vector 0). The space-vector decoder can be stored in a lookup table (or in an EPROM), whose inputs are the four 2-level comparator outputs, and the logic result of the operations is needed to select between vectors 0 and 7.

PI Output Voltage Control of the Current-Mode PWM Rectifier

Using the α, β current-mode hysteresis modulators to enforce the i_d and i_q currents to follow their reference values, i_dr, i_qr (the values of L and C are such that the i_d and i_q currents usually exhibit a very fast dynamics compared with the slow dynamics of v_o), a first-order model (36.146) of the rectifier output voltage can be obtained from Eq. (36.73).

(36.146)

Assuming now a pure resistor load R₁ = v_o/i_o and a mean delay T_d between the i_d current and the reference i_dr continuous transfer functions result for the i_d current [i_d = i_dr (l + sT_d)^{− 1}] and for the v_o voltage [v_o = k_Ai_d/(1 + sk_B) with k_A and k_B obtained from Eq. (36.146)]. Therefore, using the same approach as Examples 36.6, 36.8, and 36.11, a linear PI regulator, with gains K_p and K_i (36.147), sampling the error between the output voltage reference v_or and the output v_o, can be designed to provide a voltage proportional (k_I) to the reference current .

(36.147)

These PI regulator parameters depend on the load resistance R₁, on the rectifier parameters (C, R_c, L, R), on the rectifier operating point γ_d, on the mean delay time T_d, and on the required damping factor τ. Therefore, the expected response can only be obtained with the nominal load and input voltages, the line current dynamics depending on the K_p and K_i gains.

Results (Fig. 36.48) obtained with the values V_RMS ≈ 70 V, L ≈ 1.1 mH, R ≈ 0.1ω, C ≈ 2000 μF with equivalent series resistance ESR ≈ 0.1ω (R_c ≈ 0.1ω), _R₁. ≈ 25ω, R₂ ≈ 12ω, β = 0.0012, K_p=1.2, K_i= 100, k_I = 1 showthat the α, β space vector current modulator ensures the current tracking needed (Fig. 36.48) [17]. The v_o step response reveals a faster sliding-mode controller and the correct design of the current mode/PI controller parameters. The robustness property of the sliding-mode controlled output v_o, compared to the current mode/PI, is shown in Fig. 36.49.

FIGURE 36.48 α, β space vector current modulator operation at near unity power factor: (a) simulation result (i_1r + 30; i_2r + 30; 2 i₁; 2 i₂ –30) and (b) experimental result (1 → i_1r, 2 → i_2r (10A/div); 3 → i₁, 4 → i₂ (5A/div)).

FIGURE 36.49 Transition from rectifier to inverter operation (i_o from 8 to –8 A) obtained by switching off IGBT S_α (Fig. 36.46) and using I_a = 16 A: (a) v_o –v_or [v] with sliding-mode control and (b) v_o –v_or [v] with current-mode/PI control.

EXAMPLE 36.15 Sliding-mode controllers for multilevel inverters

Diode-clamped multilevel inverters (Fig. 36.50) are the converters of choice for high-voltage high-power dc/ac or ac/ac (with dc link) applications as the active semiconductors (usually gate turn-off thyristors (GTO) or IGBT transistors) of n-level power conversion systems, must withstand only a fraction (normally U_cc/(n – 1)) of the total supply voltage U_cc. Moreover, the output voltage of multilevel converters, being staircaselike waveforms with n steps, features lower harmonic distortion compared with the two-level waveforms with the same switching frequency.

The advantages of multilevel converters are paid into the price of the capacitor supply voltage dividers (Fig. 36.51) and voltage equalization circuits into the cost of extra power supply arrangements (Fig. 36.51c) and into increased control complexity. This example shows how to extend the two-level switching law (36.97) to n-level converters and how to equalize the voltage of the capacitive dividers.

FIGURE 36.50 (a) Single-phase, neutral point–clamped, three-level inverter with IGBTs and (b) three-phase, neutral point–clamped, three-level inverter.

FIGURE 36.51 (a) Five-level (n = 5) diode-clamped inverter with IGBTs; (b) five-level (n = 5) flying capacitor converter; and (c) multilevel converter based on cascaded full-bridge inverters.

Considering single-phase three-level inverters (Fig. 36.50a), the open-loop control of the output voltage can be made using three-level SPWM. The two-level modulator, seen in Example 36.9, can be easily extended (Fig. 36.52a) to generate the γ_III command (Fig. 36.52b) to three-level inverter legs, from the two-level γ_II signal, either with a dedicated modulator or using the following relation:

FIGURE 36.52 (a) Three-level SPWM modulator schematic and (b) main three-level SPWM signals.

(36.148)

The required three-level SPWM modulators for the output voltage synthesis seldom consider the semiconductors and the capacitor voltage divider nonideal characteristics. Consequently, the capacitor voltage divider tends to drift, one capacitor being overcharged, the other discharged, and an asymmetry appears in the currents of the power supply. A steady-state error in the output voltage can also be present. Sliding-mode control can provide the optimum switching timing between all the converter levels, together with robustness to supply voltage disturbances, semiconductor nonidealities, and load parameters.

Sliding-Mode Surface and Switching Law

For a variable-structure system where the control input u_i(t) can present n levels, consider the n values of the integer variable and , dependent on the topology and on the conducting semiconductors. To ensure the sliding-mode manifold invariance condition (36.92) and the reaching mode behavior, the switching strategy γ(t_{k+ 1}) for the time instant t_{k+ 1}, considering the value of γ(t_k), must be

(36.149)

This switching law can be implemented as depicted in Fig. 36.53a and for 5 levels in Fig. 36.53b [40]. An alternative is shown in Fig. 36.53c, and named stability condition-based modulator [18], where the switching law (36.149) is directly used, calculating the sliding-mode surface and its time derivative, implemented as a discrete time variation. Both the sliding-mode surface and its time derivative are two level quantized and upon their values (obtained by half of their sum), the voltage level is increased (or decreased), until it reaches the maximum (or the minimum). Therefore, the output level is increased (or decreased) if the error and its derivative are both positive (or negative), with the upper limit λ_max = (n – 1)/2 and lower limit λ_min = –(n –1)/2.

FIGURE 36.53 (a) Multilevel sliding-mode PWM modulator with n-level hysteresis comparator with quantization interval e; (b) four hysteresis comparator implementation of a five-level switching law; (c) Stability condition-based multilevel modulator (one phase); and (d) Generalized sigma-delta n-level modulator.

Other implementations are possible (Fig. 36.53d) since in every modulation method, the generated pulse levels must have the same volt-second average of the fundamental sinusoidal (i.e. the integral over time of the n-level voltage waveform minus the value of the fundamental should be zero).

Control of the Output Voltage in Single-Phase Multilevel Converters

To control the inverter output voltage, in closed-loop, in diode-clamped multilevel inverters with n levels and supply voltage U_cc, a control law similar to Eq. (36.132), , is suitable.

Figure 36.54a shows the waveforms of a five-level sliding-mode controlled inverter: the input sinus voltage, the generated output staircase wave, and the sliding-surface instantaneous error. This error is always within a band centered around the zero value and presents zero mean value, which is not the case of sigma-delta modulators followed by n-level quantizers, where the error presents an offset mean value in each half period.

FIGURE 36.54 (a) Scaled waveforms of a five-level sliding-mode controlled single-phase converter showing the input sinus voltage v_PWMr the generated output staircase wave u_o and the value of the sliding surface S(e_xi, t); (b) scaled waveforms of a three-level neutral point–clamped inverter showing the capacitor voltage unbalance (shown as two near flat lines touching the tips of the PWM pulses); and (c) experimental results from a laboratory prototype of a three-level single-phase power inverter with the capacitor voltage equalization described.

Experimental multilevel converters always show capacitor voltage unbalances (Fig. 36.54b) due to small differences between semiconductor voltage drops and circuitry offsets. To obtain capacitor voltage equalization, the voltage error (v_c2 –U_CC/2) is fed back to the controller (Fig. 36.55a) to counteract the circuitry offsets. Experimental results (Fig. 36.54c) clearly show the effectiveness of the correction made. The small steady-state error, between the voltages of the two capacitors, still present, could be eliminated using an integral regulator (Fig. 36.55b).

FIGURE 36.55 (a) Multilevel sliding-mode output voltage controller and PWM modulator with capacitor voltage equalization and (b) sliding-mode output current controller with capacitor voltage equalization.

Figure 36.56 confirms the robustness of the sliding-mode controller to power supply disturbances.

FIGURE 36.56 Simulated performance of a five-level power inverter, with a U_cc voltage dip (from 2 to 1.5 kV). Response to a sinusoidal wave of frequency 50 Hz: (a) v_PWMr input; (b) PWM output voltage u_o; and (c) the integral of the error voltage, which is maintained close to zero.

Output Current Control in Single-phase Multilevel Converters

Considering an inductive load with current i_L, the control law (36.107) and the switching law of (36.159), should be used for single-phase multilevel inverters. Results obtained using the capacitor voltage equalization principle just described are shown in Fig. 36.57.

FIGURE 36.57 Operation of a three-level neutral point-clamped inverter as a sinusoidal current source: scaled waveforms of the output current sine wave reference i_Lr, the output current i_L, showing ripple, together with the PWM-generated voltage u_o, with nearly equal pulse heights, corresponding to the equalized dc capacitor voltages u_C1 and u_C2.

EXAMPLE 36.16 Sliding-mode controllers for three-phase multilevel inverters

Three-phase n-level inverters (Fig. 36.58) are suitable for high-voltage, high-power dc/ac applications, such as modern high-speed railway traction drives, as the controlled turn-off semiconductors must block only a fraction [normally U_DC/(n – 1)] of the total supply voltage U_DC.

This example presents a real-time modulator for the control of the three output voltages and capacitor voltage equalization, based on the use of sliding mode and space vectors represented in the α, frame. Capacitor voltage equalization is done with the proper selection of redundant space vectors.

FIGURE 36.58 confirms the robustness of the sliding-mode controller to power supply disturbances.

Output Voltage Control in Multilevel Converters

To guarantee the topological constraints of this converter and the correct sharing of the U_DC voltage by the semiconductors, the switching strategy for the k leg (k ε {1, 2, 3}) must ensure complementary states to switches S_k1and S_k3. The same restriction applies for S_k2 and S_k4. Neglecting switching delays, dead times, on-state semiconductor voltage drops, snubber networks, and power supply variations, supposing small dead times and equal capacitor voltages U_C1 = U_C2 = U_DC/2, and using the time-dependent switching variable γ_k(t), the leg output voltage U_k (Fig. 36.58) will be U_k = γ_k(t) U_DC/2, with

(36.150)

The converter output voltages U_Sk of vector U_S can be expressed as follows:

(36.151)

The application of the Concordia transformation U_S1,2,3 = [C]U_Sαβo(Eq. (36.152) to Eq. (36.151))

(36.152)

gives the output voltage vector in the a, coordinates U_Sα,β:

(36.153)

where

(36.154)

The output voltage vector in the α,β coordinates U_Sα,β is discontinuous. A suitable state variable for this output can be its average value during one switching period:

(36.155)

The controllable canonical form is

(36.156)

Considering the control goal and Eq. (36.91), the sliding surface is

(36.157)

To ensure reaching mode behavior, and sliding-mode stability (36.92), as the first derivative of Eq. (36.157), S(e_α,β t) is

(36.158)

The switching law is

(36.159)

This switching strategy must select the proper values of U_Sα,β from the available outputs. As each inverter leg (Fig. 36.58) can deliver one of the three possible output voltages (U_dc/2; 0; –U_DC/2), all the 27 possible output voltage vectors listed in Table 36.3 can be represented in the α, frame of Fig. 36.59 (in per units, 1 p.u. = U_DC). There are nine different levels for the α space vector component and only five for the component. However, considering any particular value of α (or) component, there are at most five levels available in the remaining orthogonal component. From the load viewpoint, the 27 space vectors of Table 36.3 define only 19 distinct space positions (Fig. 36.59).

TABLE 36.3 Vectors of the three-phase three-level converter, switching variables γ_k, switch states s_kj, and the corresponding output voltages, line to neutral point, line-to-line, and α, β components in per units

FIGURE 36.59 Three-phase, neutral point clamped, three-level inverter with IGBTs.

To select one of these 19 positions from the control law (36.157) and the switching law of Eq. (36.159), two 5-level hysteretic comparators (Fig. 36.53b) must be used (5² = 25). Their outputs are the integer variables λ_α and λ, denoted λ_α, (λ_α, λ ε{– 2; – 1; 0;1; 2}) corresponding to the five selectable levels of G_α and G_β. Considering the sliding-mode stability, λ_αβ,, at time step j + 1, is given by Eq. (36.160), knowing their previous values at step j. This means that the output level is increased (decreased) if the error and its derivative are both positive (negative), provided the maximum (minimum) output level is not exceeded.

(36.160)

The available space vectors must be chosen not only to reduce the mean output voltage errors but also to guarantee transitions only between the adjacent levels, to minimize the capacitor voltage unbalance, to minimize the switching frequency, to observe minimum on or off times if applicable, and to equally stress all the semiconductors.

Using Eq. (36.160) and the control laws S(e_α,β,t) Eq. (36.157), Tables 36.4 and 36.5 can be used to choose the correct voltage vector in order to ensure stability, output voltage tracking, and DC capacitor voltage equalization. The vector with α, components corresponding to the levels of the pair λ_β,λ_α is selected, provided that the adjacent transitions on inverter legs are obtained. If there is no directly corresponding vector, then the nearest vector guaranteeing adjacent transitions is selected. If a zero vector must be applied, then one of the three zero vectors (1, 14, 27) is selected to minimize the switching frequency. If more than one vector is the nearest, then one of them is selected to equalize the capacitor voltages, as shown next.

TABLE 36.4 Switching table to be used if (U_c1 –U_c2) >ε_eu in the inverter mode, or (U_c1 — U_c2 ) < —e_eu in the regenerative mode, showing vector selection upon the variables λ_α,λ_β

TABLE 36.5 Switching table to be used if (U_c1 –U_c2 ) > εeU in the regenerative mode, or (U_c1 — U_c2 ) < –ε_eu in the inverter mode, showing vector selection upon the variables λ_α,λ_β

DC Capacitor Voltage Equalization

The discrete values of λ_α,β allow 25 different combinations. As only 19 are distinct from the load viewpoint, the extra ones can be used to select vectors that are able to equalize the capacitor voltages (U_C1 = U_C2 = U_DC/2).

Considering the control goal U_C1 = U_C2, since the first derivatives of U_C1 and U_C2 Eq. (36.161) directly depend on the γ_k(t) control inputs, from Eq. (36.91), the sliding surface is given by Eq. (36.162), where k_u is a positive gain.

(36.161)

(36.162)

The first derivative of U_c1 –U_c2 (the sliding surface) is (Fig. 36.58 with C₁ = C₂ = C):

(36.163)

To ensure reaching mode behavior and sliding-mode stability, from Eq. (36.92), considering a small enough e_Uc error, ϵ_eU, the switching law is

(36.164)

From circuit analysis, it can be seen that vectors {2, 5, 6, 13, 17, 18} result in the discharge of capacitor C₁, if the converter operates in inverter mode, or in the charge of C₂, if the converter operates in boost-rectifier (regenerative) mode. Similar reasoning can be applied for vectors {10, 11, 15, 22, 23, 26} and capacitor C₂ since this vector set give i_n currents with opposite sign relatively to the set {2, 5, 6, 13, 17, 18}. Therefore, considering the vector the switching law is:IF (U_C1-U_C2)> ε_eU

IF (U_C1-U_C2)> –ε_eU

For example, consider the case where U_c1 > U_c2 + ϵ_eU Then, the capacitor C₂ must be charged and Table 36.4 must be used if the multilevel inverter is operating in the inverter mode or Table 36.5 for the regenerative mode. In addition, when using Table 36.4, if λ_α = – 1 and λ = – 1, then vector 13 should be used.

Experimental results shown in Fig. 36.61 were obtained with a low-power, scaled-down laboratory prototype (150 V, 3kW) of a three-level inverter (Fig. 36.60) controlled by two four-level comparators plus described capacitor voltage equalizing procedures and EPROM-based lookup Tables 36.3–36.5. Transistors IGBT (MG25Q2YS40) were switched at frequencies near 4 kHz, with neutral clamp diodes 40 HFL, C₁ ≈ C₂ ≈ 20 mF. The load was mainly inductive (3× 10 mH, 2 ω).

FIGURE 36.61 (a) Experimental results showing phase and line voltages and (b) harmonic spectrum of output voltages.

FIGURE 36.60 Output voltage vectors (1 to 27) of three-phase, neutral-clamped three-level inverters, in the α, β frame.

The inverter number of levels (three for the phase voltage and five for the line voltage), together with the adjacent transitions of inverter legs between levels, are shown in Fig. 36.61a and, in detail, in Fig. 36.62a.

FIGURE 36.62 Experimental results showing (a) the transitions between adjacent voltage levels (50 V/div; time 20μs/div) and (b) performance of the capacitor voltage equalizing strategy; from top trace to bottom: 1 is the voltage reference input; 2 is the power supply voltage; 3 is the midpoint capacitor voltage, which is maintained close to Udc/2; 4 is the output current of phase 3(2 A/div; 50 V/div; 5 ms/div).

The performance of the capacitor voltage equalizing strategy is shown in Fig. 36.62b, where the reference current of phase 1 and the output current of phase 3, together with the power supply voltage (U_DC ≈ 100 V) and the voltage of capacitor C₂ (U_c2), can be seen. It can be noted that the U_c2 voltage is nearly half of the supply voltage. Therefore, the capacitor voltages are nearly equal. Furthermore, it can be stated that without this voltage equalization procedure, the three-level inverter operates only during a brief transient, during which one of the capacitor voltages vanishes to nearly zero volt and the other is overcharged to the supply voltage. Figure 36.61b shows the harmonic spectrum of the output voltages, where the harmonics due to the switching frequency (≈ a 4.5 kHz) and the fundamental harmonic can be seen.

Online Output Current Control in Multilevel Inverters

Considering a standard inductive balanced load (R,L) with electromotive force (u) and isolated neutral, the converter output currents i_k can be expressed

(36.165)

Now analyzing the circuit of Fig. 36.58, the multilevel converter-switched state-space model can be obtained:

(36.166)

The application of the Concordia matrix Eq. (36.152) to Eq. (36.166) reduces the number of the new model equations (Eq. (36.167)) to two since an isolated neutral is assumed.

(36.167)

The model Eq. (36.167) of this multiple-input multiple-output system (MIMO) with outputs i_α, i reveals the control inputs U_sα, U_s, dependent on the control variables γk (t).

From Eqs. (36.167) and (36.91), the two sliding surfaces S(e_α,t) are

(36.168)

The first derivatives of Eq. (36.167), denoted are

(36.169)

Therefore, the switching law is

(36.170)

These switching laws are implemented using the same α, vector modulators described above in this example.

Figure 36.63a shows the experimental results. The multilevel converter and proposed control behavior are obtained for step inputs (4 to 2 A) in the amplitude of the sinus references with frequency near 52 Hz (U_DC ≈ 150V). Observe the tracking ability, the fast transient response, and the balanced three-phase currents. Figure 36.63b shows almost the same test (step response from 2 to 4A at the same frequency), but now the power supply is set at 50 V and the inductive load was unbalanced (30% on resistor value). The response remains virtually the same, with tracking ability, almost no current distortions due to dead times or semiconductor voltage drops. These results confirm experimentally that the designed controllers are robust concerning these nonidealities.

FIGURE 36.63 Step response of the current control method: (a) step from 4 to 2 A. Traces show the reference current for phase 1 and the three output currents with 150V power supply (5 A/div; time scale 20 ms/div) and (b) step from 2 to 4 A in the reference amplitude at 52 Hz. Traces show the reference current for phase 1 and the three output currents with 50V power supply.

EXAMPLE 36.17 Sliding-mode vector controllers for matrix converters

Matrix converters are all silicon ac/ac switching power converters, able to provide variable amplitude almost sinusoidal output voltages, almost sinusoidal input currents, and controllable input power factor [19]. They seem to be very attractive to use in ac drives speed control and in applications related to power-quality enhancement. The lack of an intermediate energy storage link, their main advantage, implies an input/output coupling that increases the control complexity.

This example presents the design of sliding-mode controllers considering the switched state-space model of the matrix converter (nine bidirectional power switches), including the three-phase input filter and the output load (Fig. 36.64).

FIGURE 36.64 An ac/ac matrix converter with input lCr filter.

Output Voltage Control

Ideal three-phase matrix converters are obtained by assembling nine bidirectional switches, with the turn-off capability, to allow the connection of each one of the input phases to any one of the output phases (Fig. 36.64). The states of these switches are usually represented as a nine-element matrix S (Eq. (36.171)), in which each matrix element, S_kj k, j ε {1, 2, 3}, has two possible states: S_kj = 1 if the switch is closed (ON) and S_kj = 0 if it is open (OFF). Only 27 switching combinations are possible (Table 36.6), as a result of the topological constraints (the input phases should never be short circuited and the output inductive currents should never be interrupted), which implies that the sum of all the S_kj of each one of the matrix, k rows must always equal 1 (Eq. (36.171)).

(36.171)

TABLE 36.6 Switching combinations and output line voltage/input current state-space vectors

Based on matrix S, output voltages related to input neutral v_on1, v_on2, v_on3 and line voltages v₀₁₂, v₀₂₃, v₀₃₁ can be expressed in terms of matrix converter input phase voltages v_i1, v_i2, v_i3.

Input currents i_i1, i_i2, i_i3, can be expressed as a function of output currents i_0l, i₀₂, i₀₃ :

(36.172)

The application of Concordia transformation [X_α,_,0]^T = C^T[X_a,b,c]^T to the output line voltages of Eq. (36.172) results in the output voltage vector:

(36.173)

where v_cαβ are the input filter capacitor voltage and ρ_vαα; ρ_vαβ,ρ_vβα ρ_vββ are functions of the ON/OFF state of the nine S_kj switches:

(36.174)

The average value of the output voltage, in α coordinates, during one switching period is the output variable to be controlled (since v_olαβ is discontinuous) [20].

(36.175)

Considering the control goal the sliding surface S(e_αβ,t)(k_αβ < 0) is

(36.176)

The first derivative of Eq. (36.176) is

(36.177)

As the sliding-mode stability is guaranteed if S_α(e_αβ,t) , the criterion to choose the output line voltages state-space vectors is

(36.178)

This implies that the sliding mode is reached only when the vector applied to the converter has the desired amplitude and angle.

According to Table 36.6, the 6 vectors of group I have fixed amplitude but time varying phase, the 18 vectors of group II have variable amplitude and vectors of group III are null. Therefore, from the load viewpoint, the 18 highest amplitude vectors (6 vectors from group I and 12 vectors from group II) and one null vector are suitable to guarantee the sliding-mode stability.

Therefore, if two three-level comparators (C_α ε {- 1, 0, 1}) are used to quantize the deviations of Eq. (36.178) from zero, the nine output voltage error combinations (3³) are not enough to guarantee the choice of all the 19 available vectors. The extra vectors may be used to control the input power factor. As an example, if the output voltage error is quantized as C_α = 1, C = 1, at sector V_il (Fig. 36.65), the vectors –3, + 1, or 1 g might be used to control the output voltage. The final choice would depend on the input current error.

FIGURE 36.65 (a) Input voltages and their corresponding sector and (b) representation of the output voltage state-space vectors when the input voltages are located at sector V_i1.

Output Current Control

For some applications, it is more useful to control the output currents, which implies some changes on the previously designed controllers. From Fig. 36.64, the output currents can be obtained as a function of the phase voltages applied to the load:

(36.179)

As the output currents are state variables, with a strong relative degree of 1, the sliding surfaces should depend directly on their errors:

(36.180)

The state space vectors should be chosen to guarantee the stability criterion , according to:

The output voltage phase vectors can be obtained from the output voltage line vectors of Table 36.6, using the well-known relations between three phase lines and phase voltages.

(36.181)

As expected, the resultant output voltage phase vectors will have an amplitude (3 lower than the voltage line vectors of Table 36.6 and a lagging phase of π/6. As an example, from Fig. 36.65b, this will result in a –π/6 rotation of all the voltage vectors represented.

Therefore, if two three level comparators (C_α ε {–1, 0, 1}) are used to quantize the deviations of Eq. (36.180)) from zero, if the output current error is quantized as C_α = 1, C = 1, at sector Vi l (Fig. 36.65), the vectors + 9 or –7 might be used to control the output current. The final choice would depend on the input current error.

Input Power Factor Control

Assuming that the source is a balanced sinusoidal three-phase voltage supply with frequency ω_i, the switched state-space model equations of the converter input filter are obtained in 123 coordinates.

(36.182)

To control the input power factor, a reference frame synchronous with one of the input voltages v_ig1 may be used applying the Blondel–Park transformation to the matrix converter switched state-space model (Eq. (36.183)), where ρ_idd, ρ_idq, ρ_iqd, ρ_iqq are functions of the ON/OFF states of the nine S_kj switches:

(36.183)

As a consequence, neglecting ripples, all the input variables become time invariant, allowing a better understanding of the sliding-mode controller design, as well as the choice of the most adequate state-space vector. Using this state-space model, the input i_igd and i_igq currents are

(36.184)

The input power factor controller should consider the input-output power constraint (Eq. (36.185)) (the converter losses and ripples are neglected), obtained as a function of the input and output voltages and currents (the input voltage v_igq is equal to zero in the chosen dq rotating frame). The choice of one output voltage vector automatically defines the instantaneous value of the input i_igd current.

(36.185)

Therefore, only the sliding surface associated to the i_igq current is needed, expressed as a function of the system state variables and based on the state-space model determined in Eq. (36.183):

(36.186)

As the derivative of the input i_igd (t) current depends directly on the control variables S_iq(e_iq,t) the sliding function ρ_iqd,ρ_iqq will depend only on the input current error e_iq=i_igqref

(36.187)

As the sliding-mode stability is guaranteed if S_αβ(e_αβ,t) the criterion to choose the state-space vectors is [20]

(36.188)

Also, to choose the adequate input current vector, it is necessary: (a) to know the location of the output currents, as the input currents depend on the output currents location (Table 36.6); (b) to know the dq frame location. As in the chosen frame (synchronous with the v_ig1 input voltage), the dq-axis location depends on the v_ig1 input voltage location, the sign of the input current vector i_ig1 component can be determined knowing the location of the input voltages and the location of the output currents (Fig. 36.66).

FIGURE 36.66 (a) Output currents and their corresponding sector; (b) representation of input current state-space vectors, when the output currents are located at sector I₀1. The dq-axis is represented considering that the input voltages are located at sector V_i1.

Considering the previous example, at sector V_i 1 (Fig. 36.65), for an error of C_α = 1 and C = 1, vectors –3, + 1 or 1g might be used to control the output voltage. When compared, at sector I₀1 (Fig. 36.66b), these three vectors have positive i_d components and, as a result, will have a similar effect on the input i_ig1 current. However, they have a different effect on the i_ig1 current: vector –3 has a positive i_ig1 component, vector + 1 has a negative i_iq component and vector 1 g has a nearly zero i_iq component. As a result, if the output voltage errors are C_α = 1 and C = 1, at sectors V_il and I₀1, vector –3 should be chosen if the input current error is quantized as C_iq= 1 (Fig. 36.66b), vector + 1 should be chosen if the input current error is quantized as C_iq = –1 and if the input current error is C_iq = 0, vector 1 g or –3 might be used.

When the output voltage errors are quantized as zero C_α = 0, the null vectors of group III should be used only if the input current error is C_iq = 0. Otherwise (being C_iq ≠ 0), the lowest amplitude voltage vectors ({+ 2,–8,+ 5,–2,+ 8,–5} at sector Vi l of Fig. 36.65b), that were not used to control the output voltages, might be chosen to control the input i_igq current as these vectors may have a strong influence on the input current component (Fig. 36.66b).

To choose one of these six vectors, only the vectors located as near as possible to the output voltages sector (Fig. 36.67) are chosen (to minimize the output voltage ripple), and a five level comparator is enough. As a result, there will be 9 × 5 = 45 error combinations to select 27 space vectors. Therefore, the same vector may have to be used for more than one error combination.

FIGURE 36.67 (a) Output voltages and their corresponding sector and (b) representation of the lowest amplitude output voltage vectors, when the input voltages are located at sector Vo1.

With this reasoning, it is possible to obtain Table 36.7 for sector V_i1, IO 1, and VO 1 and generalize it for all the other sectors.

TABLE 36.7 State-space vectors choice at sector V_i1, I₀1, and V₀1

The experimental results shown in Fig. 36.68 were obtained with a low-power prototype (1kW), with two three-level comparators and one five-level comparator, associated to an EPROM lookup table. The transistors IGBT were switched at frequencies near 10 kHz.

FIGURE 36.68 Dynamic responses obtained with a three-phase load: (a) output reference voltage step (R = 7Ω,L=15 mH, f_o = 20 Hz): input voltage v_ig1 (CH1), input current v_ig1 (CH3), output reference voltage v_o23ref(t) (CH4), and output current i_o1(t) (CH2); (b) input reference current i_igqref(t) step: input voltage v_ig1(t) (CH1), input current i_ig1(t) (CH3), input reference current i_igqref(t) (CH2), and output current i_o1(t) (CH4).

The results show the response to a step on the output voltage reference (Fig. 36.68a) and on the input reference current (Fig. 36.68b), for a three-phase output load (R = 7ω, L= 15mH), with k_a = 100 and k_iq=2. It can be seen that the matrix converter may operate with a near unity input power factor (Fig. 36.68a, f_O = 20Hz), or with lead/lag power factor (Fig. 36.68b), guaranteeing very low ripple on the output currents, a good tracking capability and fast transient response times.

Also, some simulation results were obtained for the output current-controlled matrix converter. The results (Fig. 36.69a) show the response to a step on the output current reference at t = 0.22 s, a step of the output current frequency at t= 0.28 s and a step at the input i_igq current at t = 0.34 s, for a three phase output load (R = 3ω,L = 30mH), with k_ioαβ and k_iq Again, these results show that matrix converter may operate with lead/lag power factor, guaranteeing very low ripple on the output currents, a good tracking capability, and fast transient response times for both input and output currents.

FIGURE 36.69 Dynamic responses obtained with a three-phase load (R = 3Ω,L = 30mH) for a step in the output reference current amplitude at t = 0.22s, in the output reference current frequency at t = 0.28s, and in the input i_gq current at t=0.34s; (a) output reference current i_gq and output current i_o1(t) (b) input grid voltage v_ig1 and input grid current i_ig1) (c) input reference current i_gqref(t and input grid current i_gqref(t.

EXAMPLE 36.18 PI linear controllers for matrix converters

For comparison purposes, a Pi-based controller using a PWM (pulse width modulation) technique is designed. From Eq. (36.171), the modulation indexes m_ij associated to the matrix converter nine switches are represented as a nine-element matrix M (t) (Eq. (36.189)) [21].

(36.189)

These modulation indexes are used to synthesize the output voltages as a function of input voltages Eq. (36.190), and input currents as a function of output load currents (36.190).

(36.190)

However, assuming a balanced source system with input and output neutral wires not connected and restriction (36.189), the modulation indexes matrix may be reduced to a four element matrix Eq. (36.191) [22].

(36.191)

Based on Eqs. (36.189), (36.190), and (36.181), input currents are obtained as a function of output currents.

(36.192)

From Eqs. (36.190) and Eq. (36.190), output load phase voltages Eq. (36.193) can be directly obtained from input phase voltages using a four modulation indexes matrix Eq. (36.194) based on Eq. (36.191).

(36.193)

(36.194)

Assuming ideal input filtering, phase voltages Eq. (36.195) applied to matrix converter should be approximately equal to grid voltages.

(36.195)

Also, assuming ideal output filtering, output currents Eq. (36.196) should be nearly equal to their fundamental harmonics (with frequency ω_O and displacement factor ϕ_o).

(36.196)

If switching frequencies are much higher than input and output frequencies (f_s f_i and f_s f_O), then input currents Eq. (36.197) and output load voltages Eq. (36.198) should be approximately equal to their references:

(36.197)

(36.198)

Applying Concordia and Park transformation [23] to Eq. (36.192) and Eq. (36.193) and choosing a reference frame synchronous with input phase voltages (Θ_i = ω_it) for all the input variables and a reference frame synchronous with output phase voltages (T_O = ω_Ot) for all the output variables, then three-phase input and output variables (Eq. (36.199) and Eq. (36.201)) may become time invariant.

(36.199)

(36.200)

From Eq. (36.199) and Eq. (36.200), in the new coordinate frame, input phase voltages should be given by Eq. (36.201) and target input currents should be equal to Eq. (36.202):

(36.201)

(36.202)

Target output load phase voltages (36.203) and output currents Eq. (36.204) should be

(36.203)

(36.204)

From Eq. (36.199), in the new coordinate frame, matrix converter modulation indexes are given by Eq. (36.205):

(36.205)

From Eq. (36.199), using input voltages Eq. (36.201), two independent control actions based on different modulation indexes and allowing the independent control of each output voltage component are obtained.

(36.206)

Solving Eq. (36.206) using target output voltages Eq. (36.203), it is possible to calculate γ_dd Eq. (36.207) and γ_qd Eq. (36.208) modulation indexes.

(36.207)

(36.208)

Input/output power constraint can be verified Eq. (36.209), calculating current from Eqs. (36.200) and (36.205), assuming an ideal matrix converter without losses and input/output ideal filtering, using the previously calculated modulation indexes γ_dd Eq. (36.207) and γ_qd Eq. (36.208), input target currents Eq. (36.202) and output currents Eq. (36.204).

(36.209)

From Eq. (36.209) and Eq. (36.206), it is possible to conclude that

From Eq. (36.200) and Eq. (36.205), to guarantee decoupled i_id and i_iq current components, then γ_dq and γ_qq modulation indexes should be given by Eq. (36.210) and Eq. (36.211).

(36.210)

(36.211)

From the previously defined modulation indexes and Eq. (36.200), input i_iq current component can be determined by Eq. (36.212):

(36.212)

Constant k (Eq. (36.213)) is calculated from Eq. (36.212) using output currents (Eq. (36.204)), target input currents (Eq. (36.202)) and input/output power constraint (Eq. (36.209)):

(36.213)

In the previously defined reference frame, the modulation indexes matrix, Eq. (36.214), is time invariant and can be obtained from Eqs. (36.207), (36.208), (36.210), (36.211), and Eq. (36.213).

(36.214)

As a conclusion, according to Eq. (36.206) and Eq. (36.212) there are three possible control actions:

Output Currents Controller

In order to design the output currents controllers, it is assumed that matrix converter is feeding a three-phase general RLE load (Fig. 36.64). In the synchronized dq coordinate frame output currents are given by Eq. (36.215).

(36.215)

From Eq. (36.215), assuming nearly constant E_d and E_q voltages, H_dq (Eq. (36.216)) command voltages will guarantee that i_od and i_oq output currents follow their references.

(36.216)

From Eq. (36.206) and H_dq command variables (Eq. (36.216)), matrix converter γ_dd and γ_dq modulation indexes (Eq. 36.217)) are calculated as functions of H_dq command voltages, allowing d and q control actions decoupling (Fig. 36.70).

FIGURE 36.70 Decoupled block diagram of the current controllers.

(36.217)

Often the crossed terms ωLi_od and ωLi_oq do not have a significant weight and can be neglected.

Matrix converter should be defined as having an unitary gain and a dominant pole dependent on the average delay time T_d (usually one half of the switching period) [24].

(36.218)

The first order dynamics load may be represented as in Eq. (36.219), where R is the load resistance and τ is the load time constant.

(36.219)

Usually the zero of the compensator is chosen to cancel the pole introduced by the load.

(36.220)

From Eqs. (36.218), (36.219), and Fig. 36.70, the closed loop transfer function is given by

(36.221)

Comparing this transfer function with a second-order system in the canonical form, then ω² n = K_i/(T_p RT_d), where ω_n is the natural frequency and 2τω_n= 1/T_d, where τ is the damping factor. Choosing to minimize the closed loop response overshoot and rise time, it is possible to calculate T_p (Eq. 36.222)).

(36.222)

Input Current Controller

Due to the input/output power constraint (Eq. (36.209)), input i_id current depends on the same modulation indexes as output voltages. On the contrary, i_iq is linearly independent from output voltages and i_id input current and depends on variable k (Eq. (36.212)).

(36.223)

Using the expected values of γ_qd (Eq. (36.208)) and γ_dd (Eq. (36.207)) modulation indexes and the target output currents (Eq. (36.204)) in Eq. (36.223), input i_iq current is shown to depend linearly on variable k.

(36.224)

Neglecting the input filter dynamics, a nearly unitary matrix converter input power factor is obtained for k= 0 and, from Eq. (36.211), for γ_qq= 0. However, as the input filter is not ideal, this will usually result in leading power factor on the grid side connection. To control matrix converter input power factor, a simple integral controller would be enough, as the matrix converter input currents have no associated dynamics, depending directly on the switches states. However, due to the input filter capacitive characteristic, in general, and depending on the operating power conditions, the input power factor on the grid connection will be leading when compared to the controlled matrix converter input power factor.

To consider the input filter dynamics in the controller design, it is necessary to relate the grid current i_igq to the matrix converter input current i_iq The resultant second-order transfer function can be further used to design an adequate higher order input current linear controller.

Results

Considering an output three-phase RL load R = 3ω and L= 30mH, some results were obtained for a step of the output current amplitude at t= 0.22s, a step of the output current frequency at t= 0.28s and a step of matrix converter input i_iqcurrent at t= 0.34s (Fig. 36.71). The input filter dynamics was not considered and an integral controller was used to control matrix converter input power factor.

FIGURE 36.71 (a) Dynamic responses obtained with a three phase load (R = 3 Ω, L= 30 mH) for a step in the output reference current amplitude at t = 0.22s, in the output reference current frequency at t = 0.28s and in the input i_iq current at t = 0.34s; (b) output reference current i_olref(t) and output current i_o1(t) (c) input grid voltage v_ig1(t) and input grid current i_ig1(t) (d) matrix converter input reference current i_iqref(t) and matrix converter input filtered current i_iq(t) (e) input reference current i_igqref(t) and input grid current i_igq(t).

These results were obtained using the block diagram of Fig. 36.70, assuming that matrix converter model is characterized by T_d= l/(2^* f_m), where f_m, the triangular modulator frequency, is f_m = 10 kHz. They show that the designed controllers guarantee a good response to step changes in the references: the output current i_o1 and its reference i_o1ref are almost coincident (Fig. 36.71a) and the matrix converter input current i_iq follows its reference value i_iqref As expected, due to the input filter, the grid current is slightly in advance when compared to the i_iqref reference current or when compared to matrix converter input current i_iq.

36.4.1 Introduction

Predictive optimum controllers are based on linear optimum control systems theory and aim to solve the minimization problem of a cost functional [14, 25]. Predictive optimum Controllers automatically ensure closed-loop stability and some degree of robustness concerning parameter variation and system disturbances while being easy to numerically implement [14, 25].

Predictive controllers can be designed to minimize switching power converter state output errors, together with the switching frequency, being useful to control converter state variables, such as currents, voltages or powers, even with coupled dynamics. Several approaches to the predictive control of switching power converters are being developed and obtained results show improvements comparatively to standard modulation techniques or to sliding-mode control [26–35].

36.4.2 Principles of Nonlinear Predictive Optimum Control

The first step in designing a predictive controller is to obtain a detailed nonlinear direct dynamic model (including bounds, saturations, hysteresis or other effects) of the switching power converter. This model must contain just enough detail for the converter dynamics to allow the model to forecast, in real time and with negligible error, from initial conditions the future behavior of the converter state-space variables and load, over the next sampling steps, with the converter subjected to each possible switching state (or vector).

The next step is to define a cost functional to evaluate the error cost of the application of every vector to the converter. The cost functional contains the weighted control errors and usually is defined as a norm of the error vector, and/or weights control efforts, such as the switching frequency.

Known, measured (sampled), or estimated the initial conditions of the state variables, the predictive control algorithm executes by applying every possible control vector to the model. The predicted values of the state space variables are used to evaluate the controlled output errors corresponding to each one of the available vectors. The errors are weighted and the value of the cost functional is calculated and stored as a vector.

After applying all the vectors to the model, the minimum of the cost functional vector indicates which switching vector must be applied to the converter in order to nearly zero the output errors in the next sampling step, i.e. the next control action of the switching power converter is the vector that obtained the least value of the cost functional. Then, the algorithm is executed again in the next sampling step.

This procedure needs a powerful microprocessor to execute all the predictions in real time using fixed sampling steps (usually within 10–30 μs).

This control technology, here called nonlinear predictive optimum control is feasible in switching power converters, as they have a reduced set of control actions: from just 2 in simple dc-dc converters, to eight vectors in three-phase PWM inverters, or 27 in three-level, three-phase multilevel or matrix converters. Therefore, for these converters, the optimization problem is reduced to the calculation and selection of the vector that generates the minimum value of the cost functional vector. However, for multilevel converters with higher number of levels, the number of vectors steeply increases (125 in five-level three-phase converters). This greatly increases the cost of the control system since the microprocessor must execute the 125 predictions using a nonlinear model roughly within the same 10-30 (is sampling time. A faster alternative to the predictive optimum controller is also proposed.

36.4.3 Principles of Nonlinear Fast Predictive Optimum Control

The above algorithm needs to evaluate Eqs. (36.232) through (36.235) m times, which can be time consuming for three-phase multilevel converters with five or more levels.

To reduce the microprocessor computational task, the use of a subset of either adjacent vectors (for minimum switching frequency), or vectors that can zero one or several harmonics, is an alternative to reduce the number of candidate vectors to be analyzed in real time.

Another possibility is to use the converter inverse dynamics to obtain a fast predictive optimum controller, which is here introduced.

From the output equation of the state-space model (36.225), it can be written:

(36.237)

Note also that if we suppose that the control objective is attained at sampling time t+h, then x_t+h = x_ref, and from Eq. (36.229):

(36.238)

Using Eq. (36.237) in Eq. (36.238) and the result in the state equation of (36.225), the converter inverse dynamics, needed to estimate the necessary control vector u_t+h, can be obtained:

(36.239)

This equation defines the needed components of the control vector u_t+h. An alternative way to generate the needed control vector u_t+h is to use the controllability canonical form of the converter dynamics to compute the equivalent control, similar to Eq. (36.83).

Seldom, the converter will be able to replicate the vector in Eq. (36.239) since it is a continuously variable equivalent control vector, and the converter outputs only a reduced set of control vectors. Therefore, the control vector u_t+h might be obtained as a kind of space vector modulation or found by minimization of a quadratic cost functional, based on the norm of the difference vector between the needed u_t+h and the available set of vectors u_j:

(36.240)

Then, this functional is computed for all U_j to find the vector that leads to the minimum value of the cost functional (36.240) accordingly to Eq. (36.236).

The fast predictive optimum control needs much less computational time, as it only evaluates (36.239) one time per step and (36.240) m times. However, preliminary inspection of Eq. (36.239) indicates that it can only be directly applied to converters with input and output circuits that have time-invariant dynamic matrices.

36.4.4 Examples: Predictive Control of Multilevel Inverters and Matrix Converters

EXAMPLE 36.19 Non-linear predictive optimum control of multilevel inverters

Consider the multilevel inverter of Fig. 36.58 with three-phase ac current direct dynamics in the αβ plane given by Eqs. (36.167) and (36.161), which can be rewritten as

(36.241)

Where ;, i∈{1,2}.

The optimal controller is designed to choose the best output voltage vector able to minimize both the ac current, i_α and i_β, errors and the input dc capacitor U_C1 and U_C2 voltage unbalance.

Predictive Equations for AC α Currents

To design a real-time optimal predictive controller, the obtained α converter model (36.167) will be solved to predict the state variable values at the next sampling period, for all the 27 available vectors, assuming a sampling time h small enough so that U_C1, U_C2, and u_ep, p∈ {α,β}, can be considered nearly constant during step time h. Therefore, the simplified model is decoupled and, using Eq. (36.229) in Eq. (36.167), the αβ currents i_pt+h(p∈{α,β}) prediction is obtained:

(36.242)

Where the perturbations u_ep can be estimated using Eq. (36.233).

Predictive Equations for DV Capacitor Voltage Unbalance

To predict the capacitor voltage difference or unbalance, U_C1 –U_C2, the corresponding dynamic Eq. (36.241) must be solved. Assuming h small enough, C₁ = C₂ = C, and small control errors, it can be assumed that the ac currents follow their references, e.g. i_pi+h=i_pref Then, from Eqs. (36.241) and (36.229),

(36.243)

Quadratic Cost Functional

In NPC multilevel converters operated as ac current sources, three independent variables can be controlled, such as two ac currents, i_α(t), i_β(t), and the dc capacitor voltage unbalance U_C1 –U_C2 Therefore, the tracking error vector is defined as

(36.244)

The ac current references i_αref and i_βref are obtained one sample step forward (using (36.233)) to avoid the delay time due to processor calculation time.

The main objective of the predictive optimum controller is the minimization of both the ac currents errors and the capacitor voltage difference using the following quadratic cost functional:

(36.245)

This functional is calculated for all the multilevel 27 available vectors and the resultant value stored (Eqs. (36.242)-(36.245) are calculated 27 times). Using the procedure outlined in Eq. (36.236), the vector leading to the minimum value of the cost functional is selected to be applied to the multilevel converter.

Results

The above procedure was implemented in a PowerPC-based board (DS1103) to execute in h = 25μs. The following parameters were used: U_dc = 300V, C₁=4.4mF, C₂ = 4.4mF, L=15.1mH, R = 0.1ω, i_ac = 7A, U_e obtained from 230/400 V, 50 Hz through a 400/230 V transformer, and ρ_α = ρ_β = 11, ρ_U = 25. The ac-controlled currents and dc capacitor voltage balance are compared to the results of a sliding-mode controller. Figure 36.72 shows that the predictive optimum controller performance is better than the sliding-mode controller. The predictive optimum controller presents some robustness to industrial component tolerances. Results showed a tolerance from − 50% to + 100%.

FIGURE 36.72 Multilevel converter sinusoidal ac currents, i₁, i₂, and i₃, in steady-state operation and dc capacitor voltages, using sliding-mode controllers (a) and (c) and predictive optimum controllers (b) and (d). (a) Sliding-mode controller ac currents (12A/div); (b) predictive optimum controller ac currents (12 A/div); (c) sliding-mode controller dc capacitor voltage balancing (10V/div); (d) predictive optimum controller dc capacitor voltage balancing (10 V/div).

Further experiments [34 and 35] revealed that harmonics of ac currents were 46 dB below the 50 Hz fundamental level, improving by 14 dB the sliding-mode controller result. The switching frequency of the predictive optimum controller spreads over the frequency spectrum below 2.5 kHz, reducing and softening the audible noise. The average switching frequency of the predictive optimum-controlled multilevel converter is reduced to half of the value of a sliding-mode-controlled multilevel at the same current ripple. Further reduction could be obtained by weighting the switching frequency in the quadratic cost functional.

EXAMPLE 36.20 Fast predictive optimum control of matrix converters

Consider the three-phase ac/ac matrix converter with input lCr filter of Fig. 36.64 and suppose we want to control the output currents i_o1, i_o2, and i_o3 while guaranteeing an almost unity input power factor and near sinusoidal input currents i_ig1,i_ig2 and i_ig3.

The converter direct dynamics of the output currents in dq frame at frequency ω_o, i_od and i_oq is

(36.246)

The converter direct dynamics of the input currents in dq frame at frequency ω_i. i_igd and i_igq is given in Eqs. (36.183) and (36.184). To control the matrix input power factor, the dynamics of the input dq currents, neglecting the effects of the matrix input filter damping resistor (r→ ∞), can be simplified to be

(36.247)

The control vector u_t+h, are denned by v_odt+h, v_oqt+h and i_iqt+h From the input and output dynamics of the matrix converter, Eq. (36.248) computes the necessary vector components to ensure convergence to the reference values within one sampling step h. Most terms of the i_iqt+h current can be neglected for simplicity, the essential ones being the difference i_igqref-i_igqt with associated gain, and the feedforward value of i_igqref

(36.248)

Only one calculation for the optimum vector with components (36.247) is needed, avoiding the currents and the respective error computation for all the 27 possible converter vectors, speeding the predictive method. Since the discrete time derivative and damping terms are calculated using the current future values, the Euler backward algorithm is used, ensuring convergence.

In practice, none of the available converter vectors will present exactly the necessary components. Therefore, the distance from each vector to the optimum vector (the vector error norm) must be computed, using the cost functional:

(36.249)

Results show that fast predictive optimum controllers, using the converter inverse dynamics, present better performances than state-of-art sliding-mode controllers (Fig. 36.73). Stability and robustness of fast predictive optimum controllers, concerning parameter variation, disturbances and non modeled dynamics, must be investigated.

FIGURE 36.73 Matrix converter sinusoidal ac input and output currents, i₁, i₂, and i₃, in steady-state operation, using (a) sliding-mode controllers and (b) fast predictive optimum controllers, (a) Sliding-mode controlled ac input and output matrix currents; (b) predictive optimum-controlled input and output matrix ac currents.

36.5.1 Introduction

Fuzzy logic control is a heuristic approach that easily embeds the knowledge and key elements of human thinking in the design of nonlinear controllers [36–38]. Qualitative and heuristic considerations, which cannot be handled by conventional control theory, can be used for control purposes in a systematic form and for applying fuzzy control concepts [39]. Fuzzy logic control does not need an accurate mathematical model, can work with imprecise inputs, can handle nonlinearity, and can present disturbance insensitivity greater than the most nonlinear controllers. Fuzzy logic controllers usually outperform other controllers in complex, nonlinear, or undefined systems for which a good practical knowledge exists.

Fuzzy logic controllers are based on fuzzy sets, i.e. classes of objects in which the transition from membership to nonmembership is smooth rather than abrupt. Therefore, boundaries of fuzzy sets can be vague and ambiguous, making them useful for approximation models.

The first step in the fuzzy controller synthesis procedure is to define the input and output variables of the fuzzy controller. This is done accordingly with the expected function of the controller. There are no general rules to select those variables, although typically the variables chosen are the states of the controlled system, their errors, error variation, and error accumulation. In switching power converters, the fuzzy controller input variables are commonly the output voltage or current error, and the variation or accumulation of this error. The output variables u(k) of the fuzzy controller can define the converter duty cycle (Fig. 36.74) or a reference current to be applied in an inner current-mode PI or a sliding-mode controller.

FIGURE 36.74 Structure of a fuzzy logic controller.

The fuzzy controller rules are usually formulated in linguistic terms. Thus, the use of linguistic variables and fuzzy sets implies the fuzzification procedure, i.e. the mapping of the input variables into suitable linguistics values.

Rule evaluation or decision-making infers, using an inference engine, the fuzzy control action from the knowledge of the fuzzy rules and the linguistic variable definition.

The output of a fuzzy controller is a fuzzy set, and thus, it is necessary to perform a defuzzification procedure, i.e. the conversion of the inferred fuzzy result to a nonfuzzy (crisp) control action, that better represents the fuzzy one. This last step obtains the crisp value for the controller output u(k) (Fig. 36.74).

These steps can be implemented online or off-line. Online implementation, useful if an adaptive controller is intended, performs real-time inference to obtain the controller output and needs a fast enough processor. Off-line implementation employs a lookup table built according to the set of all possible combinations of input variables. To obtain this lookup table, the input values in a quantified range are converted (fuzzification) into fuzzy variables (linguistic). The fuzzy set output obtained by the inference or decision-making engine, according to linguistic control rules (designed by the knowledge expert), is then converted into numeric controller output values (defuzzification). The table contains the output for all the combinations of quantified input entries. Off-line process can actually reduce the controller actuation time since the only effort is limited to consulting the table at each iteration.

This section presents the main steps for the implementation of a fuzzy controller suitable for switching power converter control. A meaningful example is provided.

36.5.2 Fuzzy Logic Controller Synthesis

Fuzzy logic controllers consider neither the parameters of the switching power converter or their fluctuations nor the operating conditions, but only the experimental knowledge of the switching power converter dynamics. In this way, such a controller can be used with a wide diversity of switching power converters, implying only small modifications. The necessary fuzzy rules are simply obtained considering roughly the knowledge of the switching power converter dynamic behavior.

36.5.3 Example: Near Unity Power Factor Buck-Boost PWM Rectifier

EXAMPLE 36.21 Fuzzy logic control of unity power factor buck-boost rectifiers

Consider the near-unity power factor buck-boost rectifier of Fig. 36.79, where the diodes in series with the transistors enable them to withstand negative voltages.

The switched state-space model of this converter can be written as follows:

FIGURE 36.79 Unity power factor buck-boost rectifier with four IGBTs.

(36.251)

For comparison purposes, a PI output voltage controller is designed considering that a current-mode PWM modulator enforces the reference value for the i_s current (which usually exhibits a fast dynamics compared with the dynamics of V_Co). A first-order model similar to Eq. (36.146) is obtained. The PI gains are similar to Eq. (36.116) and load-dependent (K_p=C_o/(2T_d), K_i= 1/(2T_dR_o)).

A fuzzy controller is obtained considering the approach outlined, with seven membership functions for the output voltage error, five for its change, and three membership functions for the output. The linguistic control rules are obtained as the ones depicted in Table 36.8, and the lookup table gives a mapping similar to Fig. 36.78. Performances obtained for the step response show a fuzzy controlled rectifier behavior close to the PI behavior. The advantages of the fuzzy controller emerge for perturbed loads or power supplies, where the low sensitivity of the fuzzy controller to system parameters is clearly seen (Fig. 36.80). Therefore, the fuzzy controllers can be advantageous for switching power converters with changing loads, power supply voltages, and other external disturbances.

FIGURE 36.80 Simulated result of the output voltage response to load disturbances (R_o = 50 –150 Ω at time 0.3 s): (a) PI control and (b) fuzzy logic control.