Underfill adhesive materials for flip chip applications
Abstract:
The advance of the semiconductor industry requires smaller and lighter micro-electronic packages with faster and more reliable electronic performance. Accordingly, flip chip technology, a direct chip attachment (DCA) technology that directly connects the circuitries between the silicon chip and the substrate, has been the fastest growing packaging in the semiconductor industry. Over the last decade it has also developed into many technology platforms, such as chip scale packaging (CSP) and multichip packaging. The reliability challenge of this new packaging technology was realized almost immediately and organic reinforcing materials were proposed, to be applied between the chip and the substrate (‘underfill’). To improve the productivity and reduce the cost of this new packaging technology, many forms of processes and their corresponding underfill materials, including the original capillary underfill, no-flow underfill, and wafer-level underfill, are currently actively being explored.
5.1 Introduction: flip chip and direct chip attachment technology
As the semiconductor industry advances, smaller and lighter micro-electronic packages with faster and more reliable electronic performance have become the general trend for the micro-electronic packaging industry. Direct chip attachment (DCA) technologies, which connect the electronic circuitry on the silicon chip directly to the circuitry on the substrate, have gained wide acceptance in the semiconductor industry. In contrast to the conventional wire-bonding packages, direct chip attachment connects the chip ‘face down’ directly to the substrate. Therefore, it gained the popular name ‘flip chip’ technology early in its development stage. Over the years, direct chip attachment technology developed into many technology platforms, including flip chip, chip scale packaging (CSP), and multi-chip packaging or 3D packaging, etc. Correspondingly, so-called ‘underfill’ packaging technology, which fills the re-enforcement materials into the gap between the chip and the substrate, has also been developed to ensure the reliability of these new types of package.
IBM first developed the C4 technology (Controlled Collapse Chip Connection) in the early 1960s for its mainframe computers.1 This became the first generation of flip chip packages. At its early stage, the chip was connected to ceramic substrates. In the late 1960s, Delco Electronics was the first company to use flip chip technology for automotive applications The technology did not gain broad industrial acceptance, however, until mid 1990s. Since then, flip chip on organic substrates has gained popularity in the semiconductor industry. The flip chip technology also enabled many forms of DCA technologies, such as CSP, which usually refers to package sizes of less than 120% of the chip size, and multi-chip packaging (3D packaging). Currently, DCA is the fastest growing sector in the semiconductor packaging industry with a projected > 50% annual growth rate. Most mobile semiconductor devices such as cellular phones, pagers, laptops, as well as high-speed microprocessors are currently assembled with direct chip attachment, mostly flip chip technology.
5.2 Advantages of direct chip attachment technology
DCA technology, possesses many advantages in size, performance, flexibility, reliability, and cost over conventional wire-bonding packaging technology.
5.2.1 Smaller, thinner, and lighter packages
DCA technology directly connects the circuitry on the chip and the circuitry on the substrate by metal bumps in between, making the height (or thickness) of the package much less when compared with the use of conventional wire-bonding technology. In addition, conventional wire-bonding technology allows the wire connections only around the perimeter of the chip. Flip chip technology, however, uses the whole area of the chip and hence reduces the required size of the package by as much as 95%. Finally, the smaller and thinner flip chip package also significantly reduces the weight of the package. In some cases, the weight can be as little as 5% of the conventional wire-bonding package.
5.2.2 High performance
Since the electrical connections are made by directly connecting the chip and the substrate, flip chip technology offers the highest electrical speed performance among the available assembly technologies. Research has indicated that eliminating bond wires reduces the delaying inductance and capacitance of the connection by a factor of 10, and shortens the path by a factor of 25 to 100.2 As discussed earlier, flip chip technology can make electrical connection using the whole chip area, and thus achieves the highest I/O density of all assembly technologies. In addition, it also offers flexibility of I/O connectivity and allows more advanced assembly technology, such as 3D packaging.
5.3 Reliability challenge of flip chip technology
Challenges in the reliability of this new technology were recognized almost immediately when the flip chip technology was introduced to broad applications in the semiconductor industry. In the mid 1990s, organic substrates were broadly used in the semiconductor industry. Unlike the ceramic substrates that IBM used in its early C4 applications, organic substrates have a much higher coefficient of thermal expansion (CTE) than the silicon chip, as well as the solder bump connections. Therefore, the primary reliability challenge of this new type of microelectronic package was its reliability under thermal stress. During the thermal cycling reliability test (experiencing from –40 °C to 150 °C repeatedly for as much as a few thousand cycles), the metal bumps (usually Sn/Pb eutectic alloy) connecting the circuitries of the chip and the substrate may crack and result in failure of the assembly. The root cause of this reliability failure is apparently the thermal mismatch of the low CTE of the silicon chip (3 ppm) and the high CTE of the organic substrate (usually 50–80 ppm). Encapsulant materials were soon introduced to reinforce the solder bumps and to enhance the solder interconnect reliability.3 Since the flip chip and the substrate are connected by the solder bumps, the encapsulant material needs to be flowed into the gaps between the chip and the substrate. Therefore, this encapsulation process earned the name ‘underfill process’ and the corresponding encapsulant material was referred to as the ‘flip chip underfill’ material.
5.4 Advances in the flip chip underfill process and encapsulant materials
Since the flip chip technology gained broad acceptance in the semiconductor industry, scientists and engineers have been working collaboratively to further advance this technology and develop corresponding encapsulant materials. In order to improve the productivity and reduce the overall cost of this technology, many processes to underfill the chip assembly have been explored, which include the original capillary underfill process, so-called ‘no-flow’ or ‘pre-applied’ underfill processes, and the ‘wafer level’ pre-applied underfill process. Each of these processes requires different material properties of the encapsulant; in many cases, joint process development and material development programs have been carried out. The joint programs have involved universities and affiliated research centers, major semiconductor manufacturing companies, and major chemical companies that supply the underfill encapsulant materials.
5.4.1 Capillary underfill process
The first attempt to apply organic underfill encapsulant materials to reinforce the solder bump interconnects consisted of allowing the encapsulating materials to flow into the gap between the chip and the substrate by capillary force. Figure 5.1 illustrates the current ‘capillary underfill’ process in flip chip and CSP technologies. First, a chip is attached to a substrate during the ‘reflow’ process. After the solder interconnects are established, a low viscosity encapsulant material is applied to fill the gap between the chip and the substrate. Since the encapsulant material is flowed into the gap by capillary force, this is called the ‘capillary underfill’ process. In this process, each package is underfilled individually, which limits productivity. Although this process is currently widely employed in the industry and demonstrates enhanced reliability of the packages, it is slow since the encapsulant material has to flow gradually to fill the gap and each package has to be underfilled individually. Requirements on material flow properties are also stringent in order to shorten the flow time. The viscosity of the encapsulant must be low, and sometimes heat has to be applied to ensure that the encapsulant flows properly. Therefore, the slow underfilling and resulting relatively high cost become the bottlenecks for this capillary underfill process.
The underfill encapsulant material usually contains up to 50% by weight silica fillers to reduce its CTE from 50–90 ppm to 20–30 ppm and match the solder bump’s CTE for maximum reinforcement. The primary material design challenge for the capillary underfill process is the requirement for low viscosity of the underfill material with a high percentage of silica fillers. If the flow property of underfill material is not designed properly, the flow may not be complete, or it may leave many voids in the package, which causes serious reliability problems. Another issue is filler settling – silica fillers gradually settle during the flow process resulting in non-homogeneity of the underfill encapsulant, which also affects reliability. Finally, it is required that the underfill encapsulant form a good fillet around the periphery of the die, which is essential for high package reliability. As the chip size increases, these challenges become more and more significant. In addition, low viscosity organics have to be cured into solid form and without generating volatiles. It has been reported that any voids generated under the chip may cause reliability failure of the flip chip assembly. Finally, the cure process of the low viscosity liquid underfill encapsulant has to be fast to ensure high productivity and reduce cost. In the meantime, in order to fulfill the maximum package reinforcement, the cured underfill encapsulant should be a high modulus solid, with low moisture absorption and good adhesion to the chip, solder bumps and the organic substrate.
Despite the above challenges, over the last 15 years, many material manufacturers have successfully developed a number of commercial underfill encapsulants. Many reports demonstrate that the underfill encapsulant has improved the reliability of flip chip packages by 10 to 100 times. The capillary underfill process is still by for the most dominant process for direct chip attachment.
5.4.2 ′Known Good Die′ issue and reworkability
During the development of DCA technology, the issue of reworkability of the assembly has been raised. With conventional wire bonding packaging technology, a failed package can be easily removed by melting the solder connection and replacing it by re-soldering a good package. After the underfill process with the solid encapsulant materials surrounding the solder bumps, it is no longer straightforward to replace the damaged chip. Over the years, both the flip chip rework process and reworkable encapsulant materials have been developed by several researchers. The proposed flip chip rework process is illustrated in Fig. 5.2 and includes:
• localized chip removal by heating
• underfill removal and site preparation
Solid thermoplastics are formed by polymerizing liquid small molecules into linear thermoplastic polymer. Heat can make the thermoplastics flowable for their removal, or, alternatively they can be removed by using a suitable solvent. Thermosets are solidified by ‘curing’ liquid small molecules and form a cross-linked network structure. Heat cannot make the thermosets flowable and solvents cannot dissolve the cross-linked network structure, either. Thermoset materials have to go through a degradation process to break down the network structure for their removal.
Reworkable underfill encapsulant materials have been developed in parallel. One of the approaches was ‘reactive thermoplastic’ and this is summarized in Fig. 5.3.4
Another approach has been to use thermally-degradable thermosettingmaterials. Upon heating, the thermosetting materials decompose and form low molecular weight monomers and oligomers. This allows the underfill encapsulant material to be easily removed during the rework process. The representative chemistry is the cleavable ester epoxy material developed by Professor Ober at Cornell University.5 This approach uses a-terp-epoxide as the basic material for the underfill encapsulant. After curing, the material forms a thermoset solid. Upon heating during the rework process, its tertiary ester sites break down and the encapsulant becomes easily removable with common organic solvents.
In recent years, more reworkable encapsulant chemistries have been developed and explored by other universities and chemical companies. However, the actual application of the reworkable underfill technology has been limited, primarily due to cost considerations.
5.5 New material challenges to lead-free solder
Tin–lead (Sn-Pb) eutectic solder has been used for the semiconductor industry as the primary connecting materials for many decades. In recent years, the Pb toxicity issue has attracted public attention and, correspondingly, many environmental legislations have been imposed to limit Pb consumption in semiconductor industry. Alternative solder materials have been developed in recent years and most of them are metal alloys containing Sn, Cu, Ag, Zn, and Bi. So far, most of these newly developed Pb-free solder alloys have higher melting points than the conventional eutectic Sn-Pb solder. For example, the most commonly used Sn-Ag-Cu triple alloy has a melting point of 217 °C. The high melting points of these Pb-free alloys also imply high reflow temperatures during the flip chip assembly process, which in turn generates higher thermal stress on the package. In addition, the underfill encapsulant developed for eutectic solder applications faces a compatibility challenge with the Pb-free solder. The wetting behavior of the underfill on the new alloy solder bumps is usually not as good as on the eutectic solder bumps. The wetting behavior of an organic material is commonly believed to be essential to its adhesive performance, and good adhesion to the solder bumps is required for good reliability; this has become the new challenge for underfill encapsulant materials.
5.6 The ′no-flow′ pre-applied underfill process
To accelerate the slow process of the capillary underfill, a so-called ‘no-flow’ process has been proposed and is under active development by many institutions and companies. Figure 5.4 depicts such a process. The main steps involve dispensing underfill on a substrate, aligning and placing the flip chip on the substrate, and then reflowing the assembly through a typical reflow process. Different from the capillary underfill process, the no-flow underfill process does not require that the encapsulant materials flow slowly under the chip. The encapsulant materials can be quickly dispensed onto the substrates. After aligning and placing the chip on the substrate, the solder interconnect formation and the encapsulant curing occur simultaneously during the reflow process. Therefore, the no-flow process has the potential to accelerate the process speed and therefore reduce the overall process cost.
During the assembly process, however, there is a concern that air bubbles could be trapped during the fast chip attachment step, particularly for high I/O area array chips. In addition, filler particles in the encapsulant could be trapped between the solder balls and the substrate circuitry, which may affect the interconnect conductivity. Therefore, in most cases, inorganic fillers are not incorporated in current no-flow underfill encapsulants, which may limit the effectiveness of the underfill encapsulant on reliability enhancement due to the high CTE of the underfill encapsulant.
Active research and development effort has been launched in many institutions and companies. Equipment manufacturers, such as Asymtech, have even developed prototype no-flow underfill instrumentation. Many material suppliers have also developed corresponding no-flow underfill encapsulant materials. Unlike the capillary flow encapsulant materials, the viscosity of no-flow underfill materials needs to be relatively high, so that they do not flow freely to contaminate the surrounding area. During the solder bump reflow process after the chip is in place, the underfill encapsulant material should be solidified only after the solder bumps are reflowed. Ideally, the underfill encapsulant materials for this no-flow process should possesses cure ‘latency’, i.e. the underfill should not solidify immediately during the solder reflow. As soon as the solder reflows, however, the underfill encapsulant should be cured and solidify relatively fast to achieve its final properties. This cure latency requirement apparently raises a material design challenge. In the conventional solder reflow process, a flux is applied and solder reflow occurs in a separate process step. However, no-flow underfill encapsulant materials should also have a fluxing function to ensure reliable solder metal connections, since the solder reflow and underfill cure are achieved in one step. This is also a new challenge for the material developers. During the development of the no-flow underfill encapsulant materials, void formation became a major concern of this technology. It has been demonstrated in many research reports that voids in the package are a major source of reliability failure. Besides the typical origin of the voids formation – volatiles generated from the underfill encapsulant during the curing process – the no-flow process itself generates another potential voids formation mechanism. During the process, when the chip is placed on top of the substrate with the underfill on it, trapped air bubbles become another source for the undesirable void formation.
Filler entrapment is another hurdle for this technology. Without incorporation of silica filler, the material cannot achieve the desired low CTE. The high CTE of the encapsulant material may limit the underfill’s reinforcement efficiency. However, if silica filler is used, the possibility of trapping filler particles between the solder bumps and the substrate circuitry endangers the interconnect reliability. Understanding these technical challenges, intensive development work has been carried out in many institutions and material supply companies.6’7 Most of them use epoxy–anhydride based materials, but other chemistries have also been explored.8
5.7 The wafer level pre-applied underfill process
To further accelerate production speed and exploit process cost savings, the next logical step is to bring the underfill encapsulation process to ‘wafer level’. The wafer level process is the most advanced and challenging flip chip and CSP option, and potentially the most efficient and cost-effective one, too.9,10 This approach breaks the traditional ‘front-end’ and ‘back-end’ fields in the semiconductor industry and is the first attempt to merge the two separate sectors. As expected, however, this approach also encounters the most technical challenges.
As illustrated in Fig. 5.5, the process starts with the deposition of underfill encapsulant on a bumped wafer. This is followed by solidification of the underfill (or B-stage), and dicing the processed wafer into individual chips. During the assembly process, it is proposed that the individual chip is aligned and placed on the substrate, followed by an in-line reflow process. Ideally, the solder reflow and the curing of encapsulant are completed in one reflow step. By dispensing the underfill encapsulant onto a wafer instead of onto each individual chip, it is potentially a more efficient packaging process.
The wafer level process eliminates several steps in current flip chip/CSP packaging processes. However, new requirements for encapsulant materials have to be met to ensure the process is a feasible one. A non-tacky solid encapsulant at room temperature on the wafer is essential to meet both dicing and storage requirements. However, this non-tacky solid encapsulant also brings a challenge to attach the chip on the substrate during the solder reflow step. Poor wetting to the substrate and lack of fillet formation may result in poor end-use reliability of the package. Furthermore, full coverage of the solder bumps with filled encapsulant materials causes filler trapping concerns and the unevenness of the encapsulant surface may trap air voids during the attachment step. Besides the above concerns, there is another issue that needs to be considered in the final assembly process. This ‘self-alignment’ issue will be addressed in detail in Section 5.8. The wafer level dual encapsulation process.
5.7.1 Material requirements for the wafer level underfill
The performance requirements of wafer level underfill materials present material suppliers with many challenges they have never experienced before.11 In the proposed wafer level flip chip processes, the underfill encapsulant material has to perform multiple functions at a series of processing steps, combining the roles of a number of materials that have been used independently up to now. The following is a step-by-step analysis of the material requirements and strategies in terms of underfill material development.
5.7.2 Depositing underfill onto the wafer
The method of depositing underfill on finished wafer will be the first step of this process, which used to be a ‘front end’ process. The challenge for the material supplier is to supply the material with the right rheological properties to facilitate deposition. Many processing methods have been explored, including stencil printing, screen printing, and spin coating. Depending on the application method, the underfill material rheology has to be adjusted accordingly. The residue of unreacted monomer or solvent should be avoided in any case, because any small amount of residual solvent or monomer may cause voids at the later high-temperature reflow stage and curing stage, affecting the reliability of the flip chip.
5.7.3 Solidifying the underfill
The wafer and package should be easy to handle under ambient conditions after the underfill is applied. Therefore, the underfill material should be in a solid, non-tacky form at room temperature for storage and handling. From the material development point of view, this means a solidification step, either by a chemical or a physical method, and this has to be carried out after the deposition step. This is referred by many people in this field as the ‘B-stage’ process in this process. The underfill encapsulant material on the wafer is in a solid, non-tacky form for storage and handling, as well as during the subsequent dicing step. In the meantime, the B-staged underfill encapsulant has to be able to flow again during the solder reflow process to allow the formation of the solder bump connections.
5.7.4 Dicing
During the dicing step, both the silicon wafer and the underfill will experience heat generated by the diamond saw. To protect the lifetime of the saw and the integrity of the underfill encapsulant, the B-stage solidified underfill material should have good mechanical properties under dicing conditions. Also, the material should be water resistant, so as not to absorb moisture from the cooling water during this process step. A high moisture content in the underfill material will be detrimental to the later processing stage as well as to the end-use reliability of the package. It has been reported that during dicing, the material may experience temperatures as high as 100 °C or more.12
5.7.5 Storage
After the dicing step, the diced wafer or the individual chips will be packed, shipped and stored for a long period of time. During this period, the properties of the underfill encapsulant should not change, so as not to affect the subsequent processing steps such as solder reflow and final cure. Shelf-life of the diced wafer or chips should meet industrial standards, typically from six months to a year at room temperature. If the underfill materials advances and further cures on the chip during storage, the resultant high viscosity may hinder the formation of the solder bumps during the next attachment and solder reflow steps.
5.7.6 Aligning and attaching
Pick and place equipment is currently available to place the flip chip with underfill on its substrate during the attachment process. ‘Self-alignment’ is an important phenomenon during the conventional reflow process, which enables the chip to align itself with maximum accuracy to its substrate circuitry. However, due to the existence of the underfill encapsulant on the chip, the self-alignment effect will be reduced or eliminated in the wafer level flip chip packaging process. Therefore, more accurate instrument alignment may be needed in this process.
5.7.7 Reflow of the solder and forming the interconnect
Compared with the conventional flip chip attaching process, this step represents the most drastic change. The metallurgical connection has to be made in the presence of the underfill medium without conventional fluxing agents, so there are multiple challenges to the underfill encapsulant material. First, the material should carry the fluxing capability, since the solder bumps are now being surrounded by the underfill materials. Second, the solder connection has to be made before the underfill undergoes significant cure because the high viscosity of a cured underfill will certainly hinder the flow of molten solder. That means that the B-staged solid underfill encapsulant has to be liquidized at the reflow temperature to allow the metallic interconnect formation. Finally, after the metal solder bumps reflow and form the interconnects, the underfill encapsulant should fully cure relatively fast to ensure high efficiency of the process. Therefore, a carefully designed material with desired cure latency is the primary challenge to the material developers.
5.7.8 Curing of the underfill encapsulant
As stated earlier, the goal of the wafer level flip chip process is to make the solder reflow and underfill cure as a single step. Solder reflow also dictates that the underfill cure should happen after the metallurgical interconnection is made. A simple analysis of the common reflow profile, such as the one illustrated in Fig. 5.6, tells us that the assembly stays above 150 °C for two minutes before it reaches the maximum reflow temperature. During this period, the underfill material should remain as a low viscosity liquid to allow the formation of the metal interconnections. After the peak solder melting temperature at 220 °C, the device stays above 150 °C for less than 2 minutes. It is in this temperature window that the cure of the underfill encapsulant should be completed. Thus, the development of a novel curing mechanism is essential for the success of the wafer level underfill encapsulant material. Currently, the state of art in this area is achieved in no-flow underfill applications, in which a post-cure is required after the regular reflow temperature profile is completed. However, the post-cure process definitely slows the overall process and increases the cost.
5.7.9 Reliability of the wafer level underfill
The reliability requirements for wafer level underfill are identical to those for conventional underfill. The after-cure properties of the material should include high glass transition temperature, low CTE, high modulus, and good adhesion to all surfaces.
5.8 The wafer level dual encapsulation process
In current surface mount processes, liquid flux is applied onto the solder bumps to ensure the proper solder interconnect formation. In addition, the liquid flux also holds the chip in place during the in-line reflow process, which is important to ensure the alignment of the package. In the wafer level packaging process, the solder bumps are surrounded by wafer-applied encapsulant and self-alignment is no longer effective. In addition, applying conventional liquid flux is not an option for the wafer level process. Since the metal interconnect formation and the reinforcement encapsulant filling are achieved in the same reflow step, the flux application and flux residue cleaning are practically impossible. Currently widely used ‘no-clean’ fluxes, which rely on the evaporation of their organic ingredients, may generate voids during the reflow process. In order to solve this difficulty and also make the wafer level packaging a completely compatible process to current industry infrastructure, a ‘wafer level dual encapsulation’ approach is here proposed and explored.
Figure 5.7 illustrates the wafer level dual encapsulation process. As implied by the name, two types of encapsulant materials are necessary for this process. Type-I encapsulant is a highly-filled, high modulus, and high Tg material. The encapsulant is applied on the wafer before the wafer is diced into individual chips. It goes through all the wafer level processing steps such as B-staging and dicing. Type-II encapsulant is a low-viscosity liquid material without inorganic filler. It is capable of fluxing the solder bumps during the solder reflow process. During the assembly process, either the chip is dipped into the liquid Type-II material, or a droplet of the material is dispensed onto the substrate before the chip is placed on the substrate. The low-viscosity liquid Type-II encapsulant holds the chip in place during the in-line reflow process and therefore the chip can be properly aligned.
The wafer level dual encapsulation process takes advantage of both the ‘no-flow’ and the ‘wafer-level’ packaging approaches. It still shares all the advantages of the two processes, such as high production output and low processing cost. However, highly-filled Type-I underfill encapsulant with low CTE can be used in this process and this translates into better end-use reliability. It has been shown in the published literature that the most vulnerable point of the package, is at the die-bump interface due to the thermal stress generated from the CTE mis-match. Therefore, it is critical that the chip side is reinforced by a highly filled, high Tg, and low CTE Type-I encapsulant to enhance the reliability of flip chip/CSP packages. During the attachment step, a low-viscosity liquid Type-II encapsulant is applied to hold the chip in place. In addition, it provides better wetting and adhesion to the substrate. The low viscosity Type-II liquid encapsulant also flows easily during the attachment process and forms a nice ‘fan-out’ fillet around the chip after the reflow process. Both the better adhesion and the better fillet formation will contribute positively to the end-use reliability of the packages. Finally, by replacing solder flux with a liquid Type-II encapsulant, the proposed wafer level dual encapsulation process is compatible with the industry infrastructure of current surface mount technology (SMT). Therefore, this process and the corresponding encapsulant materials will be a feasible wafer packaging option for flip chip packaging and CSP.
In further detail, Type-I materials are highly-filled with silica filler, up to 60% by weight. Both solvent-containing formulations and solvent-free formulations are developed for this encapsulant. Depending on the application method, the viscosity of the formulation can be adjusted properly for stenciling or spinning coating processes. Fluxing agents are optional in the Type-I materials, although most of the formulations contain fluxing agents.
After the paste Type-I material is applied on the wafer, it is B-staged to form a smooth, void-free, and non-tacky solid coating on the wafer. The B-stage conditions need to be optimized to ensure the complete removal of the solvents and volatile ingredients in the formulation. Residual solvent and volatile ingredients have been shown to generate voids during the assembly process. on the other hand, it is desirable that the B-staged encapsulant softens during the solder reflow process. Although this wafer level dual encapsulation process obviates the stringent flow requirement for the Type-I material during the assembly step, experimental results have suggested that premature cure of the encapsulant should still be prevented.
The Type-II material is designed to be applied between the chip (with Type-I encapsulant on it) and the substrate during the assembly process. It is a low-viscosity liquid to allow easy dispensing and good spreading during the process, and to avoid the filler trapping problem, no filler is added. This material contains sufficient fluxing agent to flux the solder balls and ensure adequate interconnect formation. Premature cure of the encapsulant before the solder interconnect formation should be prevented – delayed cure is required for this material. To control the curing process, a proprietary curing agent has been developed. Finally, since void generation is a big concern during the assembly step at the high reflow temperature (up to 260 °C), the formulation should be free of solvents and volatile ingredients.
An experiment simulating the assembly process has been performed to demonstrate the feasibility of this wafer dual encapsulation process.13 A droplet of Type-II material was placed on a piece of Cu finished FR4 board. The glass slide specimen coated with B-staged Type-I encapsulant was placed face down on the droplet to form the assembly. The assembly was then heated on a hot plate which was preheated at 240 °C. Through the glass slide, the fluxing of the solder balls, the interconnect formation, and the flow and curing behavior of the encapsulant materials were observed. Within 30 seconds, it was observed that the size of the solder balls was enlarged and the glass slide collapsed on the substrate. This phenomenon demonstrated the fluxing of the solder balls and the formation of the metal interconnects. It also confirmed that the encapsulants were not prematurely cured and did not prevent the wetting and spreading of the solder balls. In addition, it was also observed that the liquid Type-II material at the bottom flowed and formed good fillets around the glass cover slide. Finally, after heating on the hot plate for two minutes, the encapsulant materials were fully cured and the glass slide was solidly bonded onto the FR4 substrate. Good fillet formation was also reported. The packages processed with both the Type-I and Type-II encapsulant materials formed fillets around the chip boundary. As can be seen in Fig. 5.8, the low-viscosity liquid Type-II material flowed well, and formed a complete fan out fillet. Closer examination of the fillet from the side view shows that the Type-II encapsulant climbed up along the chip edges. It is common knowledge in the industry that fillet formation is necessary to achieve the required reliability of the flip chip and CSP packages.
5.9 Conclusions
Flip chip technology, or in a more generic term, direct chip attachment (DCA) technology, is still in its infant stage. Due to its advantages, such as small footprint, thin package, light weight, high I/O density, and fast electronic performance, it is gaining more and more acceptance within the semiconductor industry. To enhance the reliability of these assemblies, underfill encapsulant materials are usually used. It has been demonstrated that, with the underfill encapsulant reinforcement, thermal reliability of the packages usually increases by 3 to 10 times. To improve production efficiency and reduce costs, many underfill processes have been developed and corresponding underfill encapsulant materials have been explored. Although currently the original capillary underfill process still dominates, these other approaches are actively being explored and developed.
5.10 References
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