Chapter 7 Monolithic Integration of Carbon Nanotubes and CMOS

As discussed in the previous chapter, carbon nanotubes (CNTs) have been explored for various applications with great success. With the extraordinary and unique electrical, mechanical, and chemical properties of CNTs, it is also highly desired to develop complementary metal-oxide-semiconductor (CMOS)–CNT hybrid integration technology that can take advantage of the powerful signal conditioning and processing capability of state-of-the-art CMOS technology. CNTs may be used either as an integral part of CMOS circuits or as sensing elements to form functional nano-electromechanical systems (NEMSs).

In CNT-CMOS circuits, or nanoelectronics applications, nanoscale CNT–field effect transistors (FETs) can be integrated with conventional CMOS circuits and form various functional blocks, e.g., CNT memory devices. Since the further scaling of silicon-based memories is expected to approach its limits in the near future, as the capacitor charge and writing/erasing voltages cannot be scaled down [1], a highly scalable hybrid CMOS-molecular nonvolatile memory has been widely explored, where CNT-based memories are connected to the readout CMOS logic circuitry [2,3]. The nanotube random access memory (NRAM) used in [3] is shown in Figure 7.1. It is a nonvolatile, high-density, high-speed, and low-power nanomemory developed by Woburn, Massachusetts-based Nantero, and it is claimed to be a universal memory chip that can replace DRAM, SRAM, flash memory, and ultimately hard-disk storage [3,4].

FIGURE 7.1 The structure of NRAM at (a) on and (b) off states. (From I. Nantero, NRAM^®, 2000–2009, http://www.nantero.com/mission.html.)

For sensing applications, CNTs can be used as mechanical, chemical, and radiation sensors. The integration of CMOS circuits with CNT sensors can provide high-performance interfacing, advanced system control, and powerful signal processing to achieve so-called smart sensors. Such CMOS circuits for CNT sensors can regulate the sensing temperature [5], increase the dynamic range [6], improve the measurement accuracy [7], and provide multiple readout channels to realize electronically addressable nanotube chemical sensor arrays [8]. Various sensors based on such CMOS-CNT hybrid systems have been demonstrated, including integrated thermal and chemical sensors [9,10,11].

Other efforts have been made to use multiwall carbon nanotubes (MWNTs) as the CMOS interconnect for high-frequency applications [12], or to apply CNT-based nanoelectromechanical switches for leakage reduction in CMOS logic and memory circuits [13].

Currently, monolithic integration of CMOS and CNT is still very challenging. Most CMOS-CNT systems have been realized by either a two-chip solution or complicated CNT manipulations. In this chapter, we will review various CNT synthesis technologies and CMOS-CNT integration approaches. Particularly, we will focus on the localized heating CNT synthesis method, based on which the integration of CNT on foundry CMOS has been demonstrated.

7.1.1 CARBON NANOTUBE SYNTHESIS

Great efforts have been made to investigate the CNT growth mechanism, but it is still not completely understood. Based on transmission electron microscope (TEM) observation, Yasuda et al. proposed that CNT growth starts with rapid formation of Interconnects rod-like carbons, followed by slow graphitization of walls and formation of hollow structures inside the rods [14].

There are three main methods for carbon nanotube synthesis: arc discharge [15,16,17], laser ablation [18,19,20], and chemical vapor deposition (CVD) [21,22,23,24]. The first two methods involve evaporation of solid-state carbon precursors and condensation of carbon atoms to form nanotubes. The high temperature (thousands of degrees Celsius) ensures perfect annealing of defects, and hence these two methods produce high-quality nanotubes. However, they tend to produce a mixture of nanotubes and other by-products, such as catalytic metals, so the nanotubes must be selectively separated from the by-products. This requires quite challenging post-growth purification and manipulation.

In contrast, the CVD method employs a hydrocarbon gas as the carbon source and metal catalysts heated in a tube furnace to synthesize nanotubes. It is commonly accepted that the synthesis process starts with hydrocarbon molecules adsorbed on the catalyst surface. Then the carbon is decomposed from the hydrocarbon and diffuses into the catalytic particles. Once the supersaturation is reached, carbons start to precipitate onto the particles to form carbon nanotubes. After that, nanotubes can grow by adding carbons at the top of the tubes if the particles are weakly adhered to the substrate surface. Nanotubes can also grow from the bottom if the particles are strongly adhered [25]. The former is called the tip-growth model and the latter is called the base-growth model. Compared to the arc discharge and laser ablation methods, CVD uses much lower synthesis temperature, but it is still too high to directly grow on CMOS substrates. In addition, CVD growth provides an opportunity to directly manufacture substantial quantities of individual carbon nanotubes. The diameter and location of the grown CNTs can be controlled via catalyst size [26] and catalyst patterning [27], and the orientation can be guided by an external electric field [28]. Suitable catalysts that have been reported include Fe, Co, Mo, and Ni [29].

Besides the CNT synthesis, electrical contacts need to be created for functional CNT-based devices. It is reported that molybdenum (Mo) electrodes form good ohmic contacts with nanotubes and show excellent conductivity after growth, with resistance ranging from 20 kΩ to 1 MΩ per tube [30]. The electrical properties can be measured without any post-growth metallization processing. The resistance, however, tends to increase over time, which might be due to the slight oxidation of the Mo in air. Other than that, electron-beam lithography is generally used to place post-growth electrodes. Several metals, such as gold, titanium, tantalum, and tungsten, have been investigated as possible electrode materials, and palladium top contacts are believed to be most promising [31].

7.1.2 CMOS-CNT INTEGRATION CHALLENGES AND DISCUSSION

As mentioned previously, a complete system with carbon nanotubes and microelectronic circuitry integrated on a single chip is needed to fully utilize the potentials of nanotubes for emerging nanotechnology applications. This monolithic integration requires not only high-quality nanotubes but also a robust fabrication process that is simple, reliable, and compatible with standard foundry CMOS processes. Such a CMOS-compatible integration process up to now remains a challenge, primarily due to the material and temperature limitations posted by CMOS technology [32,33].

FIGURE 7.2 (a) Circuit schematic of the decoder consisting of NMOS and single-walled carbon nanotubes. (b) Schematic of the cross section of the decoder chip, interconnected by phosphorus-doped n+ polysilicon and molybdenum. (From Y.-C. Tseng et al., Nano Letters, 4, 123–127, 2004. With permission.)

As discussed in Section 7.1.1, CVD has been widely used to synthesize nanotubes. Researchers have been working on growing CNTs directly on CMOS substrate using thermal CVD methods. For example, Tseng et al. demonstrated, for the first time, a process that monolithically integrates SWNTs with N-type metal-oxide-semiconductor (NMOS) FETs in a CVD furnace at 875°C [34]. However, the high synthesis temperature (typically 800–1000°C for SWNT growth [35]) would damage aluminum metallization layers and change the characteristics of the on-chip transistors. Ghavanini et al. have assessed the deterioration level of CMOS transistors that were applied with a CVD synthesis condition, and reported that one P-type metal-oxide-semiconductor (PMOS) transistor lost its function after the thermal CVD treatment (610°C, 22 min) [32]. As a result, the integrated circuits in Tseng’s thermal CVD CNT synthesis, as shown in Figure 7.2, can only consist of NMOS and use n+ polysilicon and molybdenum as interconnects, making it incompatible with foundry CMOS processes.

To address this problem, one possible solution is to grow nanotubes at high temperature first, and then transfer them to the desired locations on another substrate at low temperature. However, handling, maneuvering, and integrating these nano-structures with CMOS chips/wafers to form a complete system are very difficult. In the early stage, atomic force microscope (AFM) tips were used to manipulate and position nanotubes into predetermined locations under the guide of scanning electron microscope (SEM) imaging [36,37]. Although this nanorobotic manipulation realized precise control over both the type and location of CNTs, its low throughput becomes the bottleneck for large-scale assembly. Other post-growth CNT assembly methods that have been demonstrated so far include surface functionalization [38], liquid-crystalline processing [39], dielectrophoresis (DEP) [40,41,42,43], and large-scale transfer of aligned nanotubes grown on quartz [44,45].

FIGURE 7.3 (a) Process flow to integrate MWNT interconnects on CMOS substrate. (b) SEM image of one MWNT interconnect (wire and via). (From G.F. Close et al., Nano Letters, 8, 706–709, 2008. With permission.)

Among these methods, CMOS-CNT integration based on the DEP-assisted assembly technique has been reported, and a 1 GHz integrated circuit with CNT interconnects and silicon CMOS transistors has been demonstrated by Close et al. [12]. The fabrication process flow and the assembled MWNT interconnect are shown in Figure 7.3. The DEP process provides the capability of positioning the nanotubes precisely in a noncontact manner, which minimizes the parasitic capacitances and allows the circuits to operate above 1 GHz. However, to immobilize the DEP-trapped CNTs in place and to improve the contact resistances between CNTs and the electrodes, metal clamps have to be selectively deposited at both ends of the CNTs (Figure 7.3a, step 3). The process complexity and low yield (~8%, due to the MWNT DEP assembly limitation) are still the major concerns.

Alternatively, some other attempts have been made to develop low-temperature growth using various CVD methods [46,47,48]. Hofmann et al. reported vertically aligned carbon nanotubes grown at temperatures as low as 120°C by plasma-enhanced chemical vapor deposition (PECVD) [47]. However, the decrease in growth temperature jeopardizes both the quality and yield of the CNTs, as evident from their published results (shown in Figure 7.4). The synthesized products are actually defect-rich, less crystalline, bamboo-like structured carbon nanofibers rather than MWNTs or SWNTs.

FIGURE 7.4 SEM images of vertically aligned CNFs grown by PECVD deposition at (a) 500°C, (b) 270°C, and (c) 120°C. Scale bars: a and b, 1 μm; c, 500 nm. (From S. Hofmann et al., Applied Physics Letters, 83, 135–137, 2003. With permission.)

FIGURE 7.5 Fabrication process and localized heating concept. (From O. Englander et al., Applied Physics Letters, 82, 4797–4799, 2003. With permission.)

To accommodate both the high-temperature requirement (800–1000°C) for high-quality SWNT synthesis and the temperature limitation of CMOS processing (<450°C), CNT synthesis based on localized heating has drawn great interest. Englander et al. demonstrated, for the first time, the localized synthesis of silicon nanowires and carbon nanotubes based on resistive heating using microheaters [49]. The fabrication processes and concepts are shown in Figure 7.5. Operated inside a room temperature chamber, the suspended microelectromechanical system (MEMS) structures serve as microheaters to provide high temperature at predefined regions for optimal nanotube growth, leaving the rest of the chip area at low temperature. Using the localized heating concept, direct integration of nanotubes at specific areas can be potentially achieved in a CMOS-compatible manner, and there is no need for additional assembly steps. Attracted by this promising technique, several research groups have followed up, and localized CNT growth on various MEMS structures has been demonstrated [50,51,52]. However, the devices typically have large sizes, and their fabrication processes are not fully compatible with the standard foundry CMOS processes. Although this concept has solved the temperature incompatibility problem between CNT synthesis and circuit protection, the fabrication processes of microheater structures still have to be well designed to fit into standard CMOS foundry processes, and the materials of microheaters have to be selected to meet the CMOS compatibility criteria.

FIGURE 7.6 (a) Schematic of the cross-sectional layout of the chip. (b) Optical image of the device top view, showing the tungsten interdigitated electrodes on top of the membranes. Heater radius = 75 μm, membrane radius = 280 μm. (From M.S. Haque et al., Nanotechnology, 19, 025607, 2008. With permission.)

Progress toward complete CMOS-CNT systems has been made. On-chip CNT growth using CMOS micro-hotplates was later demonstrated by Haque et al. [53]. As shown in Figure 7.6, tungsten was used to fabricate both the micro-hotplates (as the thermal source) and interdigitated electrodes for nanotube contacts. MWNTs have been successfully synthesized on the membrane, and simultaneously connected to circuits through tungsten metallization. Although tungsten can survive the high-temperature growth process, and has high connectivity and conductivity, Franklin et al. reported that no SWMTs were found to grow from catalyst particles on the tungsten electrodes, presumably due to the high catalytic activity of tungsten toward hydrocarbons [30]. Further, although monolithic integration has been achieved, the utilization of tungsten, a refractory metal, as an interconnect metal is limited in CMOS foundry, especially for mixed-signal CMOS processes. From the CMOS point of view, tungsten is not a good candidate as an interconnect metal compared with aluminum and copper. Other than the material, this approach is limited to silicone on insulator (SOI) CMOS substrates, requires a backside bulk micromachining process, and has low integration density.

From the reviews above, we can see that monolithic CMOS-CNT integration is desirable to utilize the full potential of nanotubes for emerging nanotechnology applications. However, the existing approaches, although each has its own merits, still cannot meet all the requirements and realize complete compatibility with CMOS processes. To solve this problem, a simple and scalable monolithic CMOS-CNT integration technique using a novel maskless post-CMOS surface micromachining processing has been developed and will be presented in the following sections. This approach is fully compatible with commercial foundry CMOS processes and has no specific requirements on the type of metallization layers and substrates.

Since CMOS fabrication is costly and time-consuming even through the multi-project wafer (MPW) service provided by MOSIS, mock-CMOS substrates will first be used for the process development and basic conceptual verification. A mock-CMOS substrate is a silicon substrate with multiple layers of metals and dielectrics but without any diffusion layers.

7.2 CNT SYNTHESIS BY LOCALIZED RESISTIVE HEATING ON MOCK-CMOS

The localized heating concept is illustrated in Figure 7.7. A microstructure is thermally isolated by suspending it over a micromachined cavity. The microstructure has a heater embedded. When a current is injected into the heater, the temperature of the microstructure will rise. Because of the thermal isolation provided by the cavity, the temperature of the substrate outside the cavity will not change much. The key is the heater design.

7.2.1 MICROHEATER DESIGN

The local temperature distribution and the maximum temperature are the key parameters of the microheater structures. Since SWNT growth requires temperature as high as 800°C or above, the resistivity of the heater, thermal isolation, thermal stresses, and structural stiffness must be taken into consideration when designing the microheaters. A 3D model of a mock-CMOS microheater is shown in Figure 7.7. Suspended microstructures are created over a microcavity for good thermal isolation. Resistors are integrated as the heating source, and the local electrical field (E-field) and growth temperature can be controlled by the microheater geometry and power supply.

FIGURE 7.7 Structural demonstration of the mock-CMOS platinum microheater.

FIGURE 7.8 (a) Large hotplate with a meander Pt microheater embedded. (b) Serpentine microheater design. (c) Straight-line microheater design.

Three types of microheaters have been designed. The first microheater design (Figure 7.8a) is a micro-hotplate with a meander-shaped microheater embedded. The hotplate is supported by two anchored short beams. This design has a large growth area with relatively uniform temperature distribution, and potential as a gas sensor. CNTs are expected to grow on the hotplate surface. The second design (Figure 7.8b) has a serpentine shape. This design introduces trenches between the microheater (the central part) and the silicon dioxide secondary wall (the two straight lines on the side) for suspended CNT growth. With the secondary wall grounded, this configuration is also designed to study the local E-field distribution and the impact of the E-field on the CNT alignment. The third design (Figure 7.8c) is further simplified into one straight line for studying temperature and CNT density distribution along the microheater. The distribution information will facilitate the further microheater scaling. The minimization of heating elements offers more accurate local control of E-field, temperature, and growth rate. Thus the position, quantity, length, direction, and properties of CNTs can be better controlled. Moreover, smaller heating elements require less power, and lead to a higher CMOS-CNT integration density.

Several different materials have been investigated as the electrode material for CVD growth of CNTs in the literature. Metals with relatively low melting temperature, such as gold, become discontinuous as they are balling up during the high-temperature growth process, while some other candidates, such as Ti and Ta, tend to react with hydrogen and form volatile metal hydride at high temperature [30]. In our experiment, platinum (Pt) has been chosen as the microheater material due to its compatibility with CNT growth. Pt is a refractory metal with very high melting temperature, is widely used as a contact electrode in traditional CVD CNT synthesis procedures, and has demonstrated good contacts with CNTs, with resistance ranging from 10 to 50 kΩ [12].

7.2.2 DEVICE FABRICATION AND MICROHEATER CHARACTERIZATION

7.2.2.1 Device Fabrication

Based on the above microheater designs, a process flow is proposed to fabricate the devices. Figure 7.9 shows the cross-sectional view of the process flow. The fabrication process starts from the deposition of a 0.5 μm thick SiO₂ (Figure 7.9a). A Cr/Pt/Cr heater film is then sputtered and patterned using a liftoff process, in which the 200 nm thick Pt is the heater and the 30 nm thick Cr is the adhesive layer for Pt (Figure 7.9b; the Cr layers are not shown). Next another 0.5 μm thick top SiO₂ layer is deposited and patterned. Depending on the mask design, the top SiO₂ layer can remain to form an oxide/Pt/oxide sandwich structure (Figure 7.9c), or the SiO₂ over the microheater can be etched away to form a Pt/oxide bimorph structure (Figure 7.9c′). In the latter case, direct contact between Pt electrodes and CNTs will be formed during the synthesis process. Next using the patterned SiO₂ layer (Figure 7.9d) or the Pt heater itself (Figure 7.9d′) as the etching mask, an anisotropic deep-reactive-ion etching (DRIE) of silicon is performed to create trenches around the heater. Finally, isotropic silicon dry etching is performed to undercut the silicon underneath to release the microheater hotplates (or bridges) suspended over the cavity (Figure 7.9e and e′). The localized heating is realized by using a DRIE silicon dry-etching process to form a cavity to obtain a good thermal isolation. In Section 7.3, we will see that the process proposed for mock-CMOS microheater fabrication is fully transferable for releasing microheaters integrated in CMOS substrates.

FIGURE 7.9 Cross-sectional view of the proposed process flow. (a) PECVD SiO₂ deposition. (b) Pt sputtering and liftoff to form heater and pads. (c, c′) Top PECVD SiO₂ deposition and patterning. (d, d′) Anisotropic Si dry etch. (e, e′) Isotropic Si dry etch and heater release.

Three types of microheaters that are introduced in Section 7.2.1 have been fabricated and characterized. Figure 7.10 shows some SEM pictures of fabricated micro-heaters. The first design (Figure 7.10a) is an 87 × 87 μm² micro-hotplate with a symmetric meander Pt heater embedded.

FIGURE 7.10 SEM pictures of fabricated microheaters. (a) Design 1: Pt heater embedded in a micro-hotplate. (b) Design 2: Pt heater in a curved shape. (c) Design 3: Pt heater with two straight lines in parallel, labeled A, B, and C, respectively. L₁ and L₂ represent the effective length of the heater (80 μm) and the length of the cavity (about 95 μm), respectively. (d) Cross-sectional view of the device (line MM" in b).

The second (Figure 7.10b) is a serpentine microheater design. The dark region is the etch-through openings that are patterned during the step shown in Figure 7.9c. It corresponds to the trench shown in Figure 7.10d. The white region surrounding the center Pt heater in the SEM picture in Figure 7.10b is pure silicon oxide with no silicon underneath, as illustrated in Figure 7.10d. Therefore the white region outlines the size of the microcavity below the microheater. Its bright color is an artifact due to the charging effect of the sample during SEM imaging. Due to its serpentine shape, some pure silicon oxide was left between etch openings as the extra mechanical supports. This was found to be necessary. A test structure with a similar serpentine shape but no extra mechanical supports sagged down obviously after the release. Although this suspended microstructure still can function as a microheater, one can imagine that the mismatch of the thermal coefficient of expansion between CNT and Pt heaters may induce thermal stress that will increase the probability of detachment of the synthesized CNTs from the microheaters.

The third design (Figure 7.10c) is a straight-line Pt microheater. It is 5 μm wide and 120 μm long. The top SiO₂ layer is etched during the step shown in Figure 7.9c′, and thus the Pt is exposed to facilitate the electrical contact with CNTs. The exposed Pt is 80 μm long, defined as the effective length of the microheater L₁. Similarly, the white region is pure SiO₂, representing the cavity boundary, and the effective length is labeled L₂. In this design, two extra parallel Pt lines are placed on the left and right sides of the heater and labeled A and C, respectively. They are used as the second walls for CNT landing during the growth, and also as the second electrodes for extracting electrical signals after CNT growth. The trenches are 3 μm (left) and 6 μm (right) wide, respectively. For each microheater, there are two big pads for applying electrical voltage to generate heating. Another pair of electrodes is designed to apply a proper E-field if necessary (as shown in Figure 7.10, labeled “E-field electrode”).

7.2.2.2 Microheater Characterization

After device fabrication, the microheaters are characterized before performing growth experiments. The characterization is designed to measure the following properties. First, for the purpose of successful SWNT synthesis, the maximum temperature that can be reached by resistive heating and the reliability of the microheaters under such high-temperature conditions are two key factors. Then for the purpose of integrating SWNTs on CMOS chips, the local temperature distribution is a major concern, i.e., a sharp temperature gradient is desired so that the temperature can decrease rapidly from the heater center toward the substrate.

7.2.2.2.1 Maximum Temperature Estimation

The mechanical robustness at high temperature was first tested by baking microheaters in an oven at 900°C for 20 min. Both the oxide/Pt/oxide and Pt/oxide bimorph structures were expected to undergo strain incompatibility primarily due to the thermal expansion mismatch of different materials. Although slight sags were observed, all the microheaters survived the high-temperature treatments with no rupture occurring.

Then the working temperature of microheaters was evaluated using the micro-hotplate design. It has been reported that platinum has the optimum thermoresistive characteristics, and Pt resistance thermometers have served as the international standard for temperature measurements between −259.34 and 630.75°C [54]. In a linear approximation, the relation between resistance and temperature is given as follows:

$R_{T} = R_{0} (1 + α \cdot Δ T)$ $R_{T} = R_{0} (1 + α \cdot Δ T)$

(7.1)

in which R₀ is the initial resistance, R_T is the resistance dependent on temperature, α is the temperature coefficient of resistance (TCR), and ΔT is the temperature change. The de facto industrial standard value of TCR is 0.00385/°C, but thin-film platinum exhibits a coefficient that tends to decrease with the thickness. The value of TCR used for our 200 nm thick Pt microheater is about 0.00373/°C, which is obtained from Clayton’s report [54]. The microheater was electrically connected using silver epoxy and then characterized. The experimental current-voltage relation was plotted in Figure 7.11a. The resistance under each power supply can be calculated, and the corresponding temperature can be estimated based on the change of the Pt heater resistance and the TCR of Pt. The resistance of the micro-hotplate was about 46 Ω at room temperature. It increased to 212.5 Ω when the applied current was increased to 14 mA. Therefore the maximum temperature was estimated to be above 900°C based on Equation 7.1 (Figure 7.11b).

For the temperature obtained by this method, it should be noted that the calculated temperature is only an approximation and subject to the following assumptions. First, the resistance measurement is simplified. The resistance measured is actually the sum of the contact resistance and the heater’s resistance: R_Total = R_contact + R_resistor Further, the overall heater’s resistance, R_resistor should consider both the 200 nm Pt layer and the 30 nm Cr adhesive layers. At 20°C, the electrical resistivity of Cr is 125 nΩ · m, while the electrical resistivity of Pt is 105 nΩ · m [55,56]. Second, under Joule heating, the microheater actually exhibits varying temperature along the heater rather than one uniform temperature. Thus the calculated temperature is an approximation of the average temperature of the entire heater.

FIGURE 7.11 (a) I-V characterization of the microheater. (b) Temperature estimated based on resistance change.

FIGURE 7.12 Microscopic images under applied voltages of (a) 2.28 V, (b) 2.62 V, and (c) 3.00 V, respectively.

7.2.2.2.2 Heating Experiment

During the I-V characterization experiment, red glowing of the microheaters under different voltages was clearly observed under an optical microscope, as shown in Figure 7.12. This red glowing can be switched between “on” and “off” instantaneously by controlling the power supply, indicating much shorter response times than traditional CVD processes. The localized microheating combined with this fast response greatly reduces the total power consumption and improves the temperature budget of post-CMOS processing. In addition, we need an indicator to determine when the microheater has reached the required high temperature so that we can stop increasing the power and start the CNT synthesis process. Due to different structure designs or fabrication variations between devices, individual microheaters require different electrical powers to reach the same temperature. Thus neither current nor voltage is a good indicative parameter unless each microheater is characterized under the growth condition and the temperature-power relation is established for each device before the real growth. Instead, the incandescence, the emission of visible light from a hot body due to its temperature, of platinum microheaters observed as red glowing indicates that the heater reaches the required high temperature. In practice, we start flowing in synthesis gases once the red glowing is observed.

7.2.2.2.3 High-Temperature Reliability

After assessing the maximum temperature, the reliability of the microheaters at high temperature was then evaluated. Although bulk platinum has a high melting point (1768°C [56]) and is extraordinarily stable at high temperature, the degradation of platinum thin films at high temperature has been reported by several groups [57,58,59,60]. As shown in Figure 7.13a, we observed a kink point in the curve at higher voltage, and a negative slope between 1.2 and 1.4 V before the microheater was broken. To study the negative slope region, another newly released platinum thin-film microheater with the same design was tested. The voltage was gradually increased from 0 to 1.5 V and then swept back to 0 V. The sweepings were repeated from 0 to 1.5 V and from 0 to 1.8 V. As shown in Figure 7.13b, the negative slope only occurred during the first 0–1.5 V voltage sweeping. After that, the electrical characteristics changed and became repeatable as a result of a permanent change in the platinum resistance.

FIGURE 7.13 (a) Embedded straight-line platinum microheater I-V characteristics. Negative slope was observed between 1.2 and 1.4 V. (b) Heater characteristics under repeated sweepings. (c) Microheater resistance under repeated sweepings. Inset: resistance characterization of the 100 nm Pt/10 nm Ti film, reported in literature [57]. (d) Sheet resistance for 205 nm Pt/15 nm Ta and 145 nm Pt/15 nm Ta thin film, (1) before and (2) after 830°C heat treatment, as reported in literature [61].

Briand et al. reported that the resistivity of the Pt/Ta thin film increased after a heat treatment of 95 min at 830°C, regardless of the film thickness (Figure 7.13d) [61]. Replotting the electrical characteristics we obtained (Figure 7.13b) as resistance versus power in Figure 7.13c, we found that the resistance increased from 134 Ω to 185 Ω after the voltage sweeping. This resistance increase is explained as the result of self-heating treatment through resistive Joule heating, with points A′ and B′ corresponding to points A and B in Briand’s paper, respectively. There might be a critical point that is associated with this high-temperature degradation. This critical temperature might be different for Pt thin films with different configurations, such as thickness, structure, type of adhesion layer, etc. Firebaugh et al. reported that the resistance of their 100 nm Pt/10 nm Ti film was well behaved up to ~900°C, beyond which holes started to form in the film and resistance increased rapidly [57] (Figure 7.13c, inset).

For our device, the critical temperature was believed to be reached at the center of the microheater when the power was increased to around 6 mW, and the rest of the microheater later underwent similar temperature treatment when the input power was continuously increased to about 8 mW.

Several factors attribute to the degradation of platinum thin films, including interdiffusion and reaction between the Pt layer and the adhesive layer, stress, and platinum silicide formation [60], but the agglomeration of continuous thin films into islands of material is believed to be the dominant mechanism [57]. Agglomeration involves the nucleation and growth of holes in the film, and it is driven by the high surface-to-volume ratio of the thin films. The surface diffusivity is dependent on the temperature, and the diffusion of metal atoms on surface tends to reduce the surface-to-volume ratio through capillarity [62]. The sizes for the initial holes must be larger than the thickness-dependent thermodynamic critical radius, and the holes will then grow under the surface diffusion-driven capillarity [63]. As reported by Firebaugh et al. [57], holes started to form in the platinum thin film at around 900°C, and gradually increased in size with time, resulting in the discontinuity (Figure 7.14). Note that the hole growth rate is slow and the film lifetime is sufficiently long, compared with the time required for CNT growth. To avoid agglomeration, thin-film thickness greater than 1 μm was recommended [57]. For our 200 nm platinum microheaters, we noticed that although the film is not sufficiently thick, all the microheaters are capable of withstanding a sufficient amount of time required for the CNT growth process.

7.2.2.2.4 Local Temperature Distribution

In addition to the maximum temperature and the heater reliability, the local temperature distribution is also of vital importance. It was investigated using a QFI InfraScope. The thermal image of the straight-line microheater is shown in Figure 7.15a. Since the maximum working temperature of this infrared imager is 400°C, only 0.6 V was applied to the microheater. Figure 7.15d and e shows the temperature distributions along and transverse to the platinum heater line, respectively. Note that the InfraScope stage was heated to 60°C to facilitate accurate temperature measurement for this image. It is clearly shown that the temperature is near uniform at the region ±30 μm from the microheater center. This is the optimal region for CNT growth. Meanwhile, even though the temperature is as high as 400°C around the heater center, the temperature outside the microcavity drops quickly to about 100°C. Therefore the temperature distribution is compatible with the post-CMOS processing even when the supply power must be increased to provide the desired growth temperature of ~900°C. By accurately choosing the spacing between CMOS circuits and microheaters, this localized microheating method can integrate CNTs at a close proximity of the CMOS devices on the same chip. For designs 1 and 2, the corners of the microheaters have slightly higher temperatures due to the current crowding effect, as evident from their thermal images (as shown in Figure 7.15).

FIGURE 7.14 The formation and growth of holes in the 100 nm Pt/10 nm Ti thin film. (a) After 0 h at 900°C. (b) After 2 h at 900°C. (c) After 6 h at 900°C. (d) After 9 h at 900°C. Reported in literature [57].

7.2.3 ROOM TEMPERATURE CARBON NANOTUBE SYNTHESIS

After device fabrication and characterization, the samples were coated with alumina-supported iron catalyst by drop-drying. Two contact pads were connected to a voltage-controlled power supply by clamps. And then the sample was placed into a quartz tube. After 5 min of argon purging, the microheater was heated up to the state that red glowing could be observed. For example, design 2 needs a supply voltage of 3–3.5 V. Then a mix of 1000 sccm CH₄, 20 sccm C₂H₄, and 500 sccm H₂ was flowed into the quartz tube for CNT growth. After a 15 min growth, SWNTs and MWNTs with diameters ranging from 1–10 nm were successfully synthesized on all three types of suspended microstructures.

FIGURE 7.15 Thermal imaging. (a) Thermal image of design 1 by applying 0.93 V DC voltage. (b) Thermal image of design 2 by applying 1.2 V DC voltage. (c) Thermal image of design 3 by applying 0.6 V DC voltage. (d, e) Corresponding temperature distribution along and transverse to the microheater, indicating good thermal isolation. (The substrate temperature is 60°C.)

Figure 7.16 shows a dense film of CNTs grown on the micro-hotplate surface. Some interesting coiled nanostructures, as shown in the insets in Figure 7.16, are observed on many samples. The orientations of these CNTs are random since there was no guiding electrical field during growth.

On the other hand, for the other two designs with trenches and secondary landing walls, the supplied voltage simultaneously introduces an E-field (about 0.1 ~ 1.0 V/μm) between the microheater and a nearby ground electrode/oxide wall. As a result, most of the suspended CNTs grown on these two types of microheaters exhibit a significant alignment along the E-field perpendicular to the cold wall, as shown in Figure 7.17. As demonstrated in our experiments, with proper designed microheaters and trench widths, the desired temperature profile and E-field distribution can be obtained by the same power supply. The extra pair of backup electrodes designed to enhance the E-field was not used, and thus can be removed to simplify the design in the future. Although the microheater corners have a higher temperature and stronger E-field, comparing the SEM images (shown in Figure 7.17a and b) reveals that there is no significant difference between the growth around the corners and the rest of the microheater. When the microheater is further simplified into one straight line (design 3), we find that the alignment is further improved, as shown in Figure 7.17c, and the CNT growth is uniform along the length of the entire microheater, except on the small regions next to the anchors. These results are in good agreement with the measured temperature distribution. Hence the microheater geometry with either a relatively larger hotplate or a small hotspot can be customized to control the temperature distribution for regulating the CNT growth for various applications.

FIGURE 7.16 Dense film of CNTs over micro-hotplate surface (design 1). Insets: Coiled nanostructures observed in the growth.

FIGURE 7.17 Localized synthesis of CNTs suspended across the trench, showing good CNT alignment. (a, b) Zoom-in SEM of CNTs grown on design 2. (c) Zoom-in SEM of CNTs grown on design 3 (from second batch, with no Cr on top). Insets: SEMs of overall microheaters.

7.3 MASKLESS POST-CMOS-CNT SYNTHESIS ON FOUNDRY CMOS

In the previous section, localized CNT synthesis on mock-CMOS substrates has been demonstrated. We have proved that, based on the voltage-controlled localized heating, suspended on-chip microheaters can provide both uniform high temperature for high-quality CNT growth and good thermal isolation for the CMOS compatibility requirement. Repeatable and well-aligned CNT growth can be realized, and the simple straight-line microheater is promising for further scaling down to a hotspot. However, a number of vital questions have yet to be settled. First, platinum may not be available in foundry CMOS processes, and thus some other materials need to be used to form microheaters. Second, the process flow described in Section 7.2.2 requires two lithography steps for patterning microheaters and release openings, which is still too complicated for post-CMOS processes. Third, the integration presented in Section 7.2 did not involve the interconnection of CNTs with CMOS circuits in the monolithic integration. To address these issues, we present a simple and scalable CMOS-CNT integration approach in this section. CNTs are selectively synthesized on polysilicon microheaters embedded aside the CMOS circuits using localized heating and maskless post-CMOS surface micromachining techniques. There is no need of any photomasks, shadow masks, or metal deposition to achieve the localized synthesis and the CNT-polysilicon electrical contact. Successful monolithic CMOS-CNT integration has been demonstrated [64]. And it is verified that the electrical characteristics of the neighboring NMOS and PMOS transistors are unchanged after CNT growth [64].

7.3.1 INTEGRATION PRINCIPLES AND DEVICE DESIGN

As illustrated in Figure 7.18, the basic idea of the monolithic integration approach is to use maskless post-CMOS MEMS processing to form microcavities for thermal isolation and use the gate polysilicon to form the heaters for localized heating as well as the nanotube-to-CMOS interconnect. The microheaters, made of the gate polysilicon, are deposited and patterned along with the gates of the transistors in the standard CMOS foundry processes. Except the shape and dimensions, the polysilicon microheaters are equivalent to the transistor gate, and thus they share exactly the same subsequent processes, i.e., the vias, interconnects, passivation, and I/O pads. One of the top metal layers (i.e., the metal 3 layer, as shown in Figure 7.18b) is also patterned during the CMOS fabrication. It is used as an etching mask in the following post-CMOS microfabrication process for creating the microcavities. Finally, the polysilicon microheaters are exposed and suspended in a microcavity on a CMOS substrate, while the circuits are covered under the metallization and passivation layers, as illustrated in Figure 7.18b. Unlike the traditional thermal CVD synthesis that heats up the whole chamber to above 800°C, the device with embedded microheaters works like a miniaturized CVD array: The CVD chamber is kept at room temperature all the time, with only the microheaters activated to provide the local high temperature for CNT growth.

FIGURE 7.18 (a) The 3D schematic showing the concept of the CMOS-integrated CNTs. The CVD chamber is kept at room temperature all the time. (b) Cross-sectional view of the device. (c) The schematic 3D microheater showing the local synthesis from the hotspot and self-assembly on the cold landing wall under the local electric field.

The top view of a microheater design is shown in Figure 7.18c. The configuration is similar to that of the platinum microheaters. There are two polysilicon bridges: one as the microheater for generating high temperature to initiate CNT growth and the other for CNT landing. With the cold wall grounded, an E-field perpendicular to the surface of the two bridges will be induced during CNT growth. Activated by localized heating, the nanotubes will start to grow from the hotspot (i.e., the center of the microheater) and will eventually reach the secondary cold bridge under the influence of the local E-field. Since both the microheater bridge and the landing bridge are made of a gate polysilicon layer and have been interconnected with the metal layers in the CMOS foundry process, the as-grown CNTs can be electrically connected to CMOS circuitry on the same chip without any post-growth clamping or connection steps.

As discussed in Section 7.2.1, the microheater design is of vital importance. The gate polysilicon layer is thin and its thickness is determined by the foundry CMOS processes. For the AMI 0.5 μm CMOS process [65] used in this work, the polysilicon thickness is 0.35 μm. Since the serpentine design showed no meaningful advantages of the corner effect but required extra mechanical supports in the previous mock-CMOS synthesis experiments, a straight-line-shaped microheater is adopted for its superior mechanical robustness and simple design. A typical heater design is shown in Figure 7.19a, which is basically a polysilicon resistor. Since the temperature has to reach at least as high as 800°C for SWNT growth and drop quickly to avoid deteriorating the surrounding CMOS circuits, the thermal isolation, thermal stresses, and structural stiffness must be carefully considered during microheater design. Since thermal resistance is proportional to the length of a resistor, short resistors tend to dissipate heat faster, so that reaching high temperature requires more power, while long resistors tend to have mechanical stiffness issues. In addition, the current density limitation of the polysilicon resistors and the limitation of the release process do not allow us to design microheaters with too narrow width. As a result of considering all these factors, the heating unit first investigated is a 3 μm long and 3 μm wide polysilicon resistor.

FIGURE 7.19 (a) A typical heater design with stripe-shaped resistor. (b) Simulated temperature distribution along the surface of the microheater at an applied voltage of 2.5 V through the pads. The area of polysilicon microheater is 3 × 3 μm, and a thickness of 0.35 μm is chosen according to the CMOS foundry process. Inset: An SEM image of a microheater after CNT growth. (c) The line plot of the temperature along the heater (line AA′ in b).

TABLE 7.1
MOSIS AMI C5 Technology

Structure	Min	Typ	Max	Units
N+ poly sheet res	23	30	37	Ohms/sq
CMP M3 thickness	7000	7700	8400	Å
CMP M3 to M2 dielectric	10,000	11,000	12,000	Å
CMP M2 thickness	5000	5700	6400	Å
CMP M2 to M1 dielectric	10,000	11,000	12,000	Å
CMP M1 thickness	5700	6400	7100	Å
Poly thickness	3000	3500	4000	Å
Field ox under poly	3500	4000	4500	Å
Via allowed current density	1.6 (85°C),	0.6 (125°C)		mA/cnt
Metal allowed current density per width	2.2 (85°C);	0.85 (125°C)		mA/μm

Electrothermal modeling in a multiphysics finite element method tool, COMSOL [66], has been used to simulate and optimize the microheater design. The simulation results are shown in Figure 7.19b and c, where a typical polysilicon sheet resistance of 30 Ω/□ and other material properties are chosen according to the employed foundry process [65] (see Table 7.1). For the simulation, the convection and radiation heating losses are neglected as the heating area is small. The substrate bottom surface is assumed to stay at room temperature. Figure 7.19b shows the temperature distribution when a 2.5 V activation voltage is applied to the heater. It shows good agreement with the post-growth surface pattern (Figure 7.19b, inset SEM image), which is believed to reflect the temperature distribution during the growth. Figure 7.19c plots the temperature distribution along the microheater. It shows an ideal condition for CMOS-CNT integration: a very small, localized high-temperature region for CNT growth and a sharp temperature decrease toward the substrate.

Based on this 3 × 3 μm² heating unit, a series of heater design variations have been investigated. First, to exploit the geometry limitations (mainly the mechanical robustness and electrothermal properties), six line-shaped microheaters are designed with dimension variations. The width ranges from 1.2 to 6 μm, and the length ranges from 1.2 to 40 μm. Second, two types of secondary walls are designed: One is a bridge parallel to the microheater for uniform E-field formation (Figure 7.20a), and the other is a sharp tip (or multiple tips) to form a converged E-field (Figure 7.20b). The gap between the two polysilicon microstructures is typically 3–6 μm in order to obtain the proper electric field and facilitate the CNT landing. Third, opposing sharp tips (Figure 7.20c) are also designed to facilitate the CNT bridge formation since CNTs tend to attach to the nearest support boundary [67]. Finally, instead of grounding the secondary wall, some designs have five configurable inputs. As illustrated in Figure 7.20a, four pads can input different voltages to tune the electric field, and the fifth input (not shown) is connected to the substrate as a global back gate for studying the electrical gating effect.

The final CMOS chip includes test circuits and 13 embedded microheaters. The schematic layout is shown in Figure 7.21. Microheaters are placed around the center, and they are independent from each other. Four test circuits are placed close to the microheaters with spacings ranging from 36 to 60 μm. The spacings are chosen based on the temperature distribution investigation shown in Figure 7.15. The sizes of the NMOS and PMOS transistors, which are the subject of our investigation, are W_n/L_n = 3.6 μm/0.6 μm and W_p/L_p = 7.2 μm/0.6 μm, respectively. All the areas outside the central square in Figure 7.21c are covered with the metal 3 layer. It is patterned as the etching mask that covers all the circuit area beneath but has 13 etching openings, with one opening for each individual microheater. The etching opening as shown in Figure 7.21c determines the size of the microcavity. The microcavities will be formed when the top silicon dioxide and bottom silicon are all etched away during the post-CMOS MEMS processes, leaving only the suspended microheaters, as shown in Figure 7.18a and b.

FIGURE 7.20 Schematic layouts showing (a) a 3 × 10 μm microheater with a paralleled bridge as the secondary wall and four configurable input pads, (b) a 6 × 20 μm microheater with multiple tips as landing walls, and (c) a microheater with opposing sharp tips.

FIGURE 7.21 (a, b) Schematic layouts of the chip, including test circuits and 13 embedded microheaters. The spacings between the microheaters and circuits vary from 36 to 60 μm. (c, d) Close-up views of a microheater with metal 3 as etching opening mask and metal 1 as etching protection.

However, there is a selective etching issue. In the cases where the microheaters are made of platinum, specific etch chemistry can be used to etch away silicon dioxide or silicon completely with little etching to platinum. Thus etching protection for the heaters is not necessary, and the platinum microheaters themselves can be used as masks once the heaters’ shapes have been patterned. When switching the heater material to polysilicon, this is no longer the case. Both the dioxide etchant (dry etch) and silicon etchant will etch polysilicon. Recall that the polysilicon thickness is only 0.35 μm. Thus etching sequence needs to be carefully designed and etching protection is essential. In our design, the metal 1 layer above the microheater is patterned with the same shape as the microheater, but with a slightly greater width, as shown in Figure 7.21d. This patterned metal 1 layer will protect the microheaters during the first few steps when the etchants can react with polysilicon, and then it will be removed using polysilicon-safe etching recipes. Details will be presented in the device fabrication section.

7.3.2 DEVICE FABRICATION AND CHARACTERIZATION

After the layout design, the CMOS chips are fabricated through MOSIS using the commercial AMI 0.5 μm three-metal CMOS process [65]. The gate oxide thickness is 13.5 nm. The estimated layer thicknesses and other parameters are listed in Table 7.1. Several parameters in the table have been used in the modeling in the previous section. In addition, the thickness of each layer is used to estimate the etching time in the post-CMOS fabrication processes. The current density limits have also been taken into consideration when designing the metallization.

Figure 7.22a shows the schematic cross-sectional view of the CMOS chip after the foundry processes but before any post-CMOS MEMS fabrication. The metal 1 and metal 3 layers have been patterned as described in the previous section. The corresponding optical microscope image is shown in Figure 7.23a. The total chip area is 1.5 × 1.5 mm². Due to this small size, individual chips are mounted on top of a 4-inch carrier wafer for easy handling and processing. The center big square is the metal 3 layer. In addition to the 13 etching openings to expose the microheaters, there are 6 extra opening windows in the center. These are dummy structures for etching rate control. There are 32 outer pads for microheaters and 16 inner pads for circuits. These pads, as well as the area uncovered by metal 3, need to be covered with photoresist for protection before any release processes.

The maskless post-CMOS MEMS fabrication process flow that used to release the polysilicon microheaters is shown in Figure 7.22. It starts with the reactive ion etching (RIE) of silicon dioxide (Figure 7.22b). The metal 3 layer of the CMOS substrate is used as etching mask to protect the CMOS circuit area, and it also defines the cavity opening size. Within the cavity, the anisotropic etching, which uses a mixture of CHF₃ and O₂ as the etch chemistry, is mainly in the vertical direction. As a result, three steep trenches are formed, but the oxide under metal 1 is almost unattacked. Thus the polysilicon microheaters are entirely wrapped inside silicon dioxide. Next the exposed aluminum is etched by RIE (Figure 7.22c), using BCl₃, Cl₂, and Ar. At this point, the photoresist should be removed since the pad protection is no longer needed in the following steps, and removing it after the release step may damage the suspended microstructures. Then an anisotropic deep-reactive-ion etching (DRIE) of silicon is performed (Figure 7.22d) using SF₆ and C₄F₈ as the etching and passivation chemistry, respectively, to create a roughly 6 μm deep trench around the heater. Next an isotropic silicon etching using only SF₆ is performed to undercut the silicon under the microheaters (Figure 7.22e), resulting in suspended microheaters in microcavities. In these two steps of silicon etching, polysilicon will be quickly etched away if exposed. The silicon dioxide will also be etched, but at a much slower rate. As mentioned previously, metal 1 is designed slightly wider than the polysilicon microheaters. The width difference determines the thickness of the sidewall protective silicon dioxide. The oxide sidewall must withstand the etching during the two silicon etching steps so that the polysilicon microheaters will remain unattacked. The final step is to etch away the thin oxide protective layer surrounding the microheaters using a 6:1 buffered oxide etchant (BOE) at room temperature for approximately 5 min to expose the polysilicon for electrical contact with CNTs (Figure 7.22f). This BOE wet etch has a very high etching selectivity between silicon and silicon dioxide. Overall, since all the required etching masks have been patterned in the foundry processes, the post-CMOS MEMS fabrication is simple and easy to control, requiring only RIE, DRIE, and BOE etching.

FIGURE 7.22 Mastless post-CMOS MEMS fabrication process flow: (a) CMOS chip from foundry. (b) SiO₂ dry etch. (c) Al etch. (d) Anisotropic Si dry etch. (e) Isotropic Si dry etch and heater release. (f) SiO₂ wet etch.

Optical microscope images of the CMOS chip before and after the post-CMOS processing are shown in Figure 7.23a and b, respectively. A close-up optical image of one microheater is shown in Figure 7.23c. The nearby circuit, although visible, is protected under a silicon dioxide layer. Only the microheater and cold wall within the microcavity are exposed. To satisfy the spacing, the microstructures are rearranged such that the microheater is closest to the circuits and the secondary wall is on the opposite side. The polysilicon heater is connected to the metal interconnect by a number of vias. The quantity of the vias is determined by two factors: the current that is required for Joule heating and the maximum current that one single via can withstand (see Table 7.1). SEM images of two microheaters are shown in Figure 7.23d and e, with the resistances of 97 and 117 Ω, respectively. The design is simple and the released microstructures are mechanically robust. All 13 microheaters, including the sharp-tip design and the 40 μm long design, survived the post-CMOS processes. Five chips have been fabricated with a yield of 100%, indicating the robustness of the maskless post-CMOS MEMS processes.

FIGURE 7.23 (a) The CMOS chip photograph (1.5 × 1.5 mm²) after foundry process. (b) The CMOS chip photograph after post-CMOS process (before final DRIE step). (c) Close-up optical image of one microheater and nearby circuit. CMOS circuit area, although visible, is protected under silicon dioxide layer. Only the microheater and cold wall within the microcavity are exposed to synthesis gases. Polysilicon heater and metal wire are connected by vias. (d, e) Close-up SEM images of two microheaters.

Similar to the mock-CMOS samples, polysilicon microheaters were also characterized before the CNT growth experiments. The measured current-voltage relation is plotted in Figure 7.24a. However, extracting the temperature-dependent resistivity from the I-V characterization and then using the resistivity to estimate the temperature becomes difficult due to the following reasons. First, grain boundaries in polysilicon exhibit charge carrier trapping that contributes to the temperature-dependent behavior [68]. Second, dopant concentrations have a significant impact on the temperature-dependent resistivity of polysilicon. For low to moderate dopant levels (≤10¹⁸ cm^–3), increased temperature offers higher thermal energy that excites more dopant electrons to the conduction band [69], resulting in a negative TCR. Such temperature-dependent behavior is undesirable since it will cause eletrothermal instability at high temperature. For heavily doped polysilicon (≥10¹⁹ cm^–3), if neglecting the grain boundary effects, the temperature-dependent resistivity can be defined as

FIGURE 7.24 (a) I-V characterization of a 6 × 20 μm microheater. (b) Resistance extracted from the I-V characterization. (c–f) Microscopic images of a microheater: (c) before applying power, (d) starting to glow at 2.20 V, (e) showing bright glowing at 2.38 V, and (f) burnt after applying 2.47 V. Inset: Filament I-V characteristics showing the kink point. (From C.H. Mastrangelo et al., IEEE Transactions on Electron Devices, 39, 1363–1375, 1992. With permission.)

$\frac{1}{ρ} = p | e | (μ_{e} + μ_{h})$ $\frac{1}{ρ} = p | e | (μ_{e} + μ_{h})$

(7.2)

in which ρ is the resistivity, p is the free electron concentration, e is the magnitude of an electron charge, and μ_e and μ_h are the electron and hole mobility, respectively [70]. Since the majority of the dopants’ outermost electrons in heavily doped N+ silicon are already in the conduction band, the free electrons that are thermally activated from the donor no longer dominate the resistivity. Instead, the temperature-dependent behavior is dominated by the carrier mobilities at high doping levels, resulting in a positive TCR and a linearly increased resistance within the temperature range from 300 to 800 K. Lattice and impurity scattering mobility, μ_L and μ_I, respectively, are found to have significant contributions to the charge carrier mobility at high temperature [70]. The mobility terms can be expressed in the following forms:

${\begin{array}{l} μ_{L} α T^{a} & - 2.7 < a < - 1.5 \\ μ_{I} {αT}^{b} & 1.5 < b < 2 \end{array}$ ${\begin{array}{l} μ_{L} α T^{a} & - 2.7 < a < - 1.5 \\ μ_{I} {αT}^{b} & 1.5 < b < 2 \end{array}$

(7.3)

and the temperature-dependent resistivity can be expressed by a general equation [70]:

$ρ = α_{1} + α_{2} T^{α_{3}}$ $ρ = α_{1} + α_{2} T^{α_{3}}$

(7.4)

in which the parameters α₁, α₂, and α₃ have to be extracted empirically. For our microheaters, based on the polysilicon sheet resistance and the thickness, the resistivity ρ is estimated to be 1.05 × 10^–5 ohm⋅m, and the impurity doping level is estimated to be above 10¹⁹ cm^–3 using Equation 7.2.

Although a high doping level requirement has been satisfied and a positive TCR has been confirmed from the resistance calculation (as plotted in Figure 7.24b), the electrical characteristics of the microheaters were found to be unstable at temperatures beyond the polysilicon recrystallization temperature T_cr (at roughly 870 K [71]), and the linear increase in resistance no longer exists. Mastrangelo et al. reported that the resistance of a heavily doped polysilicon filament decreases when the bias is beyond a kink point (Figure 7.24 inset, point P) [72]. For the microheater we investigated, the kink point P happens around a bias voltage of 2 V (see Figure 7.23a and Figure 7.24b). Possible mechanisms reported include current-induced resistance decrease [73,74], filamentation [75], and the polysilicon thermal breakdown [76,77].

Continuing to increase the bias voltage, red glowing was first observed in the dark at 2.20 V (Figure 7.24d), and it quickly became much brighter at 2.38 V. The heater was burnt at the center under a bias voltage of 2.47 V, as evident from the comparison between Figure 7.24c and Figure 7.24f. As previously discussed, the extraction of temperature above the polysilicon recrystallization temperature is quite difficult due to its unstable electrical characteristics. Again, the incandescence of the microheater becomes a good indication of high temperature. Ehmann et al. carefully calibrated a microheater, which is also made of n-doped CMOS gate polysilicon, and estimated that the average heater temperature was about 1200 K when incandescence was observed in the dark [78]. In addition, Englander et al., who first locally synthesized CNTs on suspended polysilicon MEMS structures, reported that based on their growth results, the barely glowing condition, which is the condition when glowing is just started and still weak, offered the proper temperature (850 to 1000°c) for maximum CNT growth (prior glowing was too cold while bright glowing was too hot) [49]. Therefore the microheaters we designed and fabricated are capable of providing the high temperature required for CNT growth, and it can withstand a sufficient amount of time under the barely glowing state. The local temperature distribution is not characterized. Instead, the performances of test circuits and individual transistors are recorded, and will be compared with their performances after CNT growth to assess the effectiveness of the thermal isolation.

FIGURE 7.25 Localized synthesis of carbon nanotubes grown from (a) the 3 × 3 μm micro-heater and (b) the 6 × 6 μm microheater, suspended across the trench and connecting to the polysilicon tip/wall. Insets: SEM images of the overall microheater.

7.3.3 ON-CHIP SYNTHESIS OF CARBON NANOTUBES

After the microheater release, the CMOS chips were carefully taken off from the carrier wafer and then wire bonded to DIP packages. Next the chips were coated with alumina-supported iron catalyst by drop-drying on the surface [28]. The whole package was then placed into a quartz chamber. The on-chip microheaters were turned on by applying appropriate voltages such that bare growing was observed. The supplied voltage also introduced a local E-field of about 0.1 ~ 1.0 V/μm. The CNT growth was carried out using 1000 sccm CH₄, 15 sccm C₂H₄, and 500 sccm H₂ for 15 min, while the chamber remained at room temperature all the time.

After 15 min of growth, CNTs were successfully synthesized. Two SEM images with locally synthesized CNTs are shown in Figure 7.25. The individual suspended CNTs in Figure 7.25a were grown from the 3 × 3 μm microheater, as shown in Figure 7.23e, and landed on the near polysilicon tip. In the configuration with a parallel bridge as the secondary landing wall, the growth exhibits less convergence due to the less converging E-field. Similar growth occurred on 11 out of 13 microheaters. The 1.2 × 1.2 μm microheater and the one with opposing sharp tips were broken during the growth. The reason might be the presence of super-local heating that caused the failure at grain boundaries.

7.3.4 CHARACTERIZATION OF CARBON NANOTUBES AND CIRCUIT EVALUATIONS

After the growth, the as-grown CNTs were characterized by measuring the resistance between two polysilicon microstructures (the microheater and the landing wall) at room temperature and at atmosphere. The I-V characteristic is shown in Figure 7.26. The typical resistances of in situ-grown CNTs are in the range of several MΩ. This large resistance is primarily attributed to the contact resistance between the polysilicon and the CNTs. Recall that the final step of the post-CMOS fabrication is meant to completely remove the silicon dioxide, and thus fully expose the polysilicon surface. However, this step has been done long before the growth process due to the subsequent steps, such as wire bonding, package, and catalyst deposition. A thin layer of native oxide is expected to naturally grow on the polysilicon electrode surface with a typical thickness of about 2 nm [79]. Other factors, such as defects along the CNTs, might also contribute to the large resistance.

FIGURE 7.26 I-V characteristics of the as-grown CNTs. The I-V curve is measured between two polysilicon microstructures contacting the CNTs.

FIGURE 7.27 DC electrical characteristics of single transistors before and after CNT growth. (a) Drain current (Ids) versus grain voltage (Vds) for NMOS transistors under seven different gate voltages. (b) Drain current (Ids) versus grain voltage (Vds) for PMOS transistors under seven different gate voltages.

After the successful on-chip synthesis of CNTs, the impact of the localized heating on the nearby circuits was assessed. As mentioned in Section 7.3.1, the spacings range from 36 to 60 μm. Simple circuits, such as inverters, were first tested and their proper functions were verified after synthesis. Then more accurate electrical characteristics were measured at the transistor level. Figure 7.27 shows the DC electrical characteristics of individual NMOS and PMOS transistors before and after the CNT growth. The tests were performed at room temperature using a Keithley 4200 semiconductor characterization system. The drain current versus drain-source voltage (Ids-Vds) plots show no significant change after the synthesis, demonstrating the CMOS compatibility of this integration approach.

It should be noted that after a short period (approximately 1 month), this MΩ resistance became infinite. But the synthesis on platinum microheaters exhibited kΩ resistances that stayed almost the same after 1 year. These two synthesis experiments used the same catalyst recipe and same growth procedure. The differences come from the electrode material, which results in two types of contacts: one is polysilicon/CNTs versus Pt/CNTs, and the other is polysilicon/catalyst versus Pt/catalyst. There might be two reasons that cause the failure in the polysilicon heater case. First, it might be the result of the continuous oxidation of the polysilicon in air. Another possible reason might be due to the weaker adhesion of the CNTs and catalyst particles to the polysilicon. In our practice, the nanometer-scale iron catalyst particles are separated by and supported on alumina, a thin nonconductive layer. As shown in Figure 7.28, the catalyst on the top of the silicon dioxide surface consists of discrete particles, with the heater outline clearly visible (Figure 7.28a); the catalyst on the top of the platinum surface has a fluffy appearance, with the underneath platinum electrode partially exposed (Figure 7.28b).

However, the catalyst layer appears much thicker on CMOS chips, as evident from Figure 7.28c–f. The catalyst layer extends over trenches (Figure 7.28c). A thick catalyst layer on one of the heaters even cracks and peels off (Figure 7.28d). Some designed shapes (e.g., the multi-tip landing wall) that have successfully survived the post-CMOS fabrication (Figure 7.28e) are unable to be preserved after catalyst deposition (Figure 7.28f). The mock-CMOS devices have platinum microheaters on the surface (Figure 7.28g), while the CMOS chips have polysilicon microheaters hidden inside the microcavities (Figure 7.28h). The topographic profiles, the surface conditions of different materials, and the further miniaturized feature size might all contribute to the thicker catalyst layer, which in return might block the nanotube/polysilicon contacts or result in weak adherence when CNTs reach the secondary electrode.

To improve the chemical stability and mechanical robustness, several possible solutions are recommended for future work. First, instead of using aluminum-supported iron catalyst particles and the drop-drying method, thin-film metal catalysts can be deposited using various techniques, such as evaporation, sputtering, or molecular beam epitaxy techniques [80]. These thin films will “ball up” and break up into particles during the growth as long as the film thickness does not exceed the critical thickness [81]. In this way, the structure shape can be preserved, and the thickness of the catalyst layer can be controlled. Second, contact activation through electrical breakdown in the inert gas environment has been proven to be effective for healing the 2 nm native oxide [82]. Third, polymer deposition after the CNT growth has been reported to be capable of stabilizing the nanotube/electrode contact resistances [83]. This coating might be helpful for preventing the polysilicon from oxidation over time.

7.4 CONCLUSION

Monolithic CNT-CMOS integration can be realized using custom CMOS processes by employing refractory metals for interconnect and SOI CMOS processes. Localized heating is promising for CNT-CMOS integration. Monolithic CNTCMOS integration has been demonstrated on foundry CMOS substrate by combining MEMS microfabrication and localized heating. The post-CMOS microfabrication is maskless. The CNT growth does not affect the characteristics of the transistors on the same chip. As a hotplate is formed from creating the localized heating, integrated CNT-based gas sensors can be made. This CNT-CMOS integration technique has a wide range of applications in chemical, temperature, stress, and radiation sensing.

FIGURE 7.28 SEM images showing the catalyst layers on (a) silicon dioxide surface, (b) platinum microheater surface, and (c) polysilicon microheater surface. (d) An SEM image of one polysilicon microheater with the thick catalyst layer peeled off. (e, f) SEM images of one polysilicon microheater before and after catalyst deposition. Multifigure structure was completely covered by the catalyst layer. (g, h) Schematic cross-sectional views of mock-CMOS platinum heater and polysilicon heater embedded in CMOS chips.

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Table of Contents for Chapter 7 Monolithic Integration of Carbon Nanotubes and CMOS

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Table of Contents for
Chapter 7 Monolithic Integration of Carbon Nanotubes and CMOS