2

Overview of Architecture and Microcontroller Resources

We learnt about the different types of microcontrollers (MCUs), their selection and their various applications in previous chapter.

We will learn in this chapter about the architectures and on-chip resources in MCUs. The chapter describes the resources of memory, ports, DAC, PWM, ADC, timers and watchdog timers. It also describes the power-down mode. Details pertaining to individual MCU resources will be dealt with in later chapters.

2.1 ARCHITECTURE OF A MICROCONTROLLER

2.1.1 Functional Overview of 8048 and 8049 Microcontroller Architecture

The 8048 and 8049 microcontrollers are predecessors to 8051. Figure 2.1 shows a functional overview with the help of a block diagram of an exemplary 8048 microcomputer (microcontroller). Additional details of the basic processing unit are given in Section 2.3.1. Figure 2.2 shows the pin signals in an 8048 series microcomputer. Table 2.1 lists the pin signals. [Bar over a signal means that the signal activates when it is 0. For example, activates read when made 0 by the processor.]

2.1.2 Basic Processing Unit in the 8048 Microcomputer

Figure 2.1 shows that the 8048 has the CPU, clock circuit (oscillator circuit), and reset circuit. This is similar to a microprocessor. There is control and sequencing logic. It functions and sends the signals as in a microprocessor. There are flags for the processor status as in a microprocessor. The parts of a basic processing circuit are as follows: RESET is the signal to reset the CPU when XTAL2 and XTAL1 are crystal oscillator inputs for the processor clock. IR is the instruction register, ID the instruction decoder, ACC the accumulator-latch and A the accumulator. Section 2.3.1 will explain basic processing unit in detail with the examples and refer Example 2.15 for the understanding of the meaning of multiplexing.

Sections other than CPU are as follows:

1. Both internal and external memory can be used in 8048. Since an MCU can be used as a single-chip microcomputer with embedded program in read only memory (ROM), there is an extra feature—on-chip ROM. The ROM is 1 kB in 8048 and 2 kB in 8049. An internal RAM is also present. It saves the temporary variables and stack. The RAM is 64 B in 8048 and 128 B in 8049.
2. An MCU interacts with the I/O devices (ports) like the keyboard and LCD display. It has thus internal I/O ports. For example, there is Port 1. It has the latch. It buffers the port operations.
3. Program counter lower byte is sent to memory address register (MAR) when MCU connects to the additionally required external memory. P0 is used to send the byte in MAR to the memory. It gives A0-A7 signals. P0 is also used as a port (connects through bus buffer) when no additional memory is required, and the MCU operates in a single-chip mode. There is program counter higher byte in MAR. It connects to Port 2 and connects through bus buffer. When the MCU is operated in a single-chip mode port 2 function as port pins P2.0-P2.7. Port 2 has the latch and buffer for the port operations.
   

   Figure 2.2 Pins/Signals in an 8048 Series Microcomputer

4. The I/O devices may be interrupt driven. There is an interrupt service mechanism and interrupt circuit, priority assignment and interrupt mask. The mask is for disabling an interrupt source, when the processing of a specific time critical action takes place.
5. An MCU may be required to do real-time control of events and tasks. There is a programmable timer/event counter for this purpose.

   The 8048 microcontroller has the following sections:

    

6. CPU to process the instructions which are provided in the instruction set for 8048.
7. Address and data bus signals A0-A7 and D0-D7 are multiplexed as bus signals AD0 to AD7. The control signals are , , ALE and . When using the MCU in expended chip mode, the bus signals connect to the external pins P0.0-P0.7 and P2.0-P2.7. P0 sends the address bus signals AD0 to AD7. When ALE is active, the address latch enables the control signal at the pin ALE and the bus sends the address signals.

   Whenever AD0 to AD7 bus has the data signals, the signals at , and signals are used for selecting the external operations. When is active, then there is read from data memory. When is active, then there is write to data memory. When is active, then there is read from the program memory.

    

8. Address bus A8 to A15 output bits: These are the input cum output Port 2 pins—P2.0 to P2.7 in single-chip mode. Figure 2.1 shows P2H—Port 2 higher nibble (4-bit) and P2L—Port 2 lower nibble (4-bit). The same pins provide output as the external address bus signals A8 to A15 in the expended mode.
9. Oscillator: It connects the XTAL1 and XTAL2 pins.
10. Reset circuit: It connects to RESET pin.
11. ROM 1 kB (EPROM 1 kB in 8748).
12. RAM 64 B (128 B in 8049).
13. Interrupt external through pin.
14. An 8-bit timer/event counter: An 8-bit timer/counter means it can count from 00000000b to 1111111b (00H to FFH). When used in the timer mode, the internal clock pulses increment the counter. When used in the counter mode, the external events are used to give the input to the counter for its increment.

Harvard Architecture in Memory

Harvard architecture means that program memory and data memory are separate address spaces and accessed separately by different instructions and control signals. The 8048 can be interfaced to the program memory to store 2¹⁶ bytes for the codes at addresses from 0000H to FFFFH. The 8048 can be interfaced to the data memory to store 2¹⁶ bytes for the codes at addresses from 0000H to FFFFH.

pin—external address enable; it disables the external 1 kB addresses when it is made 1 and the on-chip ROM 1 kB is used in 8048. It enables when it is made 0 then an address of the external 64 kB memory from 0000H is used and internal ROM is then not used.

There are separate control signals to read the codes and data. These are and . When = 0, the code from a program-memory address is read and when = 0, the data from a data-memory address is read.

There is a separate control signal to write the data. When = 0, the data-bits are sent by the processor to a data-memory address when writing and using the external data memory between 0000H and FFFFH.

Program Counter

The 8048 has addressability of code-memoiy from 0000H to FFFFH for 2¹⁶ bytes. Therefore, Program Counter (PC) is of 16 bits.

Figure 2.1 shows program counter in two registers: PCL— program counter lower byte, which has an out bus of 8-bits and when MCU is used in the single-chip mode, PCH—program counter higher byte register, which outputs only 2-bit and its 2-bit out bus to program memory in 8048 (Figure 2.1), 3-bit in 8049 and 4-bit in the 8050 as well as standard 8051/8052 families. This is because of on-chip program memories in 8048, 8049 and 8050/8051/8052 basic versions are 1 kB, 2 kB and 4 kB, respectively. PCH higher byte register outputs 8 bits, when an external memory is used.

Multiplexing of the Lower byte Bus for the Address and 8-bit Data Bus

The external data bus D0 to D7 multiplexes with A0 to A7 by multiplexing in 8048. A byte of code or data can be transferred at an instance. The time interval during which the address latch enable (ALE) is active (=1) P0 there is the address at the multiplexed bus. The time during which the ALE is inactive (= 0) there is data on the bus. Section 2.3.3 gives additional details about the ports.

2.2 FAMILY MEMBERS OF 8051 AND 68HC11/12 FAMILIES

A microcontroller family member has the same basic architecture, but can differ in the number of pins and the mode of packaging. Further, there are different variants as shown in Tables 1.1 and 1.2 for the 8051 and 68HC11/12 families. Figures 2.3 and 2.4 show the families of 8051 series and 68HC11/12/16 series and the resources in these. PIC and ARM microcontroller families will be described in Chapters 13 and 16, respectively.

2.3 MICROCONTROLLER ON-CHIP RESOURCES

Each microcontroller has a basic processing unit (Section 2.3.1) and has a number of resources.

The commonly present resources are as follows:

1. Basic processing unit, internal buses and interrupt handler (Section 2.3.1).
2. On-chip program memory, Internal EEPROM and Flash (Section 2.3.2).
3. On-chip RAM (Section 2.3.2).
4. Interfacing capability to external program memory (Section 2.3.2).
5. Interfacing capability to external data memory (Section 2.3.2).
6. Ports (Section 2.3.3).
7. On-chip registers (Section 2.3.4).
8. Special function registers (Section 2.3.5).
9. UART (Section 2.3.6).
10. Serial synchronous (Section 2.3.7).
11. Timers/counters (Section 2.3.8).
12. Pulse width modulator (PWM) (Section 2.3.9).
13. On-chip ADC (Section 2.3.10).
14. Watchdog timer (Section 2.3.11).
15. Bitwise manipulation capability (Section 2.3.12).
16. Power-down mode (Section 2.3.13).
17. Real-time clock (Section 2.3.14).

Additional Resources

Section 2.4 will describe the additional on-chip resources in next-generation microcontrollers.

2.3.1 Basic Processing Unit, Internal Buses and Interrupt Handling

Basic processing unit: Processing unit processes the instruction. It fetches, decodes, read operands, executes and writes back the results during processing an instruction. After each fetch of the instruction, the program counter sets for the next instruction. When one instruction is completed, the processing of other instruction begins.

Each microcontroller has a basic processing unit, which is similar to the one present in a microprocessor. The processing unit has the IR (instruction register) into which an instruction is fetched at an instant. It has an ID (instruction decoder), which decodes the fetched instruction. It sends internal signals for the control and sequencing logic.

There is the ALU (arithmetic and logic unit for arithmetic and logic operations) and the PSW (processor status word). The PSW saves the flags after each ALU operation. For example, it saves carry resulting from the addition instruction. It also saves the processor status, for example, what is the status of an interrupt, enabled or disabled.

The basic processing unit has an oscillator circuit or is connected to a crystal (X-TAL) oscillator circuit through two external pins. The oscillator unit controls the generation of the sequences of control signals by the control and sequencing logic.

The basic processing unit has an internal reset circuitry and is connected to an external reset circuit through the reset pin (Section 2.3.15). The reset unit controls the starting of the processor on power-up or actions of the RESET external input.

Internal buses: Most of the subunits inside a microprocessor or microcontroller are interconnected through a common set of parallel lines called the internal bus. An internal bus carries the signals (bits) from one internal subunit to another at an instant (Figure 1.4). At that instant, one subunit is active and gets the control signal to send (write) the signals onto the bus, and another subunit is also active and gets another control signal to receive (read) the signals from the bus. A control and sequencing logic subunit (Figure 2.1) activates different units and subunits at different instants.

Example 2.1

An internal bus with 8 lines carries 8 bits (byte) from an accumulator to the port P1 at an instant, if accumulator and port P1 get the write and read control inputs from the control and sequencing logic at that instant (Figure 2.1).

Example 2.2

Figure 2.1 shows the internal bus width in 8048 as equal to 8 for data. Registers and internal RAMs need only 8-bit addresses in 8048/8051. They save and give 8-bit data. The 8051 and 8096 families also have the 8-bit data bus. A control and sequencing logic unit activates different sections and subsections at different instants; therefore, the same 8-bit bus is used internally for carrying all the data, addresses and instructions (codes).

A bus width equal to 8 is sufficient because two operands are of 8 bit each only in an 8-bit MCU’s ALU. An 8 bit MCU can add or subtract 8-bit in an instruction.

The 8048 and 8051 are 8-bit MCUs. A 16-bit operation has to be performed in two separate instruction cycles and the 32-bit operation in four cycles.

Example 2.3

MC68HC11 internal 16-bit address-bus accesses in single cycle. The 8048/8051/8096 facilitates access only in two cycles.

External buses: Many units in a system, such as microprocessor or microcontroller, RAM and flash memory and IO devices are interconnected through a common set of parallel lines called the external bus. (Figures 1.1 to 1.3). There are three sets of external buses—control bus, address bus and data bus.

The buses carry the signals (bits) from one unit to another at an instant. At that instant, one unit is active and gets the control signal to send (write) the signals onto the bus and another unit gets another control signal to receive the signals from the bus. The control and sequencing logic subunit in microprocessor or microcontroller activates different units and subunits at different instants through the external signals on the control bus using the control and sequencing logic in the processing unit.

Example 2.4

A data bus of 8 lines carries 8 bits (byte) from an accumulator in the controller to a RAM memory address at an instant, if the accumulator and RAM get the internal-read and external-write control inputs, respectively, from the control and sequencing logic.

Example 2.5

The external address bus width (A0 to A15) is 16 in 8048/8051 (through port P0 and P2 pins) as well as 68HC11 (through port PB and PC pins). Therefore, the external address space is 2¹⁶ = 64 kB in these MCUs (1 kB memory = 1024 B).

Multiplexing of the Lower Byte Bus for the Address and 8-bit Data Bus Signals

External data bus D0 to D7 multiplexes with lower address bus A0 to A7 by multiplexing in 8048/8051 as well as 68HC11. Multiplexing means that in one instant the same bus lines function as data bus. In another instant, the same bus lines function as the lower address bus. A byte of code or data can be transferred at that instant. Figure 2.5 shows the timing diagram. The time interval during which the address latch enable (ALE) is active (=1), there is the address at bus. The time intervals during which the ALE is inactive (= 0), there can be the data on the bus [ALE is called ADV (address valid) in 68 HC11].

The external data bus width (D0 to D7) is 8. Therefore, since A0 to A7 eight lines multiplex with D0 to D7, the external address space is 2¹⁶ = 64 kB. (1 kB memory conventionally means 1024 B.) The external data bus D0 to D7 multiplexes with A0 to A7 by multiplexing. Using a latch like 74LS373, the address bus signals can be latched using AD0-AD7, and the latch connects to the memory/port devices.

Example 2.6

The external data bus width can be optionally used as 8 or 16 in the 8096 series family. Either the address-bus lower-byte (A0 to A7) or address-bus lower and upper bytes (A0 to 15) multiplex with D0 to D7 or D0 to D15, respectively. The 16-bit operands are aligned in 8096. An alignment of operands means that the lower and higher bytes are at the even and next available odd addresses, respectively. [It can be viceversa in certain MCUs. It can be unaligned also in certain MCUs.]

Example 2.7

Figure 2.6 shows the buses and their widths in three series—8051, 68HC11 and 8096. ALU in the processing unit of these performs the 8, 8 and 16-bit operand operations, respectively, in a cycle. Instructions can perform operations on 1-bit, 8-bit and 16-bit operands in 8051 and 68HC11 and up to 32-bit operands in ARM and 8096. Each MCU has an internal bus of fixed width, which controls all the operations in an instruction cycle of the MCU.

Interrupt Handling

The basic processing unit has an interrupt handler subunit and connects to the external interrupt source(s) through the INTR pin. [ and pins in 8051]

2.3.2 Program and Data Memory

A memory has a large number of addresses. Each address saves 1 B (8-bits). Assume the data bus width equal to 8 bits. Then at each address, 1 B is written at an instant. From each address, 1 B is read at another instant.

When the data bus width is equal to 32 bits and 1 word = 32 bits (4 B), then at four consecutive addresses, 4 B are written at an instant. From each set of four addresses, 4 B are read at another instant.

A Memory Chip

1. Each memory chip has inputs of address bus signals.
2. Writing or reading by the controller or reading depends on which control bus-signal is active at an instant. If or is active then there is a read from the address. If control signal is active, then there is the write to the address in the memory.
3. Each memory chip has an interconnection with the data bus for reading and writing one or two or 4 B at an instant.
4. Each memory chip has a chip-select input (). The chip-select control input is from the output of an address decoder circuit. The address decoder circuit decodes the input address and is used for selecting the appropriate memory chip, which has the data at that address or where data are to be sent at that address. The address decoder is given higher bits of the address bus.
5. If the memory has n address bus inputs A₀ to A_n−1, then it has 2ⁿ bytes at 2ⁿ addresses in the address space from a starting address m to m + 2ⁿ − 1.

Memory Capacity in Bytes and Memory Addresses

Let us learn by two exemplary cases:

Case 1: If a memory chip has 12 address bus inputs A0 to A11, then it has 2¹² = 4096 B at 4096 addresses in address space from 0000 0000 0000 0000_b to 0000 1111 1111 1111_b i.e. (0000H to 0FFFH) when the chip selects in case the A12, A13, A14 and A15 are 0s.

Case 2: If memory has 12 address bus inputs A0 to A11, but the chip selects only when A12 = 0 and A13 = 1, A14 = 0 and A15 = 0, then the chip has 2¹² = 4096 B at 4096 addresses but at the address space from 0000 0010 0000 0000_b to 0010 1111 1111 1111_b, i.e. 2000H to 2FFFH.

Example 2.8

Assume at an instant the following situation:

1. Memory chip has 4 kB memory.
2. Address bus has 0010 1111 1111 0000 _b (2FF0H).
3. is active.
4. Data bus has 1000 0001 1000 0100 1000 1011 1000 0010 _b (81848B82H).
5. The decoder activates chip-select input to the memory chip when A12 = 0 and A13 = 1, A14 = 0 and A15 = 0.
   1. Will there will be writing to the memory chip or read to the memory at that instant? The answer is yes, because the input address also has A12 = 0 and A13 = 1, A14 =0 and A15 = 0.
   2. What will be the action? The action will be the write operation to the addresses 2FF0H, 2FF1H, 2FF2H and 2FF3H with bytes 82H, 8BH, 84H and 81H, respectively, if the controller writes to the memory in the word alignment mode called little endian (lower byte of a word saved or read first lower address in the memory). Alternatively, the action will be the write operation to the addresses 2FF0H, 2FF1H, 2FF2H and 2FF3H with bytes 81H, 84H, 8BH and 82H, respectively, if the controller writes to the memory in the word alignment mode called big endian endian (higher byte of a word saved or read first address in the memory). Intel microcontrollers often use the little endian mode and Motorola big endian.

Program memory:   Program memory can be on-chip and/or external in the MCU-based system. Program functions and routines in an MCU are mostly in a non-volatile read only memory (ROM). The program memory stores the read-only codes, constant input data and parameters of the programs. There is a separate address space for the program memory starting from the 0000H address in Harvard memory architecture in an MCU. Example 2.9 gives the exemplary contents in the program memory in a system. [Non-volatile means do not change on switching off of power.]

Example 2.9

Table 2.2 gives the exemplary contents at the program memory in the MCU-based systems

 

Table 2.2 Exemplary Contents in the Program Memory in a System

Memory	Exemplary contents	Preferred type of memory
Program memorya	Program functions, routines, boot-up program and interrupt service routines for the system after the development phase is over. Standard macros and functions for program building block functions; for example, for preset delay, for UART communication at the pre-select baud rates; needed library functions, for example for finding maximum, minimum, average and standard deviation values of a set of values, for sorting the set of values in descending or ascending order.	External or internal EPROM or Flash at laboratory test stages and on-chip masked ROM at the mass production stage.
	Permanent constants for the bytes for displaying the pictogram for the companies, emblem on LCD display; constants for maximum and minimum limits; for example, channels 0 to 99 in a TV remote control, number of maximum acceptable digits in the phone number when dialing.	Internal EPROM or Flash at laboratory test stages or masked ROM at the mass production stage.b
	Strings for the product version, welcome messages at the start of the system, messages for system-status display, operational menus for selection (like in press 1 for measuring voltage, 2 for current, 3 for resistance and 4 for frequency in an MCU-based multimeter test equipment), name and contact addresses of the manufacturer.	Internal EPROM or Flash at laboratory test stages or masked ROM at the mass production stage.b
	Modifiable and intermediate non-volatile data for the current values or results for the validity date of an account, password, and user ID and present balance in the account, data and time of last transaction, calibration constants of a sensor element or telephone numbers in a phone or contact numbers and addresses.	Internal EEPROM or Flash.b

EPROM

ROM can be in the form of EPROM during a laboratory testing phase. For example, 8751 series member has the on-chip EPROM. The EPROM can be erased by exposing the chip to the UV light. EPROM chip has a quartz window, which is transparent to the UV All the bytes at all addresses can be erased in an erasing cycle of UV exposure.

Example 2.10

Philips P87C528 has EPROM version with 32 kB program memories (internal) 512 B internal RAM, no ADC, out-compare and capture circuits associated with the timer T2 and I²C Bus.

2.3.2.1 On-chip Internal Flash and EEPROM

Flash Memory: Flash EEPROM (electrically erasable and electrically programmable ROM) is also referred to simply as flash. Flash can be erased by electrical signals.

Usually, an EEPROM erases 1 B at an instant. Flash EEPROM is when a sector consisting of many bytes (say, 1024 B or 2048 B or 4096 B) can be erased. All bits are made 1s by placing all floating gates of a sector together in place of each independently in EEPROM. However, sometimes flash is used for EEPROM that has the capacity to erase one or a few in a row byte in an instant.

Flash memory advantage is that it gives reprogramming feature in the MCU. Program codes can be repeatedly changed in flash memory when required and the changes are non-volatile. Another advantage is that a complete sector of memory addresses is erased and all bytes at that sector become 1111 1111b (FFH) in one cycle. A sector may be of the system 1 kB or 2 kB or 4 kB).

The contact details in a mobile phone are saved in the flash. These details can be changed when required.

A variant of flash is a boot mat flash. A sector (block) in boot mat flash is OTP (one time programmable). Boot-up program is one that runs on start up. Hence, the OTP sector of flash can be used in place of the ROM or EEPROM for the boot up of the system.

There is great technological advancement in flash designs like zero wait state 50 MHz. Nowadays, an 8 GB flash in a chip is available which can be inserted in a system. It is used in digital camera. A flash variant is a boot mat flash. 32 GB is going to be reality in near future.

Example 2.11

8951 series MCU has the flash. AT89xx is flesh memory based MCU. AT89C55WD has 32 kB flash internal program memory. AT89C51RC and 33AC have flash memory of 32K × 8, RAM 512×8 and 33MHz clock. 32K×8 means 32×1024 addresses and 8-bit at each address.

EEPROM: Figure 2.7 shows the types of EEPROMs. The read-cycle time of EEPROM or flash byte is the same as that in a RAM. An erase and write cycle time is high compared to read in 68HC11.

The 68HC11 has some interesting features. These are as follows:

EEPROM can be erased by electrical signals. EEPROM memory advantage is that the byte can erase and then be written again and the change is non-volatile. The changes can thus be made at the run time. Bytes can be repeatedly changed in EEPROM memory when required. Another advantage is that 1 or 2 or 4 or 16 or 64 memory addresses are erased in one cycle. Certain constants, for example, calibration constants of a sensor element can be in the EEPROM (electrically erasable and electrically programmable ROMs) (Table 2.2). These can be modified later. EEPROM bytes can be set online during execution of a program or by using the device programmer. The advantage of EEPROM is that it can be erased byte by byte before writing and can be used for non-volatile constants or intermediate status or result or the final result of a program.

EEPROMs are of the following types:

1. Erase 1 B in a cycle when modifying a variable online.
2. Erase all addresses in a cycle.
3. Erase 16 B row of addresses in a cycle.

Example 2.12

MC68HC711L6 has 512 B RAM, 512 B EEPROM and 16kx8 EPROM as the on-chip memory. An erase and write cycle is 10 ms in 68HC11. The read cycle time of EEPROM or the flash byte is the same as that in a RAM. On-chip EEPROM can be used in three modes (each in one single cycle’s erase time) as per the mode bit in the configuration register.

Storing the Bytes for the Codes in the EPROM, EEPROM or Flash Memory

Device means the MCU (with on-chip memory) or EPROM chip or flash memory or CPLD. A laboratory device programming tool is used in case an MCU has the on-chip EPROM or flash, EPROM chip, flash, EEPROM or programming logic.

The programming tool consists of the hardware and software. The hardware has a socket for placing the erased EPROM or MCU on-chip PROM. The socket can also hold flash. The software takes a file for the codes as the input. When it runs, it burns the codes and constants into the MCU. Burning is the process to write and install the bytes at the predefined addresses as per the program(s) and its constants (Table 2.2).

Storing the Bytes for the Codes in the ROM

A ROM is in the form of masked ROM after the finally tested and approved phase. The 8351 series members have the ROM area in 8051 MCU. A ROM is factory programmed by first setting a mask. The mask sets 1s and 0s at the predefined addresses as per the program(s) and its constants. The ROM chip or ROM area in MCU has an unetched metal layer, which is etched as per the mask to get 1s and 0s as per the ROM image needed to be burned in the ROM in place of all 1s before the treatment at the manufacturer’s site. For mass production of the systems, ROM is the best alternative, and cost decreases with increase in the requirements. [ROM image means the bit pattern fixed for each ROM address.]

Data Memory: Data variables and stacks in an MCU are mostly in a volatile read and write memory (RAM) or registers. There is a separate address space for data memory starting from 0000H address when there is Harvard memory architecture in an MCU. Example 2.13 gives the exemplary contents in the data memory in a system.

Example 2.13

Table 2.3 gives the exemplary contents at the data memory. (Note that Table 2.2 referred to constants and strings not in internal on-chip program memory space that can also be at the data memory space.)

 

Table 2.3 Exemplary Contents at the Data Memory

Memory	Exemplary Contents	Preferred Type of Memory
Data memory	Direct or indirect or both addressable bytes for the variables, pointers, look-up table, limited size array and individually addressable bits.	On-chip RAM
	Stack of program counters and saved variables.
	Device (includes port) control parameters and status parameters and the device/port individually addressable bits.	On-chip registers (special function registers in 8051 families) if available, else on-chip RAM
	Extended direct or indirectly addressable (or both; it depends on the MCU family) data for example, for the online large buffer, queues, pipes (for example printing and fax), file-data or network stream.	External RAM

MCUs mostly have on-chip program memory in the ROM or EPROM or flash and data memory in internal RAM and registers.

2.3.2.2 On-chip Internal RAM

MCU has the internal RAM. The RAM is 64 B in 8048 and 128 B in 8049 and 8051. The RAM is 256 B in 8052.

Example 2.14

8051 family MCU has internal RAM between addresses 00H and 7FH. The internal RAM byte between these addresses can be directly addressed and can also be indirectly addressed.

8052 family MCU has internal RAM between addresses 00H and FFH. The internal RAM byte between the addresses 00H and 7FH can be directly addressed and can also be indirectly addressed. The internal RAM byte between the addresses 80H and FFH can only be indirectly addressed.

2.3.3 Parallel Ports

At a port in a shipyard, the ships are placed and sent. Similarly, at a port the bits are latched (placed) and sent to the processor or external device or circuit. When the bits are sent (placed) from an external circuit, the port is called the input port. When the bits are (placed) for an external circuit by the processor, the port is called the output port.

An input port has a set of pins using which the bits are placed by an external device or circuit and from where the bits are taken into a register or memory address using an instruction. An output port has a set of pins where bits are sent for the output using an instruction. An IO port is bidirectional input cum output and functions both ways.

There are two types of ports—parallel and serial. A parallel 8-bit port means all the 8 bits can be placed at all its pins simultaneously. A serial port means all the 8 bits of a byte or character can be placed at its pin in 8 time slots. The time interval AT for each slot is the same and depends on a preset bit-rate. For example, if the bit rate is 1 Mbps then each bit is sent or received in 1 μs time interval. If the rate is 9,600 then each bit is sent or received in (1/9,600) s. Sections 2.3.6 and 2.3.7 will describe the details of serial communication.

Figure 2.8 shows the different port-types. A microcontroller in a single-chip mode provides several ports at the chip itself. An MCU parallel port is of 8 bits. Sometimes the number of port bits becomes less. This is during the alternate use of certain pins. The number of port pins at the chip reduces when using the expanded mode (external chips) (Table 2.1).

Memory-mapped IO Operations

Instructions which operate using memory address are also used as the IO instruction and the control signals to I/O and memory devices are thus also the same. MCUs have memory-mapped I/O devices.

I/O devices on the chip share the same address space as the internal memory, and external I/O devices share the same address space as that with the external data memory. Hence, an MCU can interface with a large number of ports (theoretically as many as the address space permits). Telephone switching exchange is an example where there is need for a large number of ports.

Expansion to Several Number of Ports from a Few Ports in the MCUs

Multiplexing and de-multiplexing circuits also provide the expansion to more number of ports.

Port with a data direction register for programmability of each pin as in or out:

Usually, a port function either an I/O port or input port or output port and all the bits are used either as input or output at an instant. However, if an 8-bit port has a data direction register (DDR) of 8 bits, then each bit of the port can be programmed to function distinctly by specifying it as the input or output. The port pin direction is programmed by a reset or set of the corresponding bit at the DDR (Fig. 2.8.(c)). The 68HC11 family provides these features in a few ports. If DDR.0 and DDR.1 register bits are programmed as 0s and all other six bits of DDR are programmed as 1s using an instruction in 68HC11, then port pins 0 and 1 are programmed as input pins and the remaining port pins 2 to 7 are programmed as the output.

Example 2.15 gives the IO port pins in 8048/8051.

Example 2.15

Ports P0 and P2: There are two ports in 8048 and also in 8051—P0 and P2. P0 port has 8 pins—P0.7, P0.6, …, P0.1 and P0.0. P2 port has 8 pins—P2.7, P2.6, …, P2.1 and P2.0.

P0 pins P0.7 to P0.0 when accessing a program or a data external memory chip carries 8 signals at the pins as AD7, AD6, …, AD1 and AD0. It carries address signals—A7, A6, …, A1 and A0 when ALE (Address Latch Enable) pin signal = 1 (Active) else D7, D6, ., D1 and D0. ALE is given to a latch to latch the address bits for the memory.

P2 pins P2.7 to P2.0 when accessing a program or a data external memory chip carry the 8 address signals—A15, A14, …, A9 and A8.

Port P1: There is port P1 in 8048 and also in 8051. P1 port has 8 pins—P1.7, P1.6, …, P1.1 and P1.0.

Port P3: There is port P3 in 8051. P3 port has 8 pins—P1.7, P1.6, …, P1.1 and P1.0 in a single chip mode.

There are alternate uses of Port P3 pins. They are used for the following:

• Serial communication
• Interrupt signals
• Timer/counter control inputs
• Control bus WR and RD signals

Example 2.16

Table 2.4 gives the examples of various types of the ports.

 

Table 2.4 Port Types in the MCU-based Systems

Port type	Example
8-bit port with latch for input or output or IO operations (Fig. 2.8(a))	Port P1 in 8048 and in 8051 classic family members
8-bit port with latch as well as bus buffer for address, data, and control buses (Fig. 2.8(b))	(i) Port P0 and P2 in 8048 and in 8051 family members. The P0 is also usable as AD0-AD7 and P2 as A8-A15 bus. (ii) HC11 Port PB output port as well as A8-A15 bus. (iii) The HC11 Port PC for the I/O with handshaking mode also usable as AD0-AD7 in the expanded mode. 8096 Ports P3 is usable as AD0-AD7; and 8096 Port P4 as the A8–A15 bus (option 1) and as AD0-AD7 and AD8-AD15 bus (option 2). 8051 Port P3 and 8096 port P2 provide UART and other control bus signals in the expanded mode
8-bit port with data direction register (Fig. 2.8(c))	68HC11 Ports C and D
8-bit input port with analog inputs capability (Fig 2.8(d))	68HC11 Port E (4-bits in certain versions) also function as analog inputs for multi-channel ADC; Port P0 in 8096 also functions as analog inputs.
8-bit port with handshaking signals (Fig. 2.8(e))	68HC11 Port C is also usable in conjunction with the handshaking signals
Open-drain port	An open drain (OD) port needs external active (MOSFET or BJT transistor) or passive (resistive) pull up to output logic 1
Quasi bidirectional port	An open drain (OD) port needs external pull up to output a logic 1, however, a quasi bidirectional port provides for 1 LSTTL gate-driving capability for few clock cycles so that in case of the use of the LSTTL latches, for example for interfacing the external memory chips, the external pull circuit is not needed

General notes and instructions for using the parallel ports are as follows:

1. One handshaking signal for strobe request from an input from a device. Alternatively it is used as acknowledgement from the device receiving port output. The other handshaking signal is the port-acknowledgement to the device. Alternatively it is used for port ready signal for the sending. It can also be used as device port buffer full signal to the device. [Buffer full means that port has data.]
2. If an OD port is to be used for the input, then the 1(s) must be written first and then the port is usable as input. First step brings output stage transistor which is at the gate output to a non-conducting state. The previous state may be a conducting state when 0 was previously sent to the output.

Important point to note is that an MCU has a few parallel ports usually, 8 bits each. Port bits are also put to the alternate uses. The external buses to the interfacing chips are also required. The port pins are also used for that.

2.3.4 On-chip Registers

An MCU has several on-chip registers. Registers are needed in the register addressing instructions and for the operands in the arithmetic and logic operations. Advantage of the registers is that a register can be addressed in an instruction by a few bits. For example, assume that there are 8-registers. Then bits 000 specify register R0, 001 specify R1, … and 111 R7. Therefore the add instruction code ADD R1, R2 needs only 6-bits for the operands R1 and R2. When 2 bits are required for add operation code, the instruction length is just 8-bit.

Example 2.17

8051 has 32 on-chip registers. These are partitioned into four sets of register banks. There are two bits called resister-set select bits in PSW called RS0 and RS1.

• If RS1-RS0 are set as 11, then bank 3 is accessed in the instruction using the register addressing mode.
• If RS1-RS0 are set as 10, then bank 2 is accessed in the instruction using the register addressing mode.
• If RS1-RS0 are set as 01, then bank 1 is accessed in the instruction using the register addressing mode.
• If RS1-RS0 are set as 00, then bank 0 is accessed in the instruction using the register addressing mode.

Assume RS1-RS0 = 10 and instruction MOV A, R4 executes. Then after executing this instruction the A gets the byte from bank 2’s register R4. Instruction will also have only 8 bits, 5 bits to specify opcode for MOV and operand A. A and 3 bits 100 to specify operand R4.

2.3.5 Special Function Registers

An MCU can have several registers, which are used for special functions. 8051 has registers for special functions. These registers are called SFRs (special function registers). The SFRs are used for following purposes in 8051:

• Accumulator
• B register
• PSW
• Timer control register
• Timer mode register
• T0 Timer counts register
• T1 Timer counts register
• Port
• Serial buffer
• Serial control
• Interrupt enable
• Interrupt priority
• Power control
• Stack pointer
• Data pointer (DPTR) lower byte
• Data pointer (DPTR) upper byte

A special function register can be used for other purposes also. This depends on the MCU:

Example 2.18

8051 has four special function registers (SFRs) called P0, P1, P2 and P3. These are used both as the output and input ports. Instruction MOVP1, R1 will output the byte at R1 to parallel port P1. Instruction MOVR1, P1 will receive the byte at P1 and place it at R1. The R1 will be of the register bank, which RS1-RS0 specifies.

Example 2.19

When a byte is transmitted as a serial data output, a transmit buffer is required. From the buffer, all the 8 bits of a byte or character can be placed at a pin in 8 or 10 or 11 time slots. It will depend on the serial communication mode for transmission. When a byte is received as serial data input, a receive buffer is required. At the buffer, all the 8-bits of a byte or character can be received at a pin in 8 or 10 or 11 timeslots. It will depend on the serial communication mode for reception.

8051 has a special function register (SFR) called SBUF. It is used both as a transmit-serial-buffer and receive-serial-buffer. Instruction MOV SBUF, A will transmit the byte at A serially using SBUF. Instruction MOV A, SBUF will receive the byte serially using SBUF and place it at A.

2.3.6 UART

The serial-line device is present in most MCUs, because the serial port is needed to communicate with many external and remote devices. In serial communication, a stream of 1s and 0s is sent or received at successive time intervals of ΔT on a single line called the serial line. There is a transmit buffer, which is present with the byte for serial transmission. There is a receive buffer, which receives the byte during serial reception.

Example 2.20

8051 has a special function register (SFR) called SBUF. It is used both as a transmit-serial-buffer and receive-serial buffer.

An internal transmit clock is used during transmission, and internal receiver clock is used during the reception of the bits. The internal clock generates pulses of 1s and 0s. There is a fixed time interval, which is kept between successive logic 1s and 0s. The time interval ΔT between successive 1s or 0s depends on the decided bit rate for serial communication between the transmitter and receiver. The reciprocal of this time interval ΔT is the bit rate of the serial communication.

UART: (Universal Asynchronous Receiver and Transmission) is a very popular mode of serial communication. The transmission and reception in UART mode is asynchronous. The successive bytes are sent and received at the serial line such that there may be variable time gap between the bytes. Also the transmitter and receiver clocks must be of the same rate but they are independent (need not be in same phase or in synchronisation). Such transmission is also called asynchronous serial communication.

Example 2.21

Figure 2.9(a) shows the UART communication format for 8-bits 10010001.

This mode communication is as follows:

1. This mode defines that there should be 1 on the serial line when the line is not in use (idle).
2. Action during the first period ΔT: Before the transmission of the byte from the transmit buffer, there should be a start bit. It means for a period ΔT equal to time interval fixed for the serial bits transmission, there should by 0. When the receiver finds that there is 1 to 0 transition followed by 0 for that interval, it assumes that start bit has been received.
3. Action during the next eight periods 8 ×ΔT: The byte from the transmit buffer is then sent on the serial line at successive time intervals.
4. The receiver looks at the line state 1 or 0 at the successive time intervals from the middle point of the start bit interval and detects 1s or 0 s, eight times to detect the byte sent on the serial line. The receiver thus gets the byte in time 8 ×ΔT.
5. Action option during next period ΔT: There may be an additional bit after that for the period ΔT. That bit is called TB8 in 8051 serial UART transmission. That bit is called RB8 in 8051 serial UART reception.
6. Action during the last period ΔT: There must be a stop bit for the period ΔT or more at the end of the transmitted byte or transmitted additional bit. The receiver must detect stop bit by the presence of 1 at the serial line for at least one time interval ΔT.
7. The reciprocal of time interval ΔT between successive bits on the serial line is called Baud rate in place of bit rate. Baud is a German word for the drop. The bits are said to be pour in at the receiver just like rain drops. This is the logic for using the word drop. Between successive bytes sent and received at the serial line there may be variable time gap. Such transmission is also called asynchronous serial communication.
8. The total period for sending the byte on the serial line = 10 × ΔT when an additional bit is not sent and = 11 × ΔT when an additional bit is sent after the byte’s serial transmission from the buffer.

The additional bit in 11T format is a bit next to the 8 data bits and before the stop bit. It is useful as follows:

1. Inter-processor asynchronous communication between the systems,
2. Error checking—It can also be used as a parity bit to reflect odd or even to find whether a bit among 8 is corrupted due to line noise (line noise when present can make bit 1 interpreted as 0 or 0 as 1).
3. A bit to indicate the meaning of the preceding 8 bits as an address or data.
4. Bit to specify that the preceding 8 bits are for instruction or data.
5. Bit to specify that the preceding 8 bits are for control-command or data.

8051 has a special function register (SFR) called SBUF. It is used both as a transmit-serial-buffer and receiver. 8051 and many MCUs have an UART device in two formats, 10T and 11T, with a programmable baud rate for the asynchronous serial communication. Modes 1, 2 and 3 of serial interface in 8051 are for asynchronous serial UART communication. Section 3.6.2 will describe it in detail. There may be two UART devices also in an MCU.

2.3.7 Synchronous Serial Communication

MCUs can possess a synchronous serial line. It also accompanies a synchronizing clock. This facilitates external and remote inter-processor transfer of bytes at a faster rate. Figure 2.9 (b) shows an exemplary format during synchronous serial communication.

1. Serial synchronous communication means each byte (or frame of bits) on the serial line needs to maintain the same phase differences between them.
2. The transmitter does communicate explicitly or implicitly clock bits—1s and 0s (Figure 2.9(b)) to the receiver. This synchronizes the receiver clock, which is made to work in the same phase. The explicitly means that the serial and clock bits are sent on two separate lines to the receiver. The implicitly means that the clock and data bits are combined in such a manner that the receiver can separate serial and clock bits back.
3. The transmitter buffer sends a byte to parallel in serial out (PISO) shift register to send different bits in the output at each clock pulse.
4. The receiver buffer receives a byte from serial in parallel out (SIPO) shift register to receive different bits in the output at each clock pulse.
5. The transmitter can also be called a master. The receiver can also be called a slave. Serial output line can be called the MOSI (master out serial in) line. MOSI is used by the master to send the command or data to the slave. Serial input line can be called MISO (master in serial out) line. MISO is used by the slave to send the acknowledgement or response. Master is the one which controls the clock during reception or transmission.
6. Each bit is for the period T at the serial line, which is the reciprocal of a rate called the bit rate. The rate is usually expressed in kbps (kilo bit per s) or Mbps (mega bit per s) unit.

Example 2.22

The mode 0 of communication is as follows in 8051:

1. Action during the eight periods 8 × ΔT: The byte from the transmit buffer is then sent on the serial line at the successive time intervals.
2. The receiver looks at the line state 1 or 0 at the successive time intervals from the negative edge of the clock eight times to detect the byte sent on the serial line. The receiver thus gets the byte in time 8 × ΔT.
3. The reciprocal of time interval AT between successive bits on the serial line is called the bit rate. Total period for sending the byte on the serial line from the buffer = 8 × ΔT.

Example 2.23

Mode 0 of serial interface in 8051 is synchronous serial. 8051 has a pair of pins for its serial interface (SI). These pins are used as Serial data out and serial clock at the master (transmitting) system. These pins are used as Serial data in and serial clock in at the slave (receiver) system. Section 3.6.1 will describe it in detail.

2.3.8 Timers/Counters

Timers are a must for real-time operations in any system (Chapter 6). Figure 2.10 shows the important - modes of functioning in timers.

1. A 16-bit timer/counter means it can count from 0000000000000000b to 11111111111111b (0000H to FFFFH). An internal clock is used in the timer mode. The internal clock pulses increment the counter. An internal clock pulse may be connected after pre-scaling. Pre-scaling divides the clock rate by a certain factor; for example, 2 or 4 or 8 or 16 or 32 or 64. When used in the counter mode, the external events are used to give the input to the counter for its increment.
2. A timer counts the equal-interval clock-pulses from an oscillator circuit. The pulses are used after a suitable fixed or programmable pre-scaling (division) factor.

Figure 2.10(a) shows a timer with internal clock and pre-scalar. The function of this timer mode can be understood by the following example.

Example 2.24

8051 family MCU has two programmable timers, T0 and T1. The 8052 variants of the family have an additional timer T2.

Example 2.25

Assume that a microcontroller timer has pulses from internal clock as input and the pulses time interval between successive 1 or 0s = ΔT. Assume ΔT_clock = 1 μs. There is an 8-bit timer register TL0. When Timer TL0 runs then it can increment up to 1111 1111b and then on the next input pulse, the TL0 will become 0000 0000b0. It means that TL0 will overflow. An overflow indicates timeout. It generates an internal interrupt. It can be called the TL0 interrupt.

Assume TL0 is loaded with a value = 64d = 40H = 0100 0000b. When TL0 runs, it gets internal clock pulses after every ΔT_clock = 1 μs (when the pre-scaling factor p=1). The TL0 when runs will reach the overflow state after (256 − 64) μs = 192 μs.

When the pre-scaling factor is 32, TL0 gets input after every 32 × ΔT_clock = 32 μs (when the prescaling factor p = 1). The TL0 when runs will reach the overflow state after (256 − 64) × 32 μs = 192 × 32 μs = 6.144 ms.

If TL0 is preloaded with value = 0d, then it will overflow after every (256 − 0) × 32 μs = 256 × 32 = 8.192 ms.

Example 2.26

Assume that a microcontroller timer/counter in place of internal clock pulses is given input from a circuit sending pulses on every 2 degree rotation of a wheel. There is an 8-bit timer register TL0.

Assume it is reset to value = 00d = 00H = 0000 0000b before the beginning of the rotation. The TL0 is then set to run. It gets pulses after every 2 degree rotation. It counts up to a maximum of 256 counts and after 255 counts, when counts = 256, the counter overflows and causes an interrupt.

If TL0 is preloaded with value = 40d, then it will overflow after every (256 − 64) = 192 counts:

A timer can be used in different modes (Figure 2.10(b)).

1. Free-running counter. When a timer/counter mode runs in a no stop, no reset, pre-load disabled state (Figure 2.10 (b)) and auto-run after each overflow, it functions as a free-running counter. It gets input from the internal clock pulses after pre-scaling.
2. Free-running counter, therefore, is also used as a continous recorder of an actual time (real time). For example, we capture the count c0 at the start of the swimming and recapture the count c1 at the end of swimming. The difference (c1 − c0) multiplied by the period between each input to the counter gives the time clocked by the swimmer.
3. Similarly, a timer in non-stop, reset and pre-load disabled state can be used for capturing the times at the different input instances. The timer saves the current timer value into an input capture register for use as a time recorder for an instance of occurrence. One can find the interval between the two events (Figure 2.10 (c)) of the input capture.
4. Just as the clock’s alarm rings on reaching the preset time, a timer in non-stop, reset and pre-load-disabled state can be used for comparing the different predefined instances. At those instances there are programmed outputs (1s or 0s or toggled). Each successful comparison also causes an interrupt. A time instance for the programmed output can be preset (as in an alarm) in a register called the out-compare register. [Figure 2.10(d)]
5. A use of the timer in another mode (Figure 2.10(e)) is a real-time clock. It is described in Section 2.3.14. It gives the repeated interrupts in order to initiate the events at regular intervals.

Example 2.27

8096 family MCU has two programmable timers, T1 and T2. T1 facilitates the high-speed input unit. 8096 captures the time instances into a FIFO and records up to eight events in quick succession. 8096 also facilitates the high-speed outputs (HSO). The HSO unit is loaded with the preset instances of the timer. The unit compares the time instances with the preset time instances and initiates the HSO actions. The HSO unit compares up to 16 instances in quick succession.

Example 2.28

68HC11/12 family has main timer, which is a free-running counter (FRC). The FRC timer is used for the input captures, real-time clock and out compare modes described above. Motorola family MCUs has a powerful unit for real-time processing. It is called a timer processing unit (TPU). The 68HC16 TPU consists of a microprogrammed control unit, control memory and a library of more than 20 different timing functions. This facilitates the fast real-time controls. This is because of the separate instruction processing unit which is used in processing the capture operations and compare operations with the timers.

2.3.9 PWM

An MCU version may have one or more pulse width modulated outputs (PWMs). PWM output is one in which the width percentage is proportional to the value loaded in a special function register which loads the modulation parameter p. Assume T is time interval between two successive clock inputs used for generating the PWM output. Figure 2.11(a) shows the continuous pulses at the PWM output.

The pulse width percentage is (100)(256–p)/256, where p is the modulation parameter in an 8-bit pulsecontrol register PCNT. When p = 0 the width = 100% and when p = 255, the width = 1%. If there are six PWM outputs provided in the MCU, then there will be six pulse control registers PCNT0, …, PCNT5.

Example 2.29

Assume that an 8-bit timer/counter is accumulating counts up to 2⁸ (=256) using an internal clock of time-period T = 1 μs in an MCU continuously. There is continuous comparison of these counts with p. There is an internal circuit such that on overflow of counts the PWM pin becomes 0 and when counts becomes equal to p, then the output at PWM pin = 1.

The output is 0 for the duration p × 1 μs and 1 for the duration (256 − p) ×1 μs. Total pulse time-period of the pulses at PWM pin = 256 μs. Since the counts are being accumulated continuously, there will be continuous pulses of duration proportional to (256 – p).

On-Chip D/A (DAC) Using PWM

DAC stands for digital-to-analog conversion such that the analog current or voltage output relates linearly to the digital value (input). The PWM device with PWM control register, can be used as the DAC by installing an appropriate integrator that interfaces with the MCU.

Analog output is obtained when the PWM output is integrated by an integrator amplifier. The amplifier output has a linear relationship with the bits used for the modulation parameter p, which is programmed using an instruction of the MCU. An MCU stores p in the special register PCNT for the PWM function. When PWM output is input to an integrator amplifier, the p relates linearly to the analog voltage. Figure 2.11(b) shows analog outputs in two cases as a function of pulse width percentage and pulse controls register parameter.

PWM is used to obtain the digital-to-analog conversion (DAC) operation as follows. The DAC operation is needed in many control-related operations. For example, DC motor control and heater current controls.

Case 1: It is assumed that the integrator-1 design is such that the output v is maximum when p = 255 and is 0 when p = 0.

Case 2: It is assumed that the integrator-2 design is such that the output v is maximum when p = 255 and is − v when p = 0.

Circuit for PWM

(i) Continuously running timer with pre-load disable and stop disabled, (ii) PWM register and (iii) a comparator is present in the PWM circuit in the MCU. Figure 2.11(c) shows the circuit for the PWM application of the MCU. It uses a pulse count and control register for the pulse width modulation. This is assuming that there is an 8-bit internal PWM output control register, PWM_CONTROL. Software can write p at its address in the MCU. Let a counter run in a free-running mode and the count value be c at an instant. A PWM output will be obtained by an operation in which at the port bit or PWM output pin the output is 1 when c > = p, and 0 when c < p.

2.3.10 On-Chip A/D Converters (ADC)

Many times, a microcontroller has an on-chip A/D (called ADC also) conversion feature. This is an important feature in the control applications. Figure 2.12 shows an MCU with an on-chip ADC. The ADC starts conversion on each negative going pulse.

The ADC does successive conversions on successive start of conversion pulses. An ADC may have programmable options for reference V

The ADC functioning can be explained by the following example.

Example 2.30

Assume a 10-bit ADC in an MCU. There are 1024 (= 2¹⁰) values between 0000000000 and 111111111. Assume positive reference Voltage = 5 V and negative reference voltage = 0 V.

1. When input is 0 V, the ADC register will have bits 0000 0000 00 = 0d after the conversion time is over. Resolution of ADC = 5 V/1024 = 0.0048828125 V.
2. When input is 5 V, the ADC register will have bits 1111 1111 11 = 1023d after the conversion time is over. This is because 0.0048828125 × 1023 = 5 V.
3. When input is 2.5 V, the ADC register will have bits 1000 0000 00 = 512d. This is because 0. 0048828125 × 512 = 2.5 V.
4. When input is 1.25 V, the ADC register will have bits 0100 0000 00 = 256d after the conversion time is over. This is because 0.0048828125 × 256 = 1.25 V.
5. When input is 0.625 V, the ADC register will have bits 0010 0000 00 = 128d after the conversion time is over, because 0.6125 V = This is because 0.0048828125 × 128 = 0.625 V.

ADC Applications

The ADC operation is needed in many control-related operations. It is needed when are reading the analog voltage from a sensor or transducer or analog input in the instrument for measuring the following: ECG waveform or temperature or pressure or position of a moving shaft by an LVDT (linear voltage differential transducer) or relative humidity or weight using a load cell or DC motor speed control speed or heater temperature current control.

Sample/Hold Amplifier in the ADC Circuit

Consider a case in which a microcontroller has an ADC device. The ADC is fed a certain signal (input analog voltage) v through an amplifier. The amplifier is called S/ (sample and hold) amplifier. The amplifier first samples the signal for a certain period (~ 1 μs) and then holds it for the required time. Sampling the signal outputs the average v after a certain period. The S/ amplifier holds v unchanged during the conversion period. The amplifier has a control signal. S/ control input = 1 when sampling and 0 when holding.

S/ amplifier thus gives the value close to the true value. This is because the random noises in the sampling period get canceled during averaging. S/ amplifier analog output is converted on a start of conversion signal.

ADC Circuit Output

The digital bits after the conversion map to the signal ratio [v / (V⁺_ref − V⁻_ref)], the converted bits can be latched at a port in the MCU or used for control applications. Here, V⁺_ref and V⁻_ref are the reference analog inputs to the ADC, set such that when v = V⁺_ref with all output bits equal to 1 and v = V⁺_ref with all output bits equal to 0. Mapping means the output bits b₀, b₁, …, b_n−1 are such that the decimal values of these are proportional to the signal ratio. These ADC device bits b₀, b₁, …, b_n−1 are stored in a register. A program can make it available the port for use by the external circuit. The circuit generates at constant programmed intervals, these bits may be updated.

2.3.11 Watchdog Timer (WDT)

The watchdog timer is a timing device that resets the system after a pre-defined timeout. WDT resets and then the further processing is (i ) either from the same address as at the beginning on the power-up (for example, in 8051) or (ii) as per the bytes at a vector address in certain MCU timeouts of the WDT (for example, in 68HC11). Most microcontroller variants of an MCU family have on-chip watchdog timer.

WDT Application

WDT has many applications. It rescues the system if a fault develops in between. An example is when a program hangs due to an interfaced circuit fault. Another example is a loop not finishing in a control program due to an exceptional condition. WDT comes to the rescue in such situation by resetting the program. On restarting, the system is expected to function normally.

Watchdog Timer Circuit

Figure 2.13 shows the working of a non-stop timer/counter used as a watchdog timer. The watchdog timer is usually programmable for the timeout period. Program counter loads on WDT timeout a value equal to one that was on power-up or that which loads on reset of the processor.

2.3.12 Bit-Wise Manipulation Capability

Figure 2.14 shows the various bit transfer or manipulation instructions. The 8051 family MCU has a powerful bit manipulation capability and has a bit manipulation capability with the carry bit (flag) playing the role of an accumulator of one bit. The C flag can be set or reset. A port bit can be set, reset, complemented, transferred or logically operated. The bit can perform these operations in bit-address space of the 8051.

2.3.13 Power-Down Mode

An MCU-based system may be designed such that it need not be switched off at any time. In this case the processor runs in the power-down mode. The MCU initiates certain actions on execution of the WAIT and STOP instructions. The stop state can also occur when clock inputs to a processor stop ticking or the program has been designed such that it shuts down the processor automatically. During the stop state the MCU disconnects external devices, and the internal clock circuit is deactivated. The battery-backed RAM activates and protects the protected area. When there is an external interrupt or reset, the MCU reactivates and forgoes the stop state.

An execution of STOP instruction can be enabled or disabled by a bit in a configuration set register in certain MCUs.

Example 2.31

The 8051 MCU provides a power-down mode bit for serial communication. The bit-transfer rate can be slowed by half, so that power is saved during communication from the MCU.

2.3.14 Real-Time Clock

An MCU is said to have a real-time clock device if it can make or have one of the timer non-stop and no reset and load-disabled state and the interrupts from this timer, once enabled, are not disabled later. The timer overflow interrupts now act like a clock that ticks at regular intervals. Timer overflow means transition from all its 1s to all 0s output state. If the timer does not stop, it repeatedly interrupts at constant intervals and it gets inputs from an internal clock continuously after appropriate scaling by a certain factor. Scaling here means division by a factor, say, 2, 4, 16 or 64. The word, real time is used because time never stops and cannot be reset. Figure 2.15 shows the actions of a real-time clock device.

Real-time clock is an important resource in a microcontroller because using this an OS sets the system clock, schedules the tasks and time-delay functions. It is an on-chip device made from the timer working in non-reset, non-loadable and non-stop mode. The interrupts from this timer are the realtime clock ticks, which also update the time information at certain memory address.

Example 2.32

Assume that there is a 16-bit time running non-stop and no reset and load-disabled state. Assume a clock input after every 1 μs. When pre-scaling factor = 32 the timer gets input every 32 μs. It will timeout after every 32 × 2¹⁶ = 2.097152 s. Real-time clock interrupts (ticks) occur every 2.097152 s.

2.3.15 Reset Circuit

Certain processors start like 8051MCU processing from 0x0000 (0xFFFF0 in 80x86). The start address on reset is programmable in certain MCUs. Certain processors start from an address as per the bytes programmed earlier at a fixed memory location. A reset circuit or device resets the microcontroller so that a processor starts smoothly. This means that the processing of instructions from a starting address is prevented during the intermediate voltages to the MCU. All the processor registers and devices and interfaced devices get the default values. Reset circuit when activated forces a processor to start the processing of instructions from a starting address smoothly, which means without glitches—sharp variations between low voltage and needed voltage.

Reset input activates just for a few clock cycles. Value of V at reset pin becomes identical to one expected after a +5V powerup or after external reset circuit input after these cycles. The reset pin V connects to other peripheral devices. This enables their reset also.

Example 2.34

68HC11/12 starts processing from the address defined by the bytes programmed at 0xFFFE (called vector address for the reset). The MCUs 68HC11 and HC12 have two start-up addresses. One is as per power-up reset vector address 0xFFFE bytes and the other is as per reset vector at 0xFFFC bytes. The latter is for start after the Reset instruction executes or after a time-out from a watchdog timer occurs.

A push-button switch may also be interfaced with MCU through the reset circuit to start the processor from the beginning start-up address. When there is a power glitch, the processor reset circuit should let the processor start smoothly from the beginning and prevent the intermediate voltage levels. In addition, when a clock monitor detects the MCU slowdown below certain frequencies due to a fault, then also the reset must activate.

The reset circuit activates for a few clock cycles and then deactivates to let the MCU processor start executing the instructions.

There is a reset pin (Table 2.1) in the MCU. It becomes input on power-up and becomes output pin for a few clock cycles to enforce the reset state in other interfaced external devices with the system. The pin finally deactivates after the program execution begins.

The reset circuit (Figure. 2.16) can be made using an external IC circuit like MAX 6314 and Motorola MC 34064. Note that on reset, not only the program counter reloads but also the default processor values reload.

2.3.16 Oscillator Circuit

Oscillator is required for generating internal states and clock pulses. 8051 usually uses 11.052 MHz or 12 MHz. X-Tal. A circuit is shown in Figure 2.17(a). If an internal clock generator is used then an internal capacitor is used, Figure 2.17(b) shows circuit when internal clock generator is used.

2.4 RESOURCES IN ADVANCED AND NEXT-GENERATION MICROCONTROLLERS

Advanced MCUs have ALUs in their arithmetic logic unit (ALU) the multiplier and accumulate subunit, floating point processing subunit, assembly optimizer and C compiler.

An MCU can have the CAN module (CAN means a network with a bus called control area network bus). An MCU can have the USB module (USB means a network with a bus called Universal Serial Bus).

MCU can have 6 to 12 PWM Channels for multi-channel analog outputs.

There can be communication I/F, 8 or 16 HPI (host port interface), 6 or more external DMA channels support, two or more standard serial ports, time-division multiplexed serial ports, multi-channel and bidirectional serial ports.

There can be a special port that has analog input and output with the CODECs. CODEC is used in telecommunication. It is a unit for digital PCM coding by ADC and other operations and decoding of analog signals by DAC and other operations at the output and input, respectively.

Example 2.35

μPSD MCU has the following resources:

1. High-density dual bank and flexible memory.
2. Programmable logic (no need of external logic circuits and gates and address decoder circuitry), Peripheral set with devices with USB.
3. Enhanced Programmable Counter Array (PCA), 9 number counter/timers.
4. PWMs.
5. I²C, Dual UART (x2), SPI and IrDA interfaces.
6. 10-bit ADC with fast 6 μsec conversion rate yields sampling rate of 166 KHz.
7. On-chip debug via JTAG and in-system programmable via JTAG (no need of external hardware emulators).

Example 2.36

Next-generation MCUs (Chapter 16) based on ARM have the 32-bit RISC processor core with CISC instruction set and on-chip compilation unit. These have super scaling multi-stage integer pipeline (s). They have multi-entry write buffers. This avoids blocking (waiting) of the processor during the external memory writes. The 0.13 foundry processes deliver 350 MHz to 500+ MHz and over 1 GHz on next-generation 0.1 μm processors. ARM 11-based family MCUs have the instructions sets, which give reduced code densities. It has the ARM DSP extensions and SIMD media-processing extensions.

SUMMARY

1. The architecture of 8051 families is based on 8048. 8048 has 3 ports P0, P1 and P2. It has 128 B internal RAM and 1 kB ROM. 8051 has 4 ports.
2. The port pins are multi-functional in the MCUs and are also used as the buses.
3. Microcontrollers have a number of internal devices and many resources.
4. The 8-bit and 16-bit internal buses carry data and the instructions for processing.
5. The flash and EEPROM memories are electrically programmable and erasable memories. Flash memory is used in many systems.
6. Pulse width modulation is a device to obtain analog outputs from the MCU after integration of the PWM pulses.
7. An MCU may have multichannel ADCs. The digital bits saved in the ADC register maps to the analog input(s).
8. Reset circuit of the MCU performs the important functions of starting the MCU. The interface devices are also reset without any glitch.
9. An MCU may have the watchdog timer. It helps in rescuing the system when a program hangs in between.
10. The power-down mode saves power when the system runs continuously. The MCU provides for STOP instructions and WAIT for saving power when processing is not required.
11. An MCU has timers. A timer can be used for real-time control.
12. An MCU of 8051 family has a powerful bit-manipulation unit using a Boolean processing unit.
13. Serial UART and synchronous communication devices are present in the MCUs.
14. New-generation MCUs have a large number of features with fast processing capabilities.

KEY TERMS

8048family: A microcontroller on which 8051 families of microcontrollers were introduced later.

ADC: An analog input converted to digital bits, whose decimal value maps the input with respect to a reference voltage input.

Address bus: A bus to carry the address for the memory and devices externally interfaced to an MCU or CPU.

Baud rate: Rate by which the bits are sent in an UART.

Bit transfer: A bit paced at one address from another address.

Bus width: Number of lines in the bus. An 8-bit bus carries 1 byte data in a single cycle.

CAN: Controller area network—a bus for the networked embedded systems; it is mostly used in the automobile and control systems.

Clock circuit: A circuit to generate the clock pulse to synchronize all the operations in the system.

CODEC: A unit for the coding for the analog input for the line output and decoding of the line input to retrieve the analog input for a voice or music or analog communication.

Counter: A digital circuit to count the input pulses.

DAC: A unit for obtaining analog output using the digital bit at an input or at a register.

Data bus: A bus to carry the data bits or code bits.

Data direction register: A register in which each bit can be programmed to set each bit at a parallel port as input or output after the programming.

Data memory: A separate memory with address space separate from the program memory.

EEPROM: Electrically erasable electrically programmable read-only memory.

Erase: A process that makes all bits as the 1s. Free-running counter: A counter in non-reset, nonstop and non-loadable state, which timeouts at regular intervals and interrupts on successive overflows.

Flash: A memory with an additional feature over EEPROM in which a sector(s) of byte can be erased simultaneously using the floating gates technology.

Handshaking: A mechanism by which firstly two signals communicate and then a port sends the latched byte or strobes the byte into it.

Input capture: A mechanism by which a time register captures from a running timer the instances ofthe events at an input pin or at another device and there is interrupt on each capture.

Instruction decoder: A decoding unit attached to the instruction register, which stores the code just before execution. The unit initiates the “controller and sequencer” actions to execute the code.

Integrator: A circuit based on OPAMP and resistor and capacitors to integrate the input up to a certain time. If its input is PWM output of an MCU, it implements the DAC operation.

Inter-processor communication: A communication (serial synchronous) between two systems.

Internal bus: A bus to carry data byte(s) or code(s) at an instance from one structural unit of MCU to another.

Internal RAM: A RAM internally available in the MCU for the registers and/or data variables and stack.

Interrupt mask: A register where a bit can be set or reset to enable or disable a maskable source of interrupt from the devices or external sources.

Interrupt source: A hardware or software related event, which interrupts the foreground program to enable execution of a service routine called the interrupt service routine.

Interrupt mechanism: A mechanism by which the interrupting sources are serviced in an MCU or CPU.

IO devices: The devices or ports to latch the bits for further processing by the MCU during input or to accept the latched bits from the bus for sending output.

kbps: Kilo bits per second—a unit to express the rates of bits transferred on a serial line.

Keyboard: A unit that provides interaction to a user when using a computing system. Laboratory device programmer: A unit to program the on-chip and off-chip CPLDs, EPROMs, EEPROMS and flashes.

Masked ROM : A ROM ready to finally install in the system after undergoing a process to fabricate a mask as per the program and then etch the unetched metal layers in the ROM memory unit.

Latch: A circuit to set the state of output according to the input state which was there during the period when the clock/control input was active.

LCD display: A liquid crystal-based one line or multiline display.

Open drain port: A port with each bit needing external passive or active pull up when interfacing it. It must also be written 1s before using the same as an input port.

Out compare: A mechanism by which a register called out-compare register compares the contents with a running timer and can generate interrupt(s) or output(s) at each successful comparison.

Parallel port: An addressable multibit unit, which can latch the bits after processing for the output and which can strobe the bits and latch before processing.

Power-down mode: A mode in which the processor deactivates the clocking unit and sleeps by a stop instruction or by an autoshutdown program and from which the processor can wake up again on interrupt; it saves power and only standby RAM is delivered power during the stop.

Pre-scaling: A process, for example, in a unit to divide and set the input pulse rates for a timer. Prescaling factor can be prefixed in the MCU or may be programmable in the MCU.

Priority assignment: A mechanism to program the priority of servicing among the multiple interrupt sources.

Program counter: A CPU register to hold the address of byte(s) for the instruction for fetch from memory.

Programmable timer: A timer whose functions can be programmed in an MCU.

Pulse width modulation (PWM): A unit to give pulse output with width percentage mapped to the available digital or analog input or to get a desired analog output from the bits in a register.

Real-time clock: A clock continously ticking and interrupting the system and used for the real-time control in the system.

Reset circuit: A ciruit that brings the CPU and associated units to the start-up state.

ROM image: A finalized program, constants and strings data, which is placed in the ROM of the system.

Sample-hold amplifier: An amplifier to sample the input for a fixed period so that the output is stable for the hold period. It is usually used with the ADC to let the analog input be noise free and stable during ADC operation of converting into the bits.

Serial asynchronous communication: A serial stream of bits in which the bytes or frames do not maintain the constant phase difference. The UART mode communication is also an asynchronous serial.

Serial synchronous communication: A serial stream of bits in which the bytes or frames maintain constant phase difference.

STOP instruction: An instruction which executes when it should enable execution in an MCU and which on execution brings the processor to a sleep state by deactivating application of the clock to the CPU units and which permits only standby power dissipation.

Timer: A device to increment when the input clock pulses are applied to it after suitable scaling. It interrupts on timeout(s), which occur on its overflow(s). It functions as counter when clock pulses are not used but external circuits give the input pulses for counting those pulses.

Timer processor unit: A unit to process the timing operation-related instructions.

UART: An asynchronous serial communication mode in which the start bit has 1 to 0 transition to begin with, then sends the data bits and then the stop bit. Before the stop bit there may be an additional bit for special use like checking the parity.

Watchdog timer: A timer, which once set, prevents the processor from hanging in a loop or waiting state and brings the processor to the restart state. [Hang up means not able to come to end due to endless wait.]

REVIEW QUESTIONS

1. What are the resources available at the 8048 and hence explain the difference in functional overview of the 8048 and microprocessor?
2. Define (a) input port and (b) output port.
3. What is meant by bus cycle? If the internal bus width is 8, then explain why the 16-bit operations take two bus cycles.
4. What is the advantage of having the program memory and data memory at a unified address space in Princeton architecture?
5. What is the advantage of having the program memory and data memory at distinct address spaces as in Harvard architecture?
6. List the benefits of EEPROM and flash.
7. When should an EEPROM be used and when should a flash be used?
8. Parallel port can be used for short distances, while the serial port can be used for long distances and remote locations. Why?
9. Internal buses are not serial buses. Explain.
10. What is the advantage of multiplexing of the data and address buses at MCU?
11. What is the advantage of multiplexing the busbuffer and port latch at an MCU?
12. When should on-chip ports and off-chip ports be used?
13. MCUs have the memory-mapped I/O operations unlike 80x86. What is the advantage?
14. When do we use a parallel port with and without handshaking signals? List the merits.
15. Describe the different uses of the asynchronous and synchronous serial ports.
16. MCUs have a PWM unit in place of the on-chip DACs. Why?
17. Describe the PWM width percentage that is mapped with the bits in an MCU register. If the clock rate is halved, what happens to the width percentage?
18. Describe on-chip multi-channel ADC applications and how the analog input maps with the converted bits.
19. Describe reset operation in an MCU. Reset circuitry in the MCU needs special design. Why?
20. Explain the use of watchdog timer.
21. When we use a STOP instruction in a program and the MCU provides for its enabling and disabling, we should disable execution of the STOP instruction when using a watchdog timer. Why?
22. A timeout period in watchdog timer is fi xed as 2048 μs for 12 MHz CPU clock and we need timeouts after in an 10.24 ms. (Hint: Restart the watchdog timer 5 times before the expiry of 2048 ms.)
23. When should the watchdog timer be disabled? At what instance and in which application should we enable the watchdog timer?
24. What are the uses of a power-down mode in an MCU? When does an MCU run in this mode?
25. What are the applications of the timer in an MCU? Why do the MCUs need at least one timer?
26. Give an example of the resources in the newgeneration MCUs.
27. List the applications of an MCU resource.
28. Explain uses of the open-drain output and quasi open-drain output.
29. Explain how to obtain a real-time clock in a system.
30. Explain how to use a data direction register with a parallel port.
31. Describe the synchronous serial port and asynchronous serial port.
32. Explain UART port operations in 10T and 11T modes.

PRACTICE EXERCISES

1. Explain the 8048 pins/signals.
2. Advanced MCUs have RISC core, on-chip CISC compiler and caches. What are their applications? List 10 examples.
3. How many bus cycles for fetch and execution are needed to fetch a 16-bit instruction of 3 bytes long?
4. An MCU has registers, ports and internal RAM at the unified address space and with the same set of addressing methods. What is the advantage?
5. An MCU has registers, ports and internal RAM at the non-unified address space (for example, special function registers and internal RAM between 0x80 and 0xFF) and with a different set of addressing methods (for example, direct and indirect addressing modes for 0x80-0xFF SFRs and RAM ). What is the advantage?
6. An MCU has a set of 8-bit addresses for each byte and a set of 8-bit addresses for the bits in certain bytes in the RAM and registers (for example, 0x00-0xFF for the internal RAM and 0x00-0xFF for the bits in certain RAM and SFRs). What is the advantage?
7. An MCU has 8-bit addresses for each byte and does not provide for the 8-bit addresses for the bits in certain bytes in the RAM and registers. What is the advantage?
8. Why can the constants and strings be placed in EEPROM and OTP data-memory space as well as in masked ROM and program memory space?
9. How do you quantify the parallel port driving capability and portloading capability?
10. A watchdog timer timeout period in an MCU is fixed as 2048 ms for 12 MHz CPU clock. If the CPU clock is operated at 8 MHz, when will be the enabled case watchdog timer timeout?
11. A timer interrupts after 1024 ms. Let the prescaling factor now be set to 16 in place of 1 earlier out of four possible values (1, 4, 16 and 64). What will be the timeout-overflow intervals now? What are the four possible intervals for the timeout interrupts?
12. An MCU has a 16-bit PWM pulse accumulator register. How can we get a duty cycle (PWM width %) be equal to 75%?
13. Give an integrator design when the analog output is 0 at 50% duty cycle, +ve at < 50% and −ve at > 50%.
14. How does a single timer create the multiple applications and multiple timings in a system?
15. Show the timing diagrams for handshaking signals and input bits at (i) an input port (ii) an output port and (iii) an I/O port.
16. How do we program software codes for a timing operation? (Hint: Use a loop and on enter and exit from loop, toggle a port bit and set the number of looping cycles such that the desired time is set.)
17. An MCU has a memory-mapped I/O. How will you create eight external ports between 0xEFF8 and 0EFF.
18. Using multiplexers and demultiplexers, how can there be more ports from two parallel ports given in an MCU?
19. Let a microcontroller interface have four modems. How will we use the TxD and RxD signals of an asynchronous serial interface in MCU.

MULTIPLE CHOICE QUESTIONS

1. An 8048 port P2 signal has
   1. address lower 8 bits
   2. 8 data bits
   3. Latched port bits
   4. Either the address higher 8 bit or latched port bits
2. 8048 accumulator (A-register)
   1. Is an input during an ALU operation and accumulates the results from the ALU
   2. Is an input during an ALU operation and accumulates along with the flags the results from the ALU
   3. Accumulates the results from the ALU
   4. Accumulates temporarily the A-register before an ALU operation
3. , , and are the signals in 8048 (also in 8051). In this
   1. , are not at the Port P3
   2. , , and are at P3
   3. all four are at P3
   4. , and are at P3
4. Classic 8051, extended 8051 and 8051MX have which of the following memory?
   1. 64 kB external program ROM, 64 kB external data and 128 B internal RAMs, respectively
   2. 64 kB program memory, 16 MB program plus constants memory and 64 MB program plus constants, respectively
   3. 64 kB program memory, 16 MB program plus constants memory and 8 MB program plus 8 MB constants, respectively
   4. 64 kB, 1 MB and 8 MB, respectively
5. 68HC11/12/16 has
   1. 4 kB and 64 kB internal/external common memory in unified address space, no separate program and data memory and 4 port plus ADC port
   2. 64 kB, 1 MB and 4 MB common memory in unified address space, no separate program and data memory and 4 ports each
   3. 64 kB, 1 MB and 4 MB memory with separate separate program and data memory and 4, 12 and 12 ports
   4. 64 kB/ 4 MB/ 4 MB common memory in unified address space, no separate program and data memory and 4, 12, and 12 ports
6. 8096 ALU can perform
   1. 1 or 8 or 16-bit operations
   2. 16-bit operations
   3. 8 or 16 or 32 bit operations
   4. 8 or 16-bit operations only
7. An MCU has a port P2 and 64 kB external data memory. Ports P0, P1 and P3 are not usable in an expanded mode. The total external memory space now available is
   1. 65,536 B
   2. 64,000 B
   3. 65,472 B
   4. 63,036 byte
8. A port must have.
   1. One handshaking signal to request data input and one for acknowledgement after data input
   2. One handshaking signal to request data input and one for acknowledgement after data input and one handshaking signal to convey buffer full and one for acknowledgement after data output successful on two common or four separate pins
   3. One handshaking signal to convey buffer full and one for acknowledgement after data output successful on two common or four separate pins
   4. Data direction register
9. An MCU does not have bit-manipulation instructions and only the byte operations are feasible. To reset the bit 0 and bit 7, the following operations are needed when all the bits were 1s earlier:
   1. AND with 1000 0001
   2. XOR with 1000 0001
   3. XOR with 1111 1111
   4. OR with 1000 0001
10. EEPROM
    1. Is flash also
    2. Is for erase at a time of one byte and flash for a sector of bytes
    3. Is different from flash
    4. Works identically for erase as well as write
11. A pulse width modulator gives an output pulse width of n₁% and after the integrator circuit gives 2 V when the pulse accumulator loads 0x40 (= 40H). It gives the width n₂% and −2 V when the pulse accumulator loads 0x80 (= 80H). The n₁ and n₂ are
    1. 0 and 50
    2. −2/25 and +2/25
    3. 50 and 100
    4. 25 and 75
12. A single reference input ADC operated on 5 V power supply input to its circuit and gives an output of 0000 1000. When input is 50 mV and 0000 1001 when input is 56.25 mV. It can measure maximum
    1. 1.6 V
    2. 3.2 V
    3. 5V
    4. Maximum cannot be determined with this information alone
13. An 8-bit auto-reload timer is loaded to an initial value of 40. It is given an input at the start of a race from a clock of 8 MHz after pre-scaling by a factor of 64. Now, the timer will overflow (timeout) in
    1. (256 − 40) μs
    2. Every (40/64) μs
    3. Every (256 − 40)/8 μs
    4. (40/8) μs
14. A byte 1001 1110 is sent on an asynchronous UART in 10T periods where Tdetermines from the baud rate of 9600. For how much minimum interval from the first start transition will there be 1s when this byte is sent twice successively with a gap of 100 ms.
    1. (12 × 104 + 100) μs
    2. (11 × 104 + 100) μs
    3. (10 × 104 + 100) μ
    4. (16 × 104 + 100) μs
15. Awatchdog timer is loaded 2048 in 8051 operating at 12 MHZ. It is reloaded when the program was running after 1000 μs. Watchdog timer will reset the MCU in.
    1. 4096 μs
    2. Cannot reset when reloaded
    3. 1000 μs
    4. 3048 μs
16. A free-running counter is driven by 16 period inputs. On the start of a race, its content was captured and the input capture register showed 16,384 (= 0100 0000 0000 0000). At the stop of the race its contents were captured again and showed 65,530 ( = 1111 1111 1111 1010). The race period is given by
    1. 16 × (65,530 − 16,384) μs
    2. 16 × [(65,530 − 16,384) + 65,536 ×n] μs
    3. 16 × [(65,536 − 16,384 + 65,530) + 65,536 × n] μs
    4. 16 × n × (65,530 − 16,384) μs,

    where n is the number of times it overflows after the first overflow.