4Space vector pulse width modulation algorithm for the three-level inverter

Three-level inverter topology is widely used in high-voltage/high-power applications with currently available power devices because of its high-voltage handling and good harmonic rejection capabilities. In the previous chapters, the space vector pulse width modulation (SVPWM) scheme for the two-level inverter is described in detail. However, the three-level inverter roughly has four times better harmonic content compared with two-level topology. The harmonic contents of the output voltage are fewer than those of the two-level inverter at the same switching frequency. In addition, the blocking voltage of each switching device is a half of the dc-link voltage and is thus an easy-to-realize high-voltage and large-capacity inverter system.

In this chapter, the SVPWM algorithm for a three-level inverter fed induction motor is presented and analyzed. This SVPWM algorithm provides high-safety voltages with less harmonic components compared to two-level structures and reduces the switching losses by limiting the switching to two thirds of the pulse duty cycle. The voltage vector selection procedure, switching time calculation, and switching pattern generation for the three-level inverter are described in detail. This SVPWM algorithm contributed to the reduction of switching power losses and has the advantages of a three-level inverter that carry out voltage with contents of less harmonic injection than two-level inverter. The proposed method can be applied to multilevel inverters above the three-level inverters. However, as the level of inverter increases, the sector identification, switching vector determination, and dwelling time calculation become more complex. The computational complexity and the execution time increase.

The implementation of SVPWM involves:

Sector identification can be done using coordinate transformation of the reference vector into a two-dimensional coordinate system. The sector can also be determined by resolving the reference phase vector along the a-, b-, and c-axes and by repeated comparison with discrete phase voltages. After identifying the sector, the voltage vectors at the vertices of the sector are determined. Once the switching voltage space vectors are determined, the switching sequences can be obtained. The calculation of the duration of the voltage vectors can be simplified by mapping the identified sector to the sector corresponding to the two-level inverter. To obtain optimum switching, the voltage vectors are to be switched for their respective durations, in a sequence such that only one switching occurs as the inverter moves from one switching state to another. Conventional techniques involve look-up tables to achieve this optimum switching sequence [50].

4.1SVPWM for the three-level inverter

4.1.1Three-level inverter topology and switching states

The schematic diagram of a three-level inverter is shown in Fig. 4.1. Each phase of the inverter consists of two clamping diodes, four IGBTs, and four freewheeling diodes. Since three kinds of switching states and terminal voltages exist in each phase, the three-level inverter has 27 (33) switching states. Figure 4.2 shows the representation of the space voltage vectors for output voltage and the space vector diagram of all switching states, where P, O, and N represent the terminal voltage, respectively, that is Vdc/2, 0, −Vdc/2 (Tab. 4.1). According to the magnitude of the voltage vectors, we divide them into four groups: zero-voltage vector (ZVV; V0), small-voltage vectors (SVVs; V1, V4, V7, V10, V13, V16), middle-voltage vectors (MVVs; V3, V6, V9, V12, V15, V18), and large-voltage vector (LVV; V2, V5, V8, V11, V14, V17). The ZVV has three switching states; SVV, two switching states; and the MVV and LVV have only one switching state.

Fig. 4.1: Schematic diagram of the three-level inverter.

Tab. 4.1: Switching states of the three-level inverter.

Fig. 4.2: Space vector diagram of the three-level inverter.

4.1.2Voltage vectors and calculation of switching times

Figure 4.3 shows the triangle formed by the voltage vectors V0, V2, and V5. This triangle is divided into four small triangles 1, 2, 3, and 4. In the space voltage vector PWM, generally, output voltage vector is formed by its nearest three vectors to minimize the harmonic components of the output voltage and the current. The duration of each vector can be calculated by vector calculation. For instance, if the reference voltage vector falls into triangle 3, the duration of each voltage vector can be calculated by the following equations:

$\begin{array}{l}{\text{V}}_{\text{1}}{\text{T}}_{\text{a}}+{\text{V}}_{\text{3}}{\text{T}}_{\text{b}}+{\text{V}}_{\text{4}}{\text{T}}_{\text{c}}={\text{V}}^{\star }{\text{T}}_{\text{S}}\\ {\text{T}}_{\text{a}}+{\text{T}}_{\text{b}}+{\text{T}}_{\text{c}}={\text{T}}_{\text{S}}\\ {\text{V}}_1=\frac{1}{2}\text{V;}{\text{V}}_3\text{=}\frac{\sqrt{3}}{2}{\text{Ve}}^{\text{j}\frac{\pi }{6}};{\text{V}}_4\text{=}\frac{1}{2}{\text{Ve}}^{\text{j}\frac{\pi }{3}};{\text{V}}^{\star }={\text{Ve}}^{\text{jθ}}\end{array}$

Fig. 4.3: Voltage vectors of the three-level inverter in sector I.

Substituting Eq. (4.3) in Eq. (4.1) and changing into trigonometric form

$\frac{\text{1}}{\text{2}}\text{V}\cdot {\text{T}}_{\text{a}}+\frac{\sqrt{3}}{2}\text{V}\cdot \left(\cos \frac{\pi }{6}+\text{j}\sin \frac{\pi }{6}\right)\cdot {\text{T}}_{\text{b}}+\frac{1}{2}\text{V}\left(\cos \frac{\pi }{3}+\text{j}\sin \frac{\pi }{3}\right)\cdot {\text{T}}_{\text{c}}=\text{V}(\text{cos}\text{θ}+\text{j}\text{sin}\text{θ})\cdot {\text{T}}_{\text{s}}.$

Separating the real and imaginary parts from Eq. (4.4),

$\begin{array}{l}\frac{\text{1}}{\text{2}}\cdot {\text{T}}_{\text{a}}+\frac{\sqrt{3}}{2}\left(\cos \frac{\pi }{6}\right)\cdot {\text{T}}_{\text{b}}+\frac{1}{2}\left(\cos \frac{\pi }{3}\right)\cdot {\text{T}}_{\text{c}}=\text{V}(\text{cos}\text{θ})\cdot {\text{T}}_{\text{s}}\\ \frac{\sqrt{3}}{2}\left(\sin \frac{\pi }{6}\right)\cdot {\text{T}}_{\text{b}}+\frac{1}{2}\left(\sin \frac{\pi }{3}\right)\cdot {\text{T}}_{\text{c}}=\text{V}(\text{sin}\text{θ})\cdot {\text{T}}_{\text{s}}.\end{array}$

By solving Eq. (4.2), Eq. (4.5), and Eq. (4.6), the values of Ta, Tb, and Tc are

$\begin{array}{l}{\text{T}}_{\text{a}}={\text{T}}_{\text{s}}[1-2\text{ksin}(\theta )]\\ {\text{T}}_{\text{b}}={\text{T}}_{\text{s}}[2\text{ksin}(\text{θ}+60)-1]\\ {\text{T}}_{\text{c}}={\text{T}}_{\text{s}}[2\text{ksin}(\text{θ}-60)+1],\end{array}$

Where $\text{k}=\frac{2}{\sqrt{3}}\text{V}.$

In other regions (1, 2, 4), the duration for each voltage vector can be calculated in the same way. Table 4.2 shows the switching times of voltage vector in sector I. The switching pattern of the three-level inverter is shown in Fig. 4.4 and corresponding switching states are shown in Tab. 4.3.

Tab. 4.2: Switching times of the three-level inverter.

4.1.3Optimized switching sequence

Fig. 4.4: Switching pattern of the three-level inverter.

Tab. 4.3: Switching states of the three-level inverter.

4.2Results and discussions

To verify the proposed SVPWM algorithm, simulation studies have been carried out for the two- and three-level inverter fed induction motor. The simulation parameters of induction motor used in this method are given in Appendix I. The simulation results for the two-level inverter are shown in Figs. 4.5 to 4.11. The gate currents and pole voltages of the two-level inverter are shown in Figs. 4.5 and 4.6, respectively. The phase voltage and line voltages of the two-level inverter are shown in Figs. 4.7 and 4.8, respectively. The d-axis and q-axis stator currents of the two-level inverter fed induction motor are shown in Fig. 4.9. The torque, speed, and flux of the two-level inverter fed induction motor are shown in Fig. 4.10 for a load torque (TL) of 10.32 N-m. The harmonic spectrum of the inverter output voltage and total harmonic distortion (THD) are shown in Fig. 4.11.

For the same conditions, Figs. 4.12 to 4.18 give the results for the three-level inverter fed induction motor. Figures 4.12 and 4.13 show the gate currents and pole voltages, respectively, of the three-level inverter. The phase voltages and line voltages of the three-level inverter are shown in Figs. 4.14 and 4.15, respectively. The d- and q-axes stator currents of the three-level inverter fed induction motor are shown in Fig. 4.16.

Fig. 4.5: Gate currents of the two-level inverter.

Fig. 4.6: Pole voltages of the two-level inverter.

Fig. 4.7: Phase voltages of the two-level inverter.

Fig. 4.8: Line-to-line voltages of the two-level inverter.

Fig. 4.9: Stator currents of the two-level inverter fed induction motor.

Fig. 4.10: Torque, speed, and flux responses of the two-level inverter fed induction motor for load torque (TL) of 10.32 N-m.

The torque, speed, and flux of the three-level inverter fed induction motor are shown in Fig. 4.17 for a load torque (TL) of 10.32 N-m. The harmonic spectrum of the inverter output voltage and the THD are shown in Fig. 4.18. Tables 4.4 and 4.5 show the comparison between two- and three-level inverter performances. The interpretation of all the results shows that in case of the three-level inverter, the output voltage, speed, and torque response considerably improves and that the torque ripples and the THD reduce.

Fig. 4.11: Output line voltage (and its harmonic spectrum) of the two-level inverter.

Fig. 4.12: Gate currents of the three-level inverter.

Fig. 4.13: Pole voltages of the three-level inverter.

Fig. 4.14: Phase voltages of the three-level inverter.

Fig. 4.15: Line-to-line voltages of the three-level inverter.

Fig. 4.16: Stator currents of the three-level inverter fed induction motor.

Fig. 4.17: Torque, speed, and flux responses of the three-level inverter fed induction motor for load torque (TL) of 10.32 N-m.

Fig. 4.18: Output line voltage (and its harmonic spectrum) of the three-level inverter.

From simulation results, the performance of the two- and three-level inverters has been analyzed. It shows that the three-level inverter is more effective than the two-level inverter in terms of rotor speed of the induction motor and the THD (Tab. 4.4). Table 4.5 shows that as the modulation index increases, the THD decreases.

Tab. 4.4: Performance of the two- and three-level inverters.

Tab. 4.5: Performance of inverters with respect to modulation index.

4.3Conclusions

In the field of high-power, high-performance applications, multilevel inverters seem to be the most promising alternative. In this chapter, the application of SVPWM control strategy on three-level inverter has been proposed and analyzed. The proposed SVPWM algorithm provides high-safety voltages with less harmonic components compared to two-level structures and reduces the switching losses by limiting the switching to two thirds of the pulse duty cycle. On the one hand, the latter aimed to prove the effectiveness of SVPWM in the contribution of switching power losses reduction and to show the advantage of the three-level inverter that carry out voltages with contents of less harmonic injection than the two-level inverter. On the other hand, the simulation results show that as modulation index increases, the THD decreases and the fundamental RMS value increases linearly. In the first proposed method, the obtained THD for the two- and three-level inverters are 54.02% and 28.60%, respectively.