[1] S. Abraham and K. Padmanabhan, “Performance of direct binary n-cube networks for multiprocessors,” IEEE Transactions on Computers, 38(7):1000–1111, 1989.

[2] Actel, Axcelerator Family FPGAs, v2.8, 2009.

[3] Actel, IGLOO Handbook, v1.2, 2009.

[4] Actel, ProASIC Plus Family Flash FPGAs, v3.5, 2004.

[5] Actel, ProASIC3 Handbook, v1.4, 2009.

[6] F. Agakov et al., “Using machine learning to focus iterative optimization,” Pro­ceedings of the International Symposium on Code Generation and Optimization, IEEE, 2006, pp. 295–305.

[7] A. Agarwal, Analysis of Cache Performance of Operating Systems and Multi­programming, PhD thesis, Computer Systems Laboratory, Stanford University, published as CSL-TR-87-332, 1987.

[8] A. Agarwal, “Limits on interconnection network performance,” IEEE Transac­tions on Parallel and Distributed Systems, 2(4):398–412, 1991.

[9] K. Ajo, A. Okamura and M. Motomura, “Wrapper-based bus implementation techniques for performance improvement and cost reduction,” IEEE Journal of Solid-State Circuits, 39(5):804–817, 2004.

[10] Altera, Avalon Interface Specifications, Version 1.2, 2009.

[11] Altera, Nios embedded processor, http://www.altera.com/products/ip/processors/nios/nio-index.html, 2010.

[12] Altera, Nios II Processor Reference Handbook Ver. 9.1, 2009.

[13] Altera, Nios II Performance Benchmarks, 2010.

[14] Altera, Stratix II Device Handbook, SII5V1-4.4, 2009.

[15] Altera, Stratix III Device Handbook, Version 2.0, 2010.

[16] Altera, Stratix IV Device Handbook, Version 4.2, 2010.

[17] H. Amano, “Japanese dynamically reconfigurable processors,” Proceedings of ERSA, 2009, pp. 19–28.

[18] AMD, AMD Geode Brochure, 2005.

[19] ARC, ARC 600, Configurable 32-bit CPU core Description, 2005.

[20] ARM, ARM 1020E, Technical Reference Manual, rev. r1p7, 2003.

[21] ARM, AMBA Bus Standard Specifications, 2010.

[22] ARM, AMBA Specification, Rev 2.0, ARM-IHI-0011A.

[23] ARM, ARM VFP11, Vector Floating-Point Coprocessor for ARM1136JF-S Processor r1p5, Technical Reference Manual, 2007.

[24] ARM, ARM1136J(F)-S Processor Specifications, 2010.

[25] J.M. Arnold, “The architecture and development flow of the S5 software configurable processor,” Journal of VLSI Signal Processing, 47(1):3–14, 2007.

[26] Arteris, “A comparison of network-on-chip and busses,” White Paper, 2005.

[27] K. Asanovic et al., The landscape of parallel computing research: A view from Berkeley, Technical Report No. UCB/EECS-2006-183, 2006.

[28] K. Atasu et al., “CHIPS: Custom hardware instruction processor synthesis,” IEEE Transactions on Computer-Aided Design, 27(3):528–541, 2008.

[29] K. Atasu et al., “Optimizing instruction-set extensible processors under data bandwidth constraints,” Proceedings of Design, Automation and Test in Europe Conference, IEEE, 2007, pp. 1–6.

[30] T. Austin, E. Larson and D. Ernst, “SimpleScalar: An infrastructure for computer system modeling,” IEEE Computer, 35(2):59–67, 2002.

[31] B. Bacheldor, “Belgium hospital combines RFID, sensors to monitor heart patients,” RFID Journal, March 6, 2007.

[32] B. Bailey, G. Martin and A. Piziali, ESL Design and Verification: A Prescription for Electronic System-Level Methodology, Morgan Kaufmann, 2007.

[33] J.E. Barth et al., “Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering,” IBM Journal of Research and Developmental, 46(6):675–689, 2002.

[34] S. Baskiyar and N. Meghanathan, “A survey of contemporary real-time operating systems,” Informatica, 29:233–240, 2005.

[35] J. Becker, M. Hubner, G. Hettich, R. Constapel, J. Eisenmann and J. Luka, “Dynamic and partial FPGA exploitation,” Proceedings of the IEEE, 95(2):438–452, 2007.

[36] T. Becker, W. Luk and P.Y.K. Cheung, “Enhancing relocatability of partial bitstreams for run-time reconfiguration,” Proceedings of the IEEE Interna­tional Symposium on Field-Programmable Custom Computing Machines, 2007, pp. 35–44.

[37] T. Becker, W. Luk and P.Y.K. Cheung, “Parametric design for reconfigurable software-defined radio,” Reconfigurable Computing: Architectures, Tools and Applications, LNCS 5453, J. Becker et al. (eds.), Springer, 2009.

[38] T. Becker, W. Luk and P.Y.K. Cheung, “Energy-aware optimisation for run-time reconfiguration,” Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2010, pp. 55–62.

[39] P. Beckett and S. Goldstein, “Why area might reduce power in nanoscale CMOS,” IEEE International Symposium on Circuits and Systems, 3:2329–2332, 2005.

[40] L. Benini and G. De Micheli, “Networks on chips: A new SOC paradigm,” IEEE Computer, 35(1):70–78, 2002.

[41] D.P. Bhandarkar, “Analysis of memory interference in multiprocessors,” IEEE Transactions on Computers, C-24(9):897–908, 1975.

[42] V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, (2nd ed.), Kluwer, 1997.

[43] J. Bicarregui, C.A.R. Hoare and J.C.P. Woodcock, “The verified software repository: A step towards the verifying compiler,” Formal Aspects of Computing, 18(2):143–151, 2006.

[44] M. Birnbaum and H. Sachs, “How VSIA answers the SOC dilemma,” IEEE Computer, 32(6):42–50, 1999.

[45] P. Biswas et al., “ISEGEN: Generation of high-quality instruction set extensions by iterative improvement,” Proceedings of DATE, 2005, pp. 1246–1251.

[46] P. Boehm and T. Melham, Design and verification of on-chip communication protocols, Oxford University Computing Laboratory Research Report, RR-08-05, 2008.

[47] K. Bonsor, “How power paper will work,” How Stuff Works, 12 January 2001.

[48] M. Borgatti et al., “A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O,” IEEE Journal of Solid-State Circuits, 38(3):521–529, 2003.

[49] J.A. Bower et al., “Dynamic clock-frequencies for FPGAs,” Microprocessors and Microsystems, 30(6):388–397, 2006.

[50] P. Brisk, A. Kaplan and M. Sarrafzadeh, “Area-efficient instruction set synthesis for reconfigurable system-on-chip designs,” Proceedings of DAC, 2004, pp. 395–400.

[51] D.C. Burger and T.M. Austin, “The SimpleScalar Tool Set, Version 2.0,” Computer Architecture News, 25(3):13–25, 1997.

[52] M. Butts, A.M. Jones and P. Wasson, “A structural object programming model, architecture, chip and tools for reconfigurable computing,” Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines, IEEE, 2007, pp. 55–64.

[53] Cadence Design Systems Inc, Palladium Datasheet, 2004.

[54] CEVA, Ceva X-1620 Product Note, 2005.

[55] K. Chen et al., “Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects,” IEEE Transactions of the Electron Devices, 44(11):1951–1957, 1997.

[56] D. Chen, J. Cong and P. Pan, “FPGA design automation: A survey,” Foundations and Trends in in Electronic Design Automation, 1(3):139–169, 2006.

[57] C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk and S. Wilton, “Dynamic voltage scaling for commercial FPGA,” Proceedings of the IEEE International Conference on Field-Programmable Technology, National University of Singapore, 2005, pp. 173–180.

[58] S. Ciricescu et al., “The reconfigurable streaming vector processor (RSVP),” IEEE/ACM International Symposium on Microarchitecture MICRO-36, pp. 141–150, 2003.

[59] ClearSpeed, ClearSpeed CSX600 Datasheet, 2006.

[60] K. Compton and S. Hauck, “Totem: Custom reconfigurable array generation,” Proceedings of the Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2001, pp. 111–119.

[61] K. Compton and S. Hauck, “Reconfigurable computing: A survey of systems and software,” ACM Computing Surveys, 34(2):171–210, 2002.

[62] G.A. Constantinides, “Word-length optimization for differentiable nonlinear systems,” ACM Transactions on Design Automation of Electronic Systems, 11(1):26–43, 2006.

[63] B.W. Cook, S. Lanzisera and K.S.J. Pister, “SoC issues for RF Smart Dust,” Proceedings of the IEEE, 94(6):1177–1196, 2006.

[64] CrossBow Technologies, Xfabric Core Connectivity Junction, Preliminary Product Specification, 2004.

[65] R. Etienne-Cummings, P. Pouliquen and M.A. Lewis, “A vision chip for color segmentation and pattern matching,” EURASIP Journal on Applied Signal Processing, 2003(7):703–712, 2003.

[66] U. Cummings, “PivotPoint: Clockless crossbar switch for high-performance embedded systems,” IEEE Micro, 24(2):48–59, 2004.

[67] Cymbet, The POWER FAB (Thin Film Lithium Ion Cell) Battery System, 2007.

[68] Cypress semiconductor, CY8C41123 and CY8C41223 Linear Power PSoC Devices, 2005.

[69] J. Daemen and V. Rijmen, The Design of Rijndael: AES—The Advanced Encryption Standard, Springer-Verlag, 2002.

[70] W.J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Transactions on Computers, 39(6):775–785, 1990.

[71] W.J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks,” Proceedings of the Design Automation Conference, 2001.

[72] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.

[73] S. Das et al., “A self-tuning DVS processor using delay-error detection and correction,” IEEE Journal of Solid-State Circuits, 41(4):792–804, 2006.

[74] K. DeHaven, “Extensible processing platform ideal solution for a wide range of embedded systems,” Xilinx White Paper WP369 (v1.0), 2010.

[75] J.A. DeRosa and H.M. Levy, “An evaluation of branch architectures,” Proceedings of the 14th Annual Symposium on Computer Architecture, ACM, 10–16, 1987.

[76] A.S. Dhodapkarm and J.E. Smith, “Tuning adaptive microarchitectures,” International Journal of Embedded Systems, 2(1/2):39–50, 2006.

[77] R. Dimond, O. Mencer and W. Luk, “Application-specific customisation of multi-threaded soft processors,” IEE Proceedings—Computers and Digital Techniques, 153(3):173–180, 2006.

[78] J. Duato, S. Yalamanchili and L. Ni, Interconnection Networks, Morgan Kaufmann, 2003.

[79] S. Dutta, “Architecture and implementation of multiprocessor SOCs for advanced set-top boxes and digital TV systems,” Proceedings of the 16th Symposium on Integrated Circuits and System Design, 2003, pp. 145–146.

[80] C. Ebeling et al., “Implementing an OFDM receiver on the RaPiD reconfigurable architecture,” IEEE Transactions on Computers, 53(11):1436–1448, 2004.

[81] E. El-Araby, I. Gonzalez and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Transactions on Reconfigurable Technology and Systems, 1(4):21, 2009.

[82] Elixent Corporation, DFA 1000 Accelerator Datasheet, 2003.

[83] Embedded Access, MQX RTOS Product Description, 2010.

[84] Fairchild Semiconductor, Two Input NAND Gate Layout, 1966.

[85] A. Fang et al., “Integrated hybrid silicon evanescent racetrack laser and photodetector,” 12th OptoElectronics and Communications Conference, 2007.

[86] A. Fauth, M. Freericks and A. Knoll, “Generation of hardware machine models from instruction set descriptions,” Proceedings of the IEEE Workshop VLSI Signal Processing, IEEE, 242–250, 1993.

[87] A. Fauth, J. Van Praet and M. Freericks, “Describing instruction set processors using nML,” Proceedings of DATE, IEEE, 503–507, March 1995.

[88] Federal Information Processing Standards publication 180-2, Secure Hash Standard, August 2002.

[89] A.K. Fidjeland and W. Luk, “Customising application-specific multiprocessor systems: A case study,” Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, IEEE, 239–244, 2005.

[90] A. Fidjeland, W. Luk and S. Muggleton, “A customisable multiprocessor for application-optimised inductive logic programming,” Proceedings of the Visions of Computer Science—BCS International Academic Conference, September 2008, pp. 319–330.

[91] D. Fisch, A. Singh and G. Popov, “Z-RAM ultra-dense memory for 90nm and below,” Hot Chips 18, August 2006.

[92] J.A. Fisher, “Very long instruction word architectures and the ELI-512,” Proceedings of the 10th Symposium on Computer Architecture, ACM, 140–150, 1983.

[93] J.A. Fisher, P. Faraboschi and C. Young, Embedded Computing, Elsevier, 2005.

[94] J.A. Fisher, P. Faraboschi and C. Young, “Customizing processors: Lofty ambitions, stark realities,” Customizable Embedded Processors, P. Ienne and R. Leupers (eds.), pp. 39–55, Morgan Kaufmann, 2007.

[95] D. Flynn, “AMBA: Enabling reusable on-chip designs,” IEEE Micro, 17(4):20–27, 1997.

[96] M.J. Flynn, Computer Architecture, Jones and Bartlett, 1995.

[97] M.J. Flynn, “Some computer organizations and their effectiveness,” IEEE Transactions on Computing, 21(9):948–960, 1972.

[98] M.J. Flynn and P. Hung, “Microprocessor design issues: Thoughts on the road ahead,” IEEE Micro, 25(3):16–31, 2005.

[99] M.J. Flynn, P. Hung and K.W. Rudd, “Deep-submicron microprocessor design issues,” IEEE Micro, 19(4):11–22, 1999.

[100] C.W. Fraser, D.R. Hanson and T.A. Proebsting, “Engineering a simple, efficient code-generator generator,” ACM Letters on Programming Languages and Sys­tems, 1(3):213–226, 1992.

[101] Freescale Semiconductor, Freescale e600 Core Product Brief, Rev.0, 2004.

[102] Freescale Semiconductor, Freescale MPC8544E PowerQUICC III Integrated Processor, Hardware Specifications, Rev.2, 2009.

[103] Fujitsu, MB93555A Product Description, 2010.

[104] H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985.

[105] S. Furber and J. Bainbridge, “Future trends in SoC interconnect,” Proceedings of the International Symposium on System-on-Chip, 2005, pp. 183–186.

[106] Gaisler, Leon 4 Product Description, 2010.

[107] K. Gaj and P. Chodowiec, “Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays,” Proceedings of the RSA Security Conference, 2001, pp. 84–99.

[108] A. Gerstlauer et al., “Electronic system-level synthesis methodologies,” IEEE Transactions on Computer-Aided Design, 28(10):1517–1530, 2009.

[109] S.K. Ghandi, VLSI Fabrication Principles, (2nd ed.), Morgan Kaufmann Publishers, 1994.

[110] D. Goodwin and D. Petkow, “Automatic generation of application specific processors,” Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2003, pp. 137–147.

[111] H.H. Goode and R.E. Machol, System Engineering—An Introduction to the Design of Large-Scale Systems, McGraw-Hill, 1957.

[112] P. Guerrier and A. Grenier, “A generic architecture for on-chip packet-switched interconnections,” Proceedings of the IEEE Design Automation and Test in Europe, IEEE, 250–256, 2000.

[113] I.J. Haikala, Program behavior in memory hierarchies, PhD thesis (Technical Report A-1986-2), University of Helsinki, 1986.

[114] A. Halambi and P. Grun, “Expression: A language for architecture exploration through compiler/simulator retargetability,” Proceedings of DATE, March 1999, pp. 485–490.

[115] J. Hayter, Probability and Statistics for Engineers and Scientists, Duxbury Press, 2006.

[116] J. Heape and N. Stollon, “Embedded logic analyzer speeds SoPC design,” Chip Design Magazine, August/September 2004.

[117] H. Hedberg, T. Lenart and H. Svensson, “A complete MP3 decoder on a chip,” Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2005, pp. 103–104.

[118] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, (4th ed.), Morgan Kaufmann, 2006.

[119] M. Hohenauer and R. Leupers, C Compilers for Asips: Automatic Compiler Generation with LISA, Springer, 2009.

[120] A.B.T. Hopkins and K.D. McDonald-Maier, “A generic on-chip debugger for wireless sensor networks,” Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, IEEE, 338–342, 2006.

[121] F. Hutter et al., “Boosting verification by automatic tuning of decision procedures,” Proceedings of the International Conference on Formal Methods in Computer-Aided Design, IEEE, 27–34, 2007.

[122] K. Hwang and F.A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, 1984.

[123] IBM, 128-Bit Processor Logic Bus—Architecture Specification, Version 4.4, SA-14-2538-02, 2001.

[124] IBM, CoreConnect Bus Architecture, https://www-01.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture, 2010.

[125] IBM, Embedded DRAM Comparison Charts, IBM Microelectronics Presentation, December 2003.

[126] IBM, On-chip Peripheral Bus—Architecture Specification, Version 2.1, SA-14-2528-02, 2001.

[127] P. Ienne and R. Leupers (eds.), Customizable Embedded Processors, Morgan Kaufmann, 2007.

[128] K. Illgner et al., “Programmable DSP platform for digital still cameras,’ Pro­ceedings of the International Conference on Acoustics, Speech, and Signal Process­ing, 4:2235–2238, 1999.

[129] Infineon, TriCore2, Synthesizable Processor Core, 2010.

[130] InSpeed, InSpeed SOC320, Emulex Overview, 2010.

[131] Intel, Intel IOP333 I/O Processor Datasheet, July 2005.

[132] Intel, Intel PXA27x Overview, 2010.

[133] ITRS, International Technology Roadmap for Semiconductors, 2009.

[134] ITRS, ITRS Roadmap Summary, 2006.

[135] M. Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991.

[136] D. Johnson, Handbook of Optical through the Air Communications, Imagineering E-Zine, 2008.

[137] J.R. Jump and S. Lakshmanamurthy, “NETSIM: A general-purpose interconnection network simulator,” International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, H.D. Schwetman et al. (eds.), pp. 121–125, Society for Computer Simulation International, 1993.

[138] P.H.J. Kelly et al., “THEMIS: Component dependence metadata in adaptive parallel applications,” Parallel Processing Letters, 11(4):455–470, 2001.

[139] J.O. Kephart and D.M. Chess, “The vision of autonomic computing,” IEEE Computer, 36(1):41–50, 2003.

[140] D. Keymeulen et al., “Self-adaptive system based on field programmable gate array for extreme temperature electronics,” Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, IEEE, 296–300, 2006.

[141] M. Kistler, M. Perrone and F. Petrini, “Cell multiprocessor communication network: Built for speed,’ IEEE Micro, 26(3):10–23, 2006.

[142] L. Kleinrock, Queueing Systems: Theory, Vol. 1, Theory, John Wiley and Sons, 1975.

[143] F. Kobayashi et al., “Hardware technology for Hitachi M-880 processor group,” Proceedings of the Electronic Components and Technologies Conference, 693–703, 1991.

[144] T. Komuro, S. Kagami and M. Ishikawa, “A dynamically reconfigurable simd processor for a vision chip,” IEEE Journal of Solid-State Circuits, 39(1):265–268, 2004.

[145] C. Kruskal and M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Transactions on Computers, C-32(12):1091–1098, 1983.

[146] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2):203–215, 2007.

[147] K. Kutaragi et al., “A microprocessor with a 128 bit CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder,” IEEE International Solid-State Circuits Conference, IEEE, 256–257, 1999.

[148] S.K. Lam and T. Srikanthan, “Rapid design of area-efficient custom instructions for reconfigurable embedded processing,” Journal of Systems Architecture, 55(1):1–14, 2009.

[149] Lattice Semiconductor, Lattice XP2 Family Handbook, HB1004 Version 02.5, 2010.

[150] D. Lawrie, “Access and alignment of data in an array processor,” IEEE Transactions on Computers, 24(12):1145–1154, 1975.

[151] E.A. Lee, “Embedded software,” Advances in Computers, 56:56–97, 2002.

[152] F. Lee and A. Dolgoeorodov, “Implementation of H.264 encoding algorithms on a software-configurable processor,” Proc. GSPx, 2005.

[153] D. Lee et al., “Accuracy-guaranteed bit-width optimization,” IEEE Transactions on Computer-Aided Design, 25(10):1990–2000, 2006.

[154] J.K.F. Lee and A.J. Smith, “Analysis of branch prediction strategies and branch target buffer design,” IEEE Computer, 17(1):6–22, 1984.

[155] O. Lehtoranta et al., “A parallel MPEG-4 encoder for FPGA based multiprocessor SOC,” Proceedings of the IEEE ISCAS, 2005.

[156] S. Leibson, “NOC, NOC, NOCing on heaven’s door: Beyond MPSOCs,” Electronics Design, Strategy, News, 8 December 2005.

[157] G. Lemieux and D. Lewis, Design of Interconnect Networks for Programmable Logic, Kluwer, 2004.

[158] V. Liguori and K. Wong, “Designing a real-time HDTV 1080p baseline H.264/AVC encoder core,” Proceedings of DesignCon, 2006.

[159] W. Luk et al., “A high-level compilation toolchain for heterogeneous systems,” Proceedings of the IEEE International SOC Conference, 2009, pp. 9–18.

[160] D. Lyonnard, S. Yoo, A. Baghdadi and A.A. Jerraya, “Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip,” Proc. Design Automation Conference, 518–523, IEEE, May 2001.

[161] P. Lysaght and D. Levi, “Of gates and wires,” International Parallel and Distributed Processing Symposium, 2004.

[162] P. Machanick, “SMP-SOC is the answer you get if you ask the right questions,” Proceedings of SAICSIT, SAICSIT, 12–21, 2006.

[163] T. Makimoto, “The hot decade of field programmable technologies,” Proceedings of the IEEE International Conference on Field-Programmable Technology, IEEE, 3–6, 2002.

[164] G. Martin and H. Chang (eds.), Winning the SoC Revolution, Kluwer, 2003.

[165] M.M. Mbaye, N. Blanger, Y. Savaria and S. Pierre, “A novel application-specific instruction-set processor design approach for video processing acceleration,” Journal of VLSI Signal Processing Systems, 47(3):297–315, 2007.

[166] G. McFarland, CMOS Technology Scaling and its Impact on Cache Delay, PhD thesis, Stanford University, 1997.

[167] J. McGregor, Interconnects target SoC design, Microprocessor Report, 2004.

[168] S. McKeever and W. Luk, “Provably-correct hardware compilation tools based on pass separation techniques,” Formal Aspects of Computing, 18(2):120–142, 2006.

[169] B. McNamara, M. Ji and M. Leabman, “Implementing 802.16 SDR using a software-configurable processor,” Proceedings of GSPx, 2005.

[170] C.A. Mead and L.A. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980.

[171] B. Mei et al., “ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,” Field-Programmable Logic and Applications, LNCS 2778, P.Y.K. Cheung, G.A. Constantinides and J.T. de Sousa (eds.), Springer, 2003.

[172] A. Mello, L. Moller, N. Calazans and F. Moraes, “MultiNoC: A multiprocessing system enabled by a network on chip,” Proceedings of Design, Automation and Test in Europe, IEEE, 234–239, 2005.

[173] S. Meninger et al., “Vibration-to-electric energy conversion,” IEEE Transactions of the VLSI Systems, 9(1):64–76, 2001.

[174] Mentor Graphics, Atsana Semiconductor J2211 Product Description, 2010.

[175] Mentor Graphics, Nucleus Operating System, 2010.

[176] Microprocessor Report, Matsushita Integrated Platform, 2005.

[177] Microprocessor Report, MicroBlaze Can Float, 5/17/05-02, 2005.

[178] Microprocessor Report, XAP3 Takes the Stage, 6/13/05-01, 2005.

[179] P. Mishra and N. Dutt (eds.), Processor Description Languages, Applications and Methodologies, Morgan Kaufmann, 2008.

[180] S. Mirzaei, A. Hosangadi and R. Kastner, “FPGA implementation of high speed FIR filters using add and shift method,” Proceedings of ICCD, 2006, pp. 308–313.

[181] A. Molnar et al., “An ultra low power 900 MHz RF transceiver for wireless sensor output,” Proceedings of the Custom Integrated Circuits Conference, IEEE, 2004, pp. 401–404.

[182] A.C. Murray, R.V. Bennett, B. Franke and N. Topham, “Code transformation and instruction set extension,” ACM Transactions on Embedded Computing, 8(4), Article 26, 2009.

[183] MIPS, MIPS 74K Core Product Description, 2010.

[184] NetSilicon, NET+Works for NET+ARM, Hardware Reference Guide, 2000.

[185] NetSilicon, NetSilicon NS9775 Datasheet, Rev. C, January 2005.

[186] NXP, LH7A404, 32-Bit System-on-Chip, Preliminary data sheet, July 2007.

[187] M. Oka and M. Suzuoki, “Designing and programming the Emotion Engine,” IEEE Micro, 19(6):20–28, 1999.

[188] Open Core Protocol International Partners, Open Core Protocol Specification 1.0, OCP-IP Association, Document Version 002, 2001.

[189] OpenCores, Wishbone B4, 2010.

[190] OpenCores, OpenRISC, 2010.

[191] I. Page and W. Luk, “Compiling occam into FPGAs,” FPGAs, W. Moore and W. Luk (eds.), pp. 271–283, Abingdon EE&CS books, 1991.

[192] R. Paschotta, Encyclopedia of Laser Physics and Technology, RP Photonics, 2010.

[193] S. Pasricha and N. Dutt, On-Chip Communication Architectures, Morgan Kaufmann, 2008.

[194] J.H. Patel, “Performance of processor–memory interconnections for multiprocessors,” IEEE Transactions on Computers, 30(10):771–780, 1981.

[195] L.D. Partain, Solar Cells and Their Applications, Wiley, 2004.

[196] O. Pell, “Verification of FPGA layout generators in higher order logic,” Journal of Automated Reasoning, 37(1–2):117–152, 2006.

[197] O. Pell and W. Luk, “Instance-specific design,” Reconfigurable Compuing, S. Hauck and A. DeHon (eds.), pp. 455–474, Morgan Kaufmann, 2008.

[198] P. Pelgrims, T. Tierens and D. Driessens, Evaluation Report OCIDEC-Case, De Nayer Instituut., 2003.

[199] Philips, Nexperia PNX1700 Connected Media Processor, 2007.

[200] M. Porrmann, U. Witkowski and U. Rueckert, “Implementation of self-organizing feature maps in reconfigurable hardware,” FPGA Implementations of Neural Networks, A.R. Omondi and J.C. Rajapakse (eds.), 247–269, Springer, 2006.

[201] E.J. Prinz et al., “Sonos: An embedded 90 nm SONOS flash EEPROM utilizing hot electron injection programming and 2-sided hot hole injection erase,” IEDM Conference Record, 2002.

[202] S. Przybylski, M. Horowitz and J. Hennessy, “Characteristics of performance optimal multi-level cache hierarchies,” Proceedings of the 16th Symposium on Computer Architecture, ACM, 114–121, June 1989.

[203] V.L. Pushparaj et al., “Flexible energy storage devices based on nanocomposite paper,” Proceedings of the National Academy of the USA, 104(34):13574–13577, 2007.

[204] C.V. Ravi, “On the bandwidth and interference in interleaved memory systems,” IEEE Transactions on Computers, 21(8):899–901, 1972.

[205] RFID Journal, http://www.rfidjournal.com.

[206] S. Roundy et al., “Power sources for wireless sensor networks,” Proceedings of the 1st European Workshop on Wireless Sensor Networks, 2004, pp. 1–17.

[207] C. Rowen and S. Leibson, Engineering the Complex SoC, Prentice Hall, 2004.

[208] R.M. Russell, “The CRAY-1 computer system,” Communications of the ACM, 21(1):63–72, 1978.

[209] S. Sane, “The aerodynamics of insect flight,” The Journal of Experimental Biology, 206:4191–4208, 2003.

[210] J. Schmaltz and D. Borrione, “A generic network on chip model,” Theorem Proving in Higher Order Logics, LNCS 3603, J. Hurd and T. Melham (eds.), pp. 310–325, Springer, 2005.

[211] P. Sedcole et al., “Run-time integration of reconfigurable video processing systems,” IEEE Transactions on VLSI Systems, 15(9):1003–1016, 2007.

[212] P. Sedcole and P.Y.K. Cheung, “Parametric yield modelling and simulations of FPGA circuits considering within-die delay variations,” ACM Transactions on Reconfigurable Technology and Systems, 1(2), Article 10, 2008.

[213] S. Seng, W. Luk and P.Y.K. Cheung, “Run-time adaptable flexible instruction processors,” Field Programmable Logic and Applications, LNCS 2438, M. Glesner, P. Zipf and M. Renovell (eds.), pp. 545–555, 2002.

[214] R.A. Shafik, B.H. Al-Hashimi and K. Chakrabarty, “Soft error-aware design optimization of low power and time-constrained embedded systems,” Proceedings of DATE, IEEE, 1462–1467, 2010.

[215] L. Shannon and P. Chow, “SIMPPL: An adaptable SoC framework using a programmable controller IP interface to facilitate design reuse,” IEEE Transactions on VLSI Systems, 15(4):377–390, 2007.

[216] N. Shirazi, W. Luk and P.Y.K. Cheung, “Run-time management of dynamically reconfigurable designs,” Field-Programmable Logic and Applications, LNCS 1482, R.W. Hartenstein and A. Keevallik (eds.), pp. 59–68, Springer, 1998.

[217] M. Shirvaikar and L. Estevez, “Digital camera design with JPEG, MPEG4, MP3 and 802.11 features,” Embedded Systems Conference, 2006.

[218] M.L. Shooman, Reliability of Computer Systems and Networks: Fault Tolerance, Analysis, and Design, Wiley, 2001.

[219] SiliconBlue, iCE65 Ultra Low-Power Mobile FPFA Family, 2.1.1, 2010.

[220] Silicon Hive, Avispa block accelerator, Product Brief, 2003.

[221] A.J. Smith, “Cache evaluation and the impact of workload choice,” Proceedings of the 12th International Symposium on Computer Architecture, pp. 64–73, ACM, 1985.

[222] J.E. Smith, “A study of branch prediction strategies,” Proceedings of the Symposium on Computer Architecture, pp. 135–148, ACM, 1981.

[223] A.J. Smith, “Cache memories,” ACM Computing Surveys, 14(3):473–530, 1982.

[224] A.J. Smith, “Cache evaluation and the impact of workload choice,” Proceed­ings of the International Symposium on Computer Architecture, pp. 64–73, ACM, 1985.

[225] Sonics Inc, Sonics μNetwork Technical Overview, Document Revision 1, 2002.

[226] B. Stackhouse el al. “A 65 nm 2-billion-transistor quad-core Itanium processor,” IEEE Journal of Solid-State Circuits, 44(1):18–31, 2009.

[227] T. Starnes, Programmable Microcomponent Forecast through 2006, Gartner Market Statistics, 2003.

[228] H.S. Stone, High-Performance Computer Architecture, (2nd ed.), AddisonWesley, 1990.

[229] W.D. Strecker, Analysis of the Instruction Execution Rate in Certain Computer Systems, PhD thesis, Carnegie-Mellon University, 1970.

[230] Stretch, “The S6000 family of processors,” Architecture White Paper, 2009.

[231] H.E. Styles and W. Luk, “Exploiting program branch probabilities in hardware compilation,” IEEE Transactions on Computers, 53(1):1408–1419, 2004.

[232] H.E. Styles and W. Luk, “Compilation and management of phase-optimized reconfigurable systems,” Proceedings of the International Conference on Field-Programmable Logic and Applications, IEEE, 311–316, 2005.

[233] T. Sugizaki et al., “Novel multi-bit sonos type flash memory using a high-k charge trapping layer,” IEEE Symposium on VLSI Technology, Digest of Technical Papers, IEEE, 27–28, June 2003.

[234] Sun, “Java Card 3 Platform,” White Paper, 2008.

[235] Sun, OpenSPARC T1 FPGA Implementation, Release 1.6 Update, 2008.

[236] K.W. Susanto, “An integrated formal approach for system on chip,” Proceed­ings of the International Workshop in IP Based Design, 119–123, October 2002.

[237] M. Suzuoki et al., “A microprocessor with a 128-bit CPU, ten floating-point MAC’s, four floating-point dividers, and an MPEG-2 decoder,” IEEE Journal of Solid-State Circuits, 34(11):1608–1618, 1999.

[238] D. Sykes et al., “Plan-directed architectural change for autonomous systems,” Proceedings of the International Workshop on Specification and Verification of Component-Based Systems, 2007, pp. 15–21.

[239] Target Compiler Technologies, The nML Processor Description Language, 2002.

[240] Tensilica, Tensilica Instruction Extension (TIE) Language Reference Manual, 2006.

[241] R. Tessier et al., “A reconfigurable, power-efficient adaptive Viterbi decoder,” IEEE Transactions on VLSI Systems, 13(4):484–488, 2005.

[242] J.E. Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman and Co., 1970.

[243] Texas Instruments, TMS320C6713B, Floating point digital signal processor Datasheet, Rev. B, 2006.

[244] T.J. Todman et al., “Reconfigurable computing: Architectures and design methods,” IEE Proceedings—Computers and Digital Techniques, 152(2):193–207, 2005.

[245] T. Todman, J.G. de, F. Coutinho and W. Luk, “Customisable hardware compilation,” The Journal of Supercomputing, 32(2):119–137, 2005.

[246] R.M. Tomasulo, “An efficient algorithm for exploiting multiple arithmetic units,” IBM Journal of Research and Development, 11(1):25–33, 1967.

[247] J.D. Ullman, Computational Aspects of VLSI, Computer Science Press, 1984.

[248] J. Villarreal, A. Park, W. Najjar and R. Halstead, “Designing modular hardware accelerators in C with ROCCC 2.0,” Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2010.

[249] Virtual Socket Interface Alliance, On-Chip Bus DWG, Virtual Component Interface (VCI) Specification Version 2, OCB 2 2.0, 2001.

[250] W.J. Watson, “The TI ASC: A highly modular and flexible super computer architecture,” Proceedings of the AFIPS, 41(1):221–228, 1972.

[251] B. Wen and K. Boahen, “Active bidirectional coupling in a cochlear chip,” Advances in Neural Information Processing Systems 17, B. Sholkopf and Y. Weiss (eds.), MIT Press, 2006.

[252] N. Whitehead, M. Abadim and G. Necula, “By reason and authority: A system for authorization of proof-carrying code,” Proceedings of the IEEE Computer Security Foundations Workshop, IEEE, 236–250, 2004.

[253] S.J.E. Wilton et al., “A synthesizable datapath-oriented embedded FPGA fabric for silicon debug applications,” ACM Transactions on Reconfigurable Technology and Systems, 1(1), Article 7, 2008.

[254] Wind River, Wind River VxWorks, http://www.windriver.com/products/vxworks, 2010.

[255] R. Wood, “Fly, robot fly,” IEEE Spectrum, 45(3):21–25, 2008.

[256] C.-L. Wu and T.-Y. Feng, “On a class of multistage interconnection networks,” IEEE Transactions on Computers, 29(8):694–702, 1980.

[257] Xelerated, Xelerator X10q Network Processors, Product Brief, 2004.

[258] Xilinx, MicroBlaze Processor Reference Guide, EDK 11.4, 2009.

[259] Xilinx, Microblaze Processor Reference Guide, 2004.

[260] Xilinx, MicroBlaze Soft Processor Core, http://www.xilinx.com/tools/microblaze.htm, 2010.

[261] Xilinx, PowerPC 405 Processor Block Reference Guide, 2003.

[262] Xilinx, Virtex II Datasheet, 2004.

[263] Xilinx, Virtex 4 FPGA User Guide, v2.6, 2008.

[264] Xilinx, Virtex 5 FPGA User Guide, v5.3, 2010.

[265] Xilinx, Virtex-6 Family Overview, v2.2, 2010.

[266] E.M. Yeatman, “Advances in power sources for wireless sensor nodes,” Proceedings of the 1st International Workshop on Body Sensor Networks, 2004.

[267] T.-Y. Yeh and Y.N. Patt, “Alternative implementations of two-level adaptive branch prediction,” Proceedings of the International Symposium on Computer Architecture, ACM, 124–134, May 1992.

[268] T.-Y. Yeh and Y.N. Patt, “Two-level adaptive training branch prediction,” Proceedings of the International Symposium on Microarchitecture, IEEE, 51–61, November 1991.

[269] P. Yianancouras, J.G. Steffan and J. Rose, “Exploration and customization of FPGA-based soft processors,” IEEE Transactions on Computer-Aided Design, 26(2):266–277, 2007.

[270] A.C. Yu, Improvement of Video Coding Efficiency for Multimedia Processing, PhD thesis, Stanford University, 2002.

[271] B. Zhai et al., “A 2.60pJ/inst subthreshold sensor processor for optimal energy efficiency,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, IEEE, 2006, pp. 154–155.

[272] Z. Zhang et al., “AutoPilot: A platform-based ESL synthesis system,” HighLevel Synthesis: From Algorithm to Digital Circuit, P. Coussy and A. Morawiec (eds.), Springer Publishers, 2008.

[273] J. Zufferey and D. Floreano, “Toward 30-gram autonomous indoor aircraft: Vision-based obstacle avoidance and altitude control,” Proceedings of the IEEE International Conference on Robotics and Automation, 2005, pp. 2594–2599.