1

codes and constants

2

register banks

3

INT0 and INT1

4

Carry and 0x0D2

5

Parity = 1 and F0= 1

6

P3.1 and P3.0

7

external memory chips mot used

8

latching the address; middle of S1 and middle of S2

9

Timer 1/Counter; WR and RD

10

two 8 bit timers TL0 and TH0 are used. T1, if set to run in mode 2 then, used for serial bit transmission or reception in case serial mode 1 or 3 used

11

using T1 and T0 as counters in mode 0

12

TF1,TR1,TF0 and TR0 = 0s, IT1, IE1, IT0 and IE0 = 0s for the timers and external interrupts

13

synchronous communication; 1

14

mode 1 serial transmission, receiver disable, TI and RI flags reset

15

2s/(256– TH1) where s means PCON.7 bit and TH1 means pre-load counts which auto reload in case T1 runs in mode 2.

16

ten ; 1

17

EA and ES bits; 1

18

8, placing the codes for the ISR

19

0x0023; less or equal to 8

20

ES; PS = 1 and PX1 = 0

1

1 B; S3; S4; S6; one; 1; 12 MHz

2

move from a direct address to A register; direct addressing.; move from an address pointed by Ri to A register; indirect addressing; move data8 to A register; immediate addressing;

3

E7, E9 and 69

4

internal RAM; 25H;D0H

5

move from 7DH address to DPH; direct

6

increments; address; 1;

7

OR logic; bit; C, OV and AC; OV and resets C.

8

0; subtract without borrow not available

9

0C; 57; OV;1; (C = 0)

10

26; 1

11

ADC, SUBB, MUL and DIV

12

decreases byte at the direct address and jump to a relative address if byte becomes 0; 127; 128

13

8; P1; 21000;

14

jump is within 2048 addresses; will not;

15

call is to a 16-bit code-address; will

16

RET

17

RETI

18

MOVA, #50H—A; no; no; no; no
RL A— A; no; no; no; no
ADD A,10H—A; no; no; no; C, OV and AC
MOVR0, #88H—no; R0=88H; no; no; no
MOV DPTR, #2000—DPH and DPL; no; no; no; no
MOVC A, A+PC—A; no; no; no; no

19

MOV0D0H, #00H—no; PSW; no; no; All, C, AC,
F0, RS1 and OV = 0s, P, F1 and RS0 = 1
MOV R7, #20H— R7; no; no; no; no
SUBB R7, #2—R7; no; no; no; C, OV and AC
MOV 0F0H,R7— no; B; no; no; no
MOVA, #21H—no; A; no; no; no
MUL AB—no; A and B; no; no; OV and C
MOVR6, 0F0H—R6; no; no; no; no
CJNE R6, #31H, 0F0H—R6, no, no, no, no
CLR A—no; A; no; no; no
MUL AB— no; A and B; no; no; OV and C
MOVR6, 0F0H; R6; no; no; no; no
CJNE R6, #00H, 20H— R6, no, no, no, no

20

PUSH 18H;
-
PUSH 1AH;
0x0086; PUSH 1BH;
0x0086; PUSH 1CH;
0x0088; PUSH 1DH;
0x008A; PUSH 1EH;
0x008C; PUSH 1FH;
POP 19H;
POP 1AH;
0x0096H ; POP 1BH;
0x0098H ; POP 1CH;
0x009AH ; POP 1DH;
0x009CH ; POP 1EH;
0x009EH; POP 1EF;

1

1; EA; ET0; 1; 1

2

0x0003;

3

higher priority interrupt; first; return;

4

ISR has executed instruction ‘disable interrupts’

5

instruction finishes or on return from ISR

6

Running program; ISR

7

8051; source of interrupt

8

8051; 8

9

ISR; return; higher priority interrupt service routine cannot preempt a lower priority interrupt under execution till return and thus latency is predictable

10

ISR; higher priority interrupt service routine can preempt a lower priority interrupt under execution

11

4 ms

12

ISR executes once only on edge transition

13

TI; RI; start; ISR instructions

14

(11/9.600) ms

15

timer; external

16

exception or trap condition occurs

17

in 80x86; compulsorily service-routine execution

18

suspension of service-routine execution so that current one finishes

19

service deadline

20

operations; disable interrupts

1

1; FFFFH

2

counts; 256

3

8192

4

1; T0 mode

5

3; 1; TR0; Gate P3.1

6

2; 6; ET0; 1

7

TL0; TH0; baud intervals in UART serial

8

TF0 =1 in case EA and ET0 = 1s

9

ET1; 0

10

higher priority routine taken 50μs

11

can’t

12

compared; running timer-counter

13

output level bit = 1 and output enabled; F000H

14

running timer-counter counts reach 1000H OC interrupt ; 1

15

successive count increment interval; number of overflows per s

16

external interrupt; 2; 00H; TH0

17

periodic interrupts and run of service routine at regular intervals

18

80x96; SWT interrupt enable bit; HSO_time

19

0.01; less than 1

1

needs to be sent control words

2

USART; serial synchronous and asynchronous reception and transmission

3

4; PA, PB, PC

4

programming for; bit; PC

5

5; OBFA, ACKA, IBFA, STBA and INT

6

16; 4

7

decoding the addresses

8

programmable DMA controller

9

bulk transfer of bytes between memory and IO peripheral

10

programmable interrupt controller

11

to register the priorities to resolve the priorities of interrupts at 8-interrupt request (IRQ) pins

12

to register the priorities to resolve the priorities of interrupts at 8-interrupt request (IRQ) pins

13

transferring induced voltages for the data of physical condition; amplifier, signal conditioner and sample-hold

14

generating actions through current or voltage or magnetic field or other changes; current amplifier

15

is nearest 8-bit number to 255 × 1.204/2.048 and 00111111

16

1.024×255/128 V

17

0.008V

18

1.024×255/128 V

19

0.008V

20

serial synchronous communication between integrated circuits; equal interval between serial clock bits

1

two signals; scan; sense

2

4; 4

3

decoder; encoder; more; scan and sense signals required

4

current input; bit; pin; is 1; 0

5

00110000; 00110001; 01000001; 01000010;00100000;

6

Character 0; 1; A; B;

7

p; n; 10 to 16; p; 300 to 220; n

8

four 7-segment displays; port; one ; display gets the port output

9

16

10

3 pixels; green; blue; (RGB); G ; B

11

data; IO control logic; timing control logic and registers

12

input; for mouse; keypad; multi-touch controller based

13

voltage differences

14

keyboard; display;

15

print controller; character font ROM; circular memory buffer; interface ; Centronics

16

11

1

within +127 or −127 of next instruction address; next instruction address to address within next 2048 addresses;0000H; FFFFH

2

0AAH; 0FFH; 0FFH; 0FFH

3

bits b3, b4 and b5 become 1s; others same as before; 28H ;0FH;

4

0; ISR for T0 runs; interrupt; interrupts

5

1; (10000H − F141H) μs; 12

6

decreases; compared; FFH; not equal; RETI; CLR TR0

7

96;TR1 is set ;

8

do not change; any one; not incrementing; return from interrupt

9

edge triggered; level activated; interrupt event flag; 10000101

10

44H; P1; 22H;

11

20; 400μs; 2000μs; 1600μs

12

MOVX; MOV R0; byte at internal RAM address 7EH

13

four; Label; Operation; operands; comments

14

listing; addresses; individual;

15

in-between; wait; independent

16

constant time intervals; synchronise

17

no, no need; DJNZ

18

push PSW first, then A and pops A first and then PSW.

19

If R6 is FFH then next instruction else to instruction labelled from startms, Next instruction is if R7 is FFH then next instruction else to instruction labelled from start,

20

address; processor; executing

1

an array of characters in data memory; 0; 9

2

summation of 20 elements in the variable array; 0; 19

3

Small Device; open; SDCC is; C99; all the projects, workspaces; Visual C++ 6.0/NET debugger; simulator

4

unsigned 8; 8; 32; 64; IEEE 754; int; short, 32;

5

extern

6

pdata; MOVX @R1;

7

P1A5

8

12

9

counts, counts+1; counts +2; 0x10C1B0; 3; 16;

10

7; 0 or 2; 6; 2; 5; single processor communication

11

return type.; arguments

12

arguments; memory model; bank

13

Library; library; library

14

compiler; manager; linker; locator; peephole; simpler

15

SBUF; SBUF; SCON; TI

16

0; 3; 0; 999

17

disable; 0x9F

18

170; 1s; 0s

19

points; functionName function

20

projectName is pointer to a character; 1;

1

multiple tasks

2

Context

3

ready; deleted; running; timeout;

4

time

5

latency; time deadline

6

operating system; tasks; real time; kernel; hardware; application layer; service

7

Operating system

8

higher priority

9

waiting

10

Priorities

11

cooperative scheduling

12

real time interrupts; system timer; timer; regular intervals; real time

13

cannot call

14

timeout; K_TMO

15

sends; a waiting task j receives the signal from the system to start.

16

posts; semaphores

17

posts; message; message

18

timeout; signal; semaphore; message

19

900; semaphore; message, memory buffer management; 16

20

system timer RTX166/167; running; 6–8; 40–46; 650

1

absolute object file

2

assembles code for; host; assembling;

3

it is using host; target

4

8051; programmer; compiling; assembling.

5

present; program; found; simulating

6

write-edit-embed and test

7

MCU; flash memory; program codes in device registers and memory

8

selecting appropriate device

9

put program codes and data in the memory; hex file

10

dissembler

11

creating source file

12

emulates input-output ports and at the device and internal bus; emulates the actions taking place by the circuit functions

13

assignments, functions, +, − (minus sign or subtraction sign), *, /, (. ) and mod. Logical operators are NOT, OR, AND, XOR, SHL (shift left) and SHR (shift right)

14

Intel or Motorola format; address and machine codes; target system; memory

15

programmed; IDE for locating

16

integrated development device; managing and editing project source files; compiling; assembling; linking; locating; debugger; simulator

17

Joint Test Action Group IEEE 1149.1; access port; boundary-scan architecture;. printed circuit boards (PCBs) through the scan of test points at the PCB and;

18

absolute object file

19

for linking library functions; executable

20

loactor

1

simplified instruction set; Harvard

2

byte and bit oriented operations on file register; literal operation/control operations; call/branch operations

3

the 8-bit address of RAM/register in register file

4

bank; accesses of register or memory by 7-bit address

5

0x00; 0x19 or 0x0F

6

ports; data direction registers; ports; port C

7

WDT; set to reset of the processor after watched-time for finishing a task is over

8

0x03; 0x03, STATUS

9

(i) STATUS; STATUS(ii) STATUS; STATUS (iii) BCF; Z

10

MCLR

11

six; EECON1; EECON2; EEDATA

12

0x000; 0x7 F

13

0x0005; 0x07FF

14

selecting the oscillator, enabling WDT, power up timer, brown-out reset, low voltage incircuit serial programming, data EE memory code protection, flash memory write, in-circuit debugger mode and protection of code

15

master synchronous serial; port; master/ slave mode I2 C

16

writing in CCPR2H-CCPR2L 16-bits for the value; TMR1 becomes equal to these 16-bits then special event triggers to reset the TMR1 and start AD conversion

17

8-bit immediate value for the operation

18

four; LP; XT; HS; Resistor/capacitor

19

voltage VDD falling below a; reset

20

capture/compare/PWM

1

16-bit; implicit, direct and immediate but no register

2

mask lower byte and higher byte; pending lower byte and higher byte

3

0x00; 0x17

4

window; extension of 24 B address space for the SFRs

5

Vertical; 512 byte; 00; 1FF;

6

ports; HSO; port pins as per HSO_Command; four pins and 16 input capture time values

7

T1; 16-bit free running counter (FRC); T2; 16-bit event counter

8

peripheral transaction server; access

9

WSR; window is used

10

Interrupt mask register; not masked; enabled;

11

interrupt pending register

12

branching instruction; branch; branch relative

13

0x2080

14

0x00; 0xFF

15

register file; register; bytes

16

a multi-bit sequence; illegal

17

synchronous; UART

18

a branching; fewer bits; branch relative

19

HSO_Time comparison; matching; T1 or T2

20

Zero register; 16 or 8 register; dummy operand; NULL; 0s.

1

ARM; multistage pipelines

2

superscalar

3

fetch; execute; n; n

4

RISC; few; same; single; hardwired circuits

5

communication; contact

6

status; saved program

7

half word

8

supervisory control mode; execution of supervisory control mode routines

9

16-bit; 32; lesser code; convert; 32

10

processor does no wait for writing next byte into a flash after first write

11

four; Slow; Idle; Stop

12

RISC; few; load; 16-word; hardwired; single; one word

13

high; sixteen; r15; r14; r13

14

high; low energy dissipation; LPC2124; AT91ASM9263EJ-S™; ADuC7026; STR720;

15

Exception; exceptional; Undefined_Excpt, PAbort_Excpt, DAbort_Excpt, IRQ_Excpt and FIQ_Excpt; causes interrupt

16

Flash; erased; using write instruction

17

NVIC (nested vector interrupt controller); NVIC; interrupt handlers; supports 8 levels of priority for preempting the low priority tasks by the higher priority tasks; configurable between 1; 240 physical interrupts

18

Catching an exception; exception

19

interrupt handler

20

Throwing an exception; SWI

1

9; IYL; IXL; IXH; ACCB;

2

8-bit; HCMOS; 0

3

negligible

4

four

5

maskable; IRQ; XIRQ; XIRQ; 64 clock cycles ; high priority interrupt

6

CFORC; OC1 register; TCNT

7

CONFIG; ROM; EEPROM, COP, registers

8

DDR

9

8-bit; as operand; offset

10

transmission; reception

11

Index register; queue; address

12

Inherent; PSHX; IX; 16;

13

Capture; −ve; +ve; 0; 1

14

Master; sends

15

0000H; 1000H

16

Out-Compare; OC; TCNT

17

TCNT; input capture; out compare

18

PACNT; counting;

19

real time interrupts; four

20

synchronous; serial bits; accepted