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by M Kumar, Tom Schubert, Erik Seligman
Formal Verification
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Title page
Table of Contents
Copyright
Foreword for “Formal Verification: An Essential Toolkit for Modern VLSI Design”
Acknowledgments
Chapter 1. Formal verification: From dreams to reality
What is FV?
Why This Book?
A Motivating Anecdote
FV: The Next Level of Depth
The Emergence of Practical FV
Challenges in Implementing FV
Amplifying the Power of Formal
Getting the Most Out of This Book
Practical Tips from This Chapter
Further Reading
Chapter 2. Basic formal verification algorithms
Formal Verification (FV) in the Validation Process
Comparing Specifications
Formalizing Operation Definitions
Boolean Algebra Notation
BDDs
Boolean Satisfiability
Chapter Summary
Further Reading
Chapter 3. Introduction to systemverilog assertions
Basic Assertion Concepts
Immediate Assertions
Sequences, Properties, and Concurrent Assertions
Summary
Further Reading
Chapter 4. Formal property verification
What is FPV?
Example for this Chapter: Combination Lock
Bringing Up a Basic FPV Environment
How is FPV Different from Simulation?
Summary
Further Reading
Chapter 5. Effective FPV for design exercise
Example for This Chapter: Traffic Light Controller
Creating a Design Exercise Plan
Setting Up the Design Exercise FPV Environment
Wiggling the Design
Exploring More Interesting Behaviors
Removing Simplifications and Exploring More Behaviors
Summary
Further Reading
Chapter 6. Effective FPV for verification
Deciding on Your FPV Goals
Staging Your FPV Efforts
Example for this Chapter: Simple ALU
Understanding the Design
Creating the FPV Verification Plan
Removing Simplifications and Exploring More Behaviors
Summary
Further Reading
Chapter 7. FPV “Apps” for specific SOC problems
Reusable Protocol Verification
Unreachable Coverage Elimination
Connectivity Verification
Control Register Verification
Post-Silicon Debug
Summary
Further Reading
Chapter 8. Formal equivalence verification
Types of Equivalence to Check
FEV Use Cases
Running FEV
Additional FEV Challenges
Summary
Further Reading
Chapter 9. Formal verification’s greatest bloopers: The danger of false positives
Misuse of the SVA Language
Vacuity Issues
Implicit or Unstated Assumptions
Division of Labor
Summary
Further Reading
Chapter 10. Dealing with complexity
Design State and Associated Complexity
Example for this Chapter: Memory Controller
Observing Complexity Issues
Simple Techniques for Convergence
Helper Assumptions … and Not-So-Helpful Assumptions
Generalizing Analysis Using Free Variables
Abstraction Models for Complexity Reduction
Summary
Further Reading
Chapter 11. Your new FV-aware lifestyle
Uses of FV
Getting Started
Making Your Manager Happy
What Do FVers Really Do?
Summary
Further Reading
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