Home Page Icon
Home Page
Table of Contents for
IBM Redbooks promotions
Close
IBM Redbooks promotions
by Octavian Lascu, Erik Bakker, Hans-Peter Eckam, Parwez Hamid, Rakesh Krishnakumar
IBM z13 Technical Guide
Front cover
Notices
Trademarks
IBM Redbooks promotions
Preface
Authors
Now you can become a published author, too!
Comments welcome
Stay connected to IBM Redbooks
Chapter 1. Introducing the IBM z13
1.1 z13 highlights
1.1.1 Processor and memory
1.1.2 Capacity and performance
1.1.3 I/O subsystem and I/O features
1.1.4 Virtualization
1.1.5 Reliability, availability, and serviceability design
1.2 z13 technical overview
1.2.1 Models
1.2.2 Model upgrade paths
1.2.3 Frames
1.2.4 CPC drawer
1.2.5 I/O connectivity: PCIe and InfiniBand
1.2.6 I/O subsystems
1.2.7 Coupling and Server Time Protocol connectivity
1.2.8 Special-purpose features
1.2.9 Reliability, availability, and serviceability (RAS)
1.3 Hardware Management Consoles (HMCs) and Support Elements (SEs)
1.4 IBM z BladeCenter Extension (zBX) Model 004
1.4.1 Blades
1.4.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
1.5 IBM z Unified Resource Manager
1.6 Operating systems and software
1.6.1 Supported operating systems
1.6.2 IBM compilers
Chapter 2. Central processor complex (CPC) hardware components
2.1 Frames and drawers
2.1.1 A Frame
2.1.2 Z Frame
2.1.3 z13 new rear cover (door) design
2.1.4 I/O drawer and PCIe I/O drawer
2.1.5 Top exit I/O cabling
2.2 CPC drawer
2.2.1 CPC drawer interconnect topology
2.2.2 Oscillator
2.2.3 System control
2.2.4 CPC drawer power
2.3 Single chip modules (SCMs)
2.3.1 Processor unit (PU) chip
2.3.2 Processor unit (core)
2.3.3 PU characterization
2.3.4 Storage control (SC) chip
2.3.5 Cache level structure
2.4 Memory
2.4.1 Memory subsystem topology
2.4.2 Redundant array of independent memory
2.4.3 Memory configurations
2.4.4 Memory upgrades
2.4.5 Drawer replacement and memory
2.4.6 Flexible Memory Option
2.4.7 Pre-planned memory
2.5 Reliability, availability, and serviceability (RAS)
2.5.1 RAS in the CPC memory subsystem
2.5.2 General z13 RAS features
2.6 Connectivity
2.6.1 Redundant I/O interconnect
2.6.2 Enhanced drawer availability (EDA)
2.6.3 CPC drawer upgrade
2.7 Model configurations
2.7.1 Upgrades
2.7.2 Concurrent PU conversions
2.7.3 Model capacity identifier
2.7.4 Model capacity identifier and MSU value
2.7.5 Capacity Backup (CBU)
2.7.6 On/Off Capacity on Demand and CPs
2.8 Power and cooling
2.8.1 Power consumption
2.8.2 High Voltage Direct Current power feature
2.8.3 Internal Battery Feature (IBF)
2.8.4 Power capping and saving
2.8.5 Power estimation tool
2.8.6 Cooling
2.8.7 Radiator Unit
2.8.8 Water-cooling unit
2.9 Summary of z13 structure
Chapter 3. Central processor complex system design
3.1 Overview
3.2 Design highlights
3.3 CPC drawer design
3.3.1 Cache levels and memory structure
3.3.2 CPC drawer interconnect topology
3.4 Processor unit design
3.4.1 Simultaneous multithreading (SMT)
3.4.2 Single-instruction multiple-data (SIMD)
3.4.3 Out-of-order (OOO) execution
3.4.4 Superscalar processor
3.4.5 Compression and cryptography accelerators on a chip
3.4.6 Decimal floating point (DFP) accelerator
3.4.7 IEEE floating point
3.4.8 Processor error detection and recovery
3.4.9 Branch prediction
3.4.10 Wild branch
3.4.11 Translation lookaside buffer (TLB)
3.4.12 Instruction fetching, decoding, and grouping
3.4.13 Extended Translation Facility
3.4.14 Instruction set extensions
3.4.15 Transactional Execution
3.4.16 Runtime Instrumentation
3.5 Processor unit (PU) functions
3.5.1 Overview
3.5.2 Central processors (CPs)
3.5.3 Integrated Facility for Linux (IFL)
3.5.4 Internal Coupling Facility (ICF)
3.5.5 z Systems Integrated Information Processor (zIIP)
3.5.6 System assist processors
3.5.7 Reserved processors
3.5.8 Integrated firmware processor (IFP)
3.5.9 Processor unit assignment
3.5.10 Sparing rules
3.5.11 Increased flexibility with z/VM mode partitions
3.6 Memory design
3.6.1 Overview
3.6.2 Main storage
3.6.3 Expanded storage
3.6.4 Hardware system area (HSA)
3.7 Logical partitioning
3.7.1 Overview
3.7.2 Storage operations
3.7.3 Reserved storage
3.7.4 Logical partition storage granularity
3.7.5 LPAR dynamic storage reconfiguration
3.8 Intelligent Resource Director (IRD)
3.9 Clustering technology
3.9.1 Coupling Facility Control Code
3.9.2 Coupling Thin Interrupts
3.9.3 Dynamic CF dispatching
3.9.4 CFCC and Flash Express use
Chapter 4. Central processor complex I/O system structure
4.1 Introduction to the InfiniBand and PCIe for I/O infrastructure
4.1.1 InfiniBand specifications
4.1.2 PCIe Generation 3
4.2 I/O system overview
4.2.1 Characteristics
4.2.2 Summary of supported I/O features
4.3 I/O drawer
4.4 PCIe I/O drawer
4.5 PCIe I/O drawer and I/O drawer offerings
4.6 Fanouts
4.6.1 PCIe Generation 3 fanout (FC 0173)
4.6.2 HCA2-C fanout (FC 0162)
4.6.3 Integrated Coupling Adapter (FC 0172)
4.6.4 HCA3-O (12x IFB) fanout (FC 0171)
4.6.5 HCA3-O LR (1x IFB) fanout (FC 0170)
4.6.6 Fanout considerations
4.7 I/O features (cards)
4.7.1 I/O feature card ordering information
4.7.2 Physical channel (PCHID) report
4.8 Connectivity
4.8.1 I/O feature support and configuration rules
4.8.2 FICON channels
4.8.3 OSA-Express5S
4.8.4 OSA-Express4S features
4.8.5 OSA-Express for ensemble connectivity
4.8.6 HiperSockets
4.9 Parallel Sysplex connectivity
4.9.1 Coupling links
4.9.2 Migration considerations
4.9.3 Pulse Per Second (PPS) input
4.10 Cryptographic functions
4.10.1 CPACF functions (FC 3863)
4.10.2 Crypto Express5S feature (FC 0890)
4.11 Integrated firmware processor
4.12 Flash Express
4.13 10GbE RoCE Express
4.14 zEDC Express
Chapter 5. Central processor complex channel subsystem
5.1 Channel subsystem
5.1.1 Multiple channel subsystems concept
5.1.2 CSS elements
5.1.3 Multiple subchannel sets
5.1.4 Parallel access volumes and extended address volumes
5.1.5 Logical partition name and identification
5.1.6 Physical channel ID (PCHID)
5.1.7 Channel spanning
5.1.8 Multiple CSSs construct
5.1.9 Adapter ID (AID)
5.1.10 Channel subsystem enhancement for I/O resilience
5.2 I/O configuration management
5.3 Channel subsystem summary
5.4 System-initiated CHPID reconfiguration
5.5 Multipath initial program load
Chapter 6. Cryptography
6.1 Cryptographic synchronous functions
6.2 Cryptographic asynchronous functions
6.2.1 Secure key functions
6.2.2 Additional functions
6.3 CPACF protected key
6.4 PKCS #11 overview
6.4.1 PKCS #11 model
6.4.2 z/OS PKCS #11 implementation
6.4.3 Secure IBM Enterprise PKCS #11 (EP11) Coprocessor
6.5 Cryptographic feature codes
6.6 CP Assist for Cryptographic Function (CPACF)
6.7 Crypto Express5S
6.8 Tasks that are run by PCIe Crypto Express5S
6.8.1 PCIe Crypto Express5S as a CCA coprocessor
6.8.2 PCIe Crypto Express5S as an EP11 coprocessor
6.8.3 PCIe Crypto Express as an accelerator
6.8.4 IBM Common Cryptographic Architecture enhancements
6.9 TKE workstation feature
6.9.1 TKE workstation with Licensed Internal Code 7.0
6.9.2 TKE workstation with Licensed Internal Code 7.1
6.9.3 TKE workstation with Licensed Internal Code 7.2
6.9.4 TKE workstation with Licensed Internal Code 7.3
6.9.5 TKE workstation with Licensed Internal Code 8.0
6.9.6 Logical partition, TKE host, and TKE target
6.9.7 Optional smart card reader
6.9.8 TKE hardware support and migration information
6.10 Cryptographic functions comparison
6.11 Software support
Chapter 7. Software support
7.1 Operating systems summary
7.2 Support by operating system
7.2.1 z/OS
7.2.2 z/VM
7.2.3 z/VSE
7.2.4 z/TPF
7.2.5 Linux on z Systems
7.2.6 z13 function support summary
7.3 Support by function
7.3.1 Single system image
7.3.2 zIIP support
7.3.3 Transactional Execution
7.3.4 Maximum main storage size
7.3.5 Flash Express
7.3.6 zEnterprise Data Compression Express (zEDC)
7.3.7 10GbE RoCE Express
7.3.8 Large page support
7.3.9 Hardware decimal floating point
7.3.10 Up to 85 LPARs
7.3.11 Separate LPAR management of PUs
7.3.12 Dynamic LPAR memory upgrade
7.3.13 LPAR physical capacity limit enforcement
7.3.14 Capacity Provisioning Manager
7.3.15 Dynamic PU add
7.3.16 HiperDispatch
7.3.17 The 63.75-K subchannels
7.3.18 Multiple subchannel sets (MSS)
7.3.19 Fourth subchannel set
7.3.20 IPL from an alternative subchannel set
7.3.21 Modified Indirect Data Address Word (MIDAW) facility
7.3.22 HiperSockets Completion Queue
7.3.23 HiperSockets integration with the intraensemble data network
7.3.24 HiperSockets Virtual Switch Bridge
7.3.25 HiperSockets Multiple Write Facility
7.3.26 HiperSockets IPv6
7.3.27 HiperSockets Layer 2 support
7.3.28 HiperSockets network traffic analyzer for Linux on z Systems
7.3.29 FICON Express16S
7.3.30 FICON Express8S
7.3.31 FICON Express8
7.3.32 z/OS Discovery and Auto-Configuration (zDAC)
7.3.33 High-performance FICON
7.3.34 Request node identification data
7.3.35 32 K subchannels for the FICON Express16S
7.3.36 Extended distance FICON
7.3.37 Platform and name server registration in FICON channel
7.3.38 FICON link incident reporting
7.3.39 FCP provides increased performance
7.3.40 N Port ID Virtualization (NPIV)
7.3.41 OSA-Express5S 10-Gigabit Ethernet LR and SR
7.3.42 OSA-Express5S Gigabit Ethernet LX and SX
7.3.43 OSA-Express5S 1000BASE-T Ethernet
7.3.44 OSA-Express4S 10-Gigabit Ethernet LR and SR
7.3.45 OSA-Express4S Gigabit Ethernet LX and SX
7.3.46 OSA-Express4S 1000BASE-T Ethernet
7.3.47 Open Systems Adapter for IBM zAware
7.3.48 Open Systems Adapter for Ensemble
7.3.49 Intranode management network (INMN)
7.3.50 Intraensemble data network
7.3.51 OSA-Express5S and OSA-Express4S NCP support
7.3.52 Integrated Console Controller
7.3.53 VLAN management enhancements
7.3.54 GARP VLAN Registration Protocol
7.3.55 Inbound workload queuing for OSA-Express5S and OSA-Express4S
7.3.56 Inbound workload queuing for Enterprise Extender
7.3.57 Querying and displaying an OSA configuration
7.3.58 Link aggregation support for z/VM
7.3.59 Multi-VSwitch Link Aggregation
7.3.60 QDIO data connection isolation for z/VM
7.3.61 QDIO interface isolation for z/OS
7.3.62 QDIO optimized latency mode
7.3.63 Large send for IPv6 packets
7.3.64 OSA-Express5S and OSA-Express4S checksum offload
7.3.65 Checksum offload for IPv4and IPv6 packets when in QDIO mode
7.3.66 Adapter interruptions for QDIO
7.3.67 OSA Dynamic LAN idle
7.3.68 OSA Layer 3 virtual MAC for z/OS environments
7.3.69 QDIO Diagnostic Synchronization
7.3.70 Network Traffic Analyzer
7.3.71 Program-directed re-IPL
7.3.72 Coupling over InfiniBand and Integrated Coupling Adapter
7.3.73 Dynamic I/O support for InfiniBand and ICA CHPIDs
7.3.74 Simultaneous multithreading (SMT)
7.3.75 Single Instruction Multiple Data (SIMD)
7.4 Cryptographic support
7.4.1 CP Assist for Cryptographic Function
7.4.2 Crypto Express5S
7.4.3 Web deliverables
7.4.4 z/OS Integrated Cryptographic Service Facility (ICSF) FMIDs
7.4.5 ICSF migration considerations
7.5 GDPS Virtual Appliance
7.6 z/OS migration considerations
7.6.1 General guidelines
7.6.2 Hardware configuration definition
7.6.3 Coupling links
7.6.4 Large page support
7.6.5 Capacity Provisioning Manager
7.6.6 Decimal floating point and z/OS XL C/C++ considerations
7.7 IBM z Advanced Workload Analysis Reporter (zAware)
7.8 Coupling facility and CFCC considerations
7.9 Simultaneous multithreading (SMT)
7.10 Single-instruction multiple-data (SIMD)
7.11 The MIDAW facility
7.11.1 Modified Indirect Data Address Word (MIDAW) technical description
7.11.2 Extended format (EF) data sets
7.11.3 Performance benefits
7.12 IOCP
7.13 Worldwide port name (WWPN) tool
7.14 ICKDSF
7.15 IBM z BladeCenter Extension (zBX) Model 004 software support
7.15.1 IBM blades
7.15.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
7.16 Software licensing
7.16.1 Software licensing considerations
7.16.2 Monthly license charge (MLC) pricing metrics
7.16.3 Advanced Workload License Charges (AWLC)
7.16.4 z Systems International Program License Agreement (IPLA)
7.16.5 zBX licensed software
7.17 References
Chapter 8. System upgrades
8.1 Upgrade types
8.1.1 Overview of upgrade types
8.1.2 Terminology that is related to CoD for z13 systems
8.1.3 Permanent upgrades
8.1.4 Temporary upgrades
8.2 Concurrent upgrades
8.2.1 Model upgrades
8.2.2 Customer Initiated Upgrade facility
8.2.3 Summary of concurrent upgrade functions
8.3 Miscellaneous equipment specification (MES) upgrades
8.3.1 MES upgrade for processors
8.3.2 MES upgrades for memory
8.3.3 MES upgrades for I/O
8.3.4 MES upgrades for the zBX
8.3.5 Summary of plan-ahead features
8.4 Permanent upgrade through the CIU facility
8.4.1 Ordering
8.4.2 Retrieval and activation
8.5 On/Off Capacity on Demand
8.5.1 Overview
8.5.2 Ordering
8.5.3 On/Off CoD testing
8.5.4 Activation and deactivation
8.5.5 Termination
8.5.6 z/OS capacity provisioning
8.6 Capacity for Planned Event (CPE)
8.7 Capacity Backup (CBU)
8.7.1 Ordering
8.7.2 CBU activation and deactivation
8.7.3 Automatic CBU enablement for GDPS
8.8 Nondisruptive upgrades
8.8.1 Components
8.8.2 Concurrent upgrade considerations
8.9 Summary of Capacity on Demand offerings
Chapter 9. Reliability, availability, and serviceability
9.1 The RAS strategy
9.2 Technology change
9.3 Structure change
9.4 Reducing complexity
9.5 Reducing touches
9.6 z13 availability characteristics
9.7 z13 RAS functions
9.7.1 Scheduled outages
9.7.2 Unscheduled outages
9.8 z13 enhanced drawer availability (EDA)
9.8.1 EDA planning considerations
9.8.2 Enhanced drawer availability processing
9.9 z13 Enhanced Driver Maintenance (EDM)
9.10 RAS capability for the HMC and SE
9.11 RAS capability for zBX Mod 004
9.12 Considerations for PowerHA in zBX environment
9.13 IBM z Advanced Workload Analysis Reporter
9.14 RAS capability for Flash Express
Chapter 10. Environmental requirements
10.1 z13 power and cooling
10.1.1 z13 new rear cover design for vectored air output
10.1.2 Power requirements and consumption
10.1.3 Cooling requirements
10.1.4 Internal Battery Feature (IBF)
10.1.5 Emergency power-off switch
10.2 z13 physical specifications
10.3 z13 physical planning
10.3.1 Raised floor or non-raised floor
10.3.2 Top Exit Power feature
10.3.3 Top Exit I/O Cabling feature
10.3.4 Weight distribution plate
10.3.5 Bolt-down kit for raised floor
10.3.6 Nonraised floor frame tie-down kit
10.3.7 Service clearance areas
10.4 Energy management
10.4.1 Power usage
10.4.2 Environmental monitoring
10.4.3 IBM Systems Director Active Energy Manager
10.4.4 Unified Resource Manager: Energy management
10.5 zBX environmental requirements
10.5.1 zBX configurations
10.5.2 zBX power components
10.5.3 zBX cooling
10.5.4 zBX physical specifications
Chapter 11. Hardware Management Console and Support Elements
11.1 Introduction to the HMC and SE
11.2 HMC and SE enhancements and changes
11.2.1 New rack-mounted HMC
11.2.2 New Support Elements
11.2.3 New backup options of HMCs and primary SEs
11.2.4 SE driver support with the HMC driver
11.2.5 HMC feature codes
11.2.6 Tree Style User Interface and Classic Style User Interface
11.3 HMC and SE connectivity
11.3.1 Hardware prerequisite changes
11.3.2 TCP/IP Version 6 on the HMC and SE
11.3.3 Assigning addresses to the HMC and SE
11.4 Remote Support Facility (RSF)
11.4.1 Security characteristics
11.4.2 RSF connections to IBM and Enhanced IBM Service Support System
11.4.3 HMC and SE remote operations
11.5 HMC and SE key capabilities
11.5.1 Central processor complex (CPC) management
11.5.2 Logical partition management
11.5.3 Operating system communication
11.5.4 HMC and SE microcode
11.5.5 Monitoring
11.5.6 Capacity on demand (CoD) support
11.5.7 Features on Demand (FoD) support
11.5.8 Server Time Protocol (STP) support
11.5.9 NTP client and server support on the HMC
11.5.10 Security and user ID management
11.5.11 System Input/Output Configuration Analyzer on the SE and HMC
11.5.12 Automated operations
11.5.13 Cryptographic support
11.5.14 Installation support for z/VM using the HMC
11.6 HMC in an ensemble
11.6.1 Unified Resource Manager
11.6.2 Ensemble definition and management
11.6.3 HMC availability
11.6.4 Considerations for multiple HMCs
11.6.5 HMC browser session to a primary HMC
11.6.6 HMC ensemble topology
Chapter 12. Performance
12.1 LSPR workload suite
12.2 Fundamental components of workload capacity performance
12.2.1 Instruction path length
12.2.2 Instruction complexity
12.2.3 Memory hierarchy and memory nest
12.3 Relative nest intensity
12.4 LSPR workload categories based on relative nest intensity
12.5 Relating production workloads to LSPR workloads
12.6 Workload performance variation
Appendix A. IBM z Advanced Workload Analysis Reporter (IBM zAware)
A.1 Troubleshooting in complex IT environments
A.2 Introducing IBM zAware
A.3 Understanding IBM zAware technology
A.4 IBM zAware prerequisites
12.6.1 Feature on Demand (FoD)
A.5 Configuring and using IBM zAware virtual appliance
Appendix B. Channel options
Appendix C. Flash Express
C.1 Flash Express overview
C.2 Using Flash Express
C.3 Security on Flash Express
Appendix D. GDPS Virtual Appliance
D.1 GDPS overview
D.2 Overview of GDPS Virtual Appliance
D.3 GDPS Virtual Appliance recovery scenarios
Appendix E. RDMA over Converged Ethernet (RoCE) improvements
E.1 Overview
E.2 Hardware
E.3 Software exploitation of SMC-R
Appendix F. IBM zEnterprise Data Compression Express
F.1 Overview
F.2 zEDC Express
F.3 Software support
Appendix G. Native Peripheral Component Interconnect Express (PCIe)
G.1 Design of native PCIe I/O adapter management
G.2 Native PCIe feature plugging rules
G.3 Native PCIe feature definitions
Related publications
IBM Redbooks
Other publications
Online resources
Help from IBM
Back cover
IBM System x Reference Architecture for Hadoop: IBM InfoSphere BigInsights Reference Architecture
Introduction
Business problem and business value
Reference architecture use
Requirements
InfoSphere BigInsights predefined configuration
InfoSphere BigInsights HBase predefined configuration
Deployment considerations
Customizing the predefined configurations
Predefined configuration bill of materials
References
The team who wrote this paper
Now you can become a published author, too!
Stay connected to IBM Redbooks
Notices
Trademarks
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Prev
Previous Chapter
Notices
Next
Next Chapter
Preface
IBM Redbooks promotions
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset