6

Real-time Control: Timers

Chapter Outline

  • Obtain understanding of features in the timers in MCUs 8051,8096 and 68HC11 and their applications for real-time controls
  • Learn programming of timers in assembly and C
  • Learn software timers and real-time clock interrupts
  • Understand the interrupt latency-intervals and timing constraints

If a clock is not there, managing our day-to-day tasks in real time will be impossible. Similarly, a system invariably needs timers. System tasks can be scheduled in real time using the timers.

Timers have a number of applications. A system can be programmed for measuring durations of the events. The system can initiate the actions or a chain of actions at the scheduled instants or sequences. The system can capture the instances of occurrences of events.

Two important resources of MCUs are (i) timers and (ii) real-time clocks (Sections 2.3.8 and 2.3.14, respectively). We learnt the timers in 8051 family MCU in Chapter 3. We will study these in 8051, 8096 and 68 HCl 1 MCUs in detail in this chapter.

6.1 PROGRAMMABLE TIMERS IN THE MCUs

A timer is a counter that receives count-inputs at prefixed regular intervals. A timer is said to timeout or overflow on the next count-input after the maximum counts at the counter. An overflow means a transition from all output bits of the timer = 1s to all bits = 0s on the next count-input. An n-bit counter can count up to 2n inputs. An 8-bit counter can count up to 28 = 256 inputs. A 16-bit counter can count upto 216 = 65,536 inputs.

Count Inputs in a Timer

The pulses at prefixed regular intervals are called clock pulses. An MCU has readily available clock pulses from its internal clock circuit to give the count-inputs. Figure 6.1 shows internal-clock pulses in 8051. Internal clock pulses are the count inputs in timer T0. The figure also shows overflow instance in 16-bit timer mode.

A count input can be at a positive edge or a negative edge—it depends on the counter characteristics.

Figure 6.1 8051 Internal Clock Pulses to Count Inputs of Timer T0 and Its Overflow in 16-Bit Timer Mode

Counter Start

The counting action of a timer can be started by a timer run (count enable) bit. For example, the T0 can run by setting TR0 = 1 by software in 8051. T0 can also be programmed to start when an external input is given for starting the timer as well as the TR0 is set by software.

Example 6.1

Assume that 8051 MCU has 12 MHz X-tal and timer T0 is programmed in mode 1. Mode 1 is mode for operation as 16-bit timer. Assume that T0 is loaded with all bits = 0s. TH0 = 00H and TL0 = 00H. When T0 is started to run by setting bit TR0 = 1, what is the period after which T0 overflows?

 

12 MHz X-tal in 8051 means T0 gets clock pulses internally at the rate of 1 μs when T0 starts the run. A 16-bit timer overflows on the next input after 216 = 65,536 count inputs. T0 will overflow after 216 × 1 μs = 65,536 μs.

Timer Resolution

Resolution is related to the time interval between two successive states of the timer. If a timer receives count inputs in intervals of T, then the resolution is T.

Free-running Counter

A free running counter means a counter that runs freely and never stops once it starts running on resetting the MCU. It gets inputs continuously using clock pulses from the internal clock circuit. An n-bit free running counter overflows after successive intervals of 2n × p × T.

There is no load or reload of free running counter. The counts can only be read and cannot be written. There is no TR timer-run bit. It is unlike the 8051 timers, T0 and T1.

Pre-scaling Factor

Pre-scaling factor is a factor by which the internal clock pulses can be divided before the input to a timer. Figure 6.2 shows a 16-bit timer TCNT in 68HC11 when it is programmed with pre-scaling factor = 1. Division by p extends the interval between each clock pulse p times. The resolution of the timer now equals p × T, where T is the period of clock pulses before pre-scaling. This extends the overflow period p times.

Figure 6.2 A 16-bit Timer TCNT in 68HC11 When it is Programmed with Pre-Scaling Factor=1

Example 6.2

68HC11 has a 16-bit timer called TCNT. TCNT is a counter that runs continuously and is called a free running counter. [It runs freely. It never stops once starts running on resetting the MCU. It does not need any TR bit setting as in 8051.] Assume X-Tal of 8 MHz frequency. Assume that it is programmed to get clock pulses with pre-scaling factor = 1. What is the period after which it overflows? What is its resolution?

 

8 MHz X-tal in 68HC11 means it is programmed to get clock pulses internally in intervals of 0.5 μs when pre-scaling factor = 1. A 16-bit timer will overflow on the next input after 216 = 65,536 count inputs. When p = 1, it overflows after 216 × 0.5 μs = 32,768 μs. The resolution is related to the time interval between each successive state of the timer. Therefore, the resolution is 0.5 μs.

Counter

A timer can also be used as a counter when instead of internal clock pulses, external inputs are given for counting. A counter increments the count value at each count input.

Interrupt From the Counter or Timer and Service by an Interrupt Service Routine

At the timeout (overflow), an interrupt occurs. If the interrupt from a timer is enabled (unmasked), an interrupt service routine (ISR) is executed. A vector address is an internally assigned address to an interrupt from a timer in the given MCU [refer Figure 5.6].

The ISR is at the vector address for the timer interrupts in 8051 [refer Figure 5.6(b)]. The ISR is at the vector address pointed by an address assigned for the timer interrupts in 68HC11. The MCU finds the ISR address by first vectoring from that address.

6.1.1 Programming Features in 8051/8052

Section 3.5.1 described the timers/counters in 8051/8052.

  1. Programming for counting or timing modes: In certain MCUs, a timer can be programmed to give the input from an external source as well as from an internal clock source. For example, 8051 T0 and T1 timer can be programmed in the counter mode by setting TMOD bit 2 and 6, respectively, and in the timer mode by resetting these bits (refer Table 3.10).
  2. Programming for number of bits 8 or 16 in counting and timing mode: In certain MCUs, a timer can be programmed either as an 8-bit or a 16-bit timer. 8051 T0 can be programmed as a 13-bit timer in mode 0, 16-bit timer in mode 1, 8-bit auto-reload timer in mode 2 and two 8-bit timers in mode 3 (refer Table 3.12).
  3. Programming for the timer start and stop: The start of a timer is programmable in certain MCUs, for example, 8051. We set the bit TR0 = 1 for starting timer T0. Prior to the overflow TR0 can be reset = 0 to stop the timer (Table 3.11).

    The timer counting action starts by a count enable (timer run) bit without any external gate input when TMOD bit 3 and 7 are reset in T0 and T1, respectively. For example, by setting only the TR0 = 1 by software, the T0 can run and stop by TR0 = 0 in 8051 when TMOD bit 3 = 0 (Table 3.10).

  4. Programming for timer/counter start by an external gate input: For example, 8051 T0 and T1 timer can be programmed in an external gate input by setting TMOD bit 3 and 7, respectively. T0 can also be programmed to start only when the TR bit = 1, and then an external input is also given for starting the timer. T0 stops if either the external input at the gate pin becomes 0 or TR = 0 (Table 3.10).
  5. Programming for loading a count value at the start: The timer/counter in 8051/52 can be preloaded with an initial count value [refer Section 3.5.1]. This enables a programmable time interval for interrupt on overflow. Let us load the timer, for example, timer T0 or T1 of 8051, with a count value, x0. Let us then start the timer. After (2n − 1 − x0) inputs, all the n bits in the timer will be 1s. After (2n − x0) inputs, the x will become 0 because an n-bit counter can count only 2n inputs. This instance is called overflow instance. The timer thus timeouts and interrupts after the interval = (2n − x0) × T. In certain MCUs like 8051, x0 can be loaded and is programmable.

Example 6.3

An 8-bit timer is programmed to receive internal pulses at the rate of 1 μs. What should be value x preloaded so that it timeouts and generates an overflow interrupt after 25 μs?

 

An 8-bit timer will overflow on the next input after 255. The pre-loaded count value x should be (256 − 25 μs/1 μs) to overflow after 25 μs, as the count-input interval is 1 μs. The initial value of the timer should be 231= E7H.

Example 6.4

What should be the value of x pre-loaded so that in 8051/52 microcontroller the T0 timeouts and generates an overflow interrupt after 100 μs? Write the programming steps. Assume 12 MHz X-tal.

 

  1. Step 1: Program timer 0 for mode 3 (TL0 and TH0 are the 8-bit timers).

  2. Step 2: Because T = 1 μs when 12 MHz X-tal is used, we load (256 − 100) for TL0 overflow after 100 count inputs in 100 μs. Load x = 156 = 9CH using MOVTL0, #9CH.

  3. Step 3: Enable timer 0 overflow interrupt.

  4. Step 4: Run the timer by setting TR0 bit = 1.

Note: The advantage of mode 3 is that now timer 1 frees itself for loading a value for setting serial baud rate.

6. Count value loading at start and then auto-reload: In certain MCUs, x0 as well as its autoreload on an overflow interrupt is programmable. After successive intervals = (2n − x0) × T, the interrupts occur repeatedly. The 8051 mode 2 timers T0 and T1 are programmable for loading at the start and then it auto-reloads after overflow. Timer T2 of 8052 is programmed for the auto-reload of the count value on overflow.

The ISR on interrupt must finish in time interval (2n − x0) × T. The interrupt deadline equals this interval so that the new ISR can run after the first one.

Example 6.5

Send an output = 1 for (216 × 1024) × T second using T2 in 8052 where T = time interval between successive clock inputs. Output = 0 after this period.

Let a 16-bit memory location M2 be cleared and be stored, 0000H. The lower byte stores at a lower memory address in 8051. It means at address M2, the data = 00H. The higher byte stores at higher memory address, it means at M2 + 1 = 00H. Let us use it for counting the number of overflow events, nov. Number of programmed overflows = 216. It means M2 and M2+1 increment after each overflow and become 00H and 00H again after 216 overflows. When we have to send an output for 216 × (1024) × T, Timer 2 is used as a timer with an initial load value of 1024 and starts by sending bit = 1 at the output pin. Now, start the timer. On interrupt from T2 overflow after the time interval = 1024 × T, the ISR executes and increments the nov at M2. Now, subsequent interrupts are programmed to occur at intervals of 1024 × T by auto-reloading. When nov at M2 exceeds 65,535 and becomes equal to 0000H again, the service routine for T2 should send bit = 0 at the output pin and disable further interrupts from T2.

Example 6.6

Write program steps for programming the above using 8051/52 microcontroller with 12 MHz X-tal. T = 1 μs for 12 MHz X-tal with 8052. A motor is required to run for (1024 × 216 μs).

 

Timers T0 and T1 are usable only as 8-bit auto-reload timers (recall mode 2). Therefore, better use 8052. The 8052 has the 16-bit T2 timer with reload capability. Programming steps are as follows:

  1. Program timer 2 for auto-reload (TL2 and TH2 are the SFRs for the 16-bit timer).

  2. MOV 00H and 00H at the memory addresses, M2 and M2 + 1. Set output bit = 1 to start the motor.

  3. 216 − 1024 = FC00H. MOVFCH and MOV00H into TH2 and TL2, respectively.

  4. Enable timer 2 overflow interrupt.

  5. Run timer2.

  6. On each interrupt, the timer T2 auto-reloads. The ISR for T2 should increment the M2 and add 00H with carry if any added at the M2 + 1. (This gives 16-bit addition at M2). If OR operation between M2 and M2 +1 results in 00H, then stop T2, return from the ISR and execute Step 6, else return from ISR for repeating the ISR on T2 overflow interrupt. The OR operation resulting in 0 means the number of overflows = 65,536 has occurred and therefore the desired period is over.

  7. Reset the output bit = 0 to stop the motor.

Note that if we wish to use 8051, T0 and T1 only, the solution is feasible even then.

6.1.2 Programming for Finding the Time Interval Between Two Events

We find the time taken between two events (for example, in one revolution of a motor) or the period for which an input remains 0 or the period for which an input remains 1 as follows:

Application Examples of the Program for Finding Timer intervals

  1. Time interval for one revolution of a motor: Take, for example, a rotating motor. When the motor starts revolving from 0°, an LED-phototransistor pair connects through a T-flip flop to the external pin input and makes it 1. On the first event at 0°, timer 0 starts and we read the timer 0 count value as x1. When the motor completes the revolution to 360°, the LED-phototransistor pair circuit to the external input pin makes the input = 0 on the second event. Then the program stops the timer 0 and read new count value x2 at timer 0 is read. From the two count values and number of timer 0 interrupts, we calculate the time interval in one revolution.
  2. Time interval for which the input becomes 0: Assume an input = 1. A circuit is made such that input is functioning as a gate to start and stop the timer. When the input becomes 0, the external input = 1. On the first event, the timer 0 starts and we read the timer 0 count value as x1. When the input becomes 1, the circuit makes the external pin input = 0 on the second event. This stops the timer 0 and we read the timer 0 new count value as x2. From the two count values and the number of timer 0 interrupts, we can find the time interval between two events.
  3. Time interval for which the input becomes 1 : Assume an input = 0. A circuit is made and when the input becomes 1, the external pin input = 1. On the first event, the timer 0 starts, and reads the timer 0 count value as x1. When the input becomes 0, the circuit makes the external input = 0. This stops the timer 0 and we read the timer 0 new count value as x2. From the two count values at two events along with the number of timer 0 interrupts that have taken place, we can find the time interval between the two events.

Example 6.7

Using a timer, find the period between two events. Assume that the interval between successive clock pulses to timer = 1 μs. Assume that the time interval between the event is small and there is no overflow of the timer. Use instructions for delay.

Let us not use ISR on the external input event.

 

Assume a timer T0. Let 16-bit T0 start by the first event by the external input. Let T0 with initial value = x1. Let 16-bit T0 running timer with count value x2 be read on the second event. We, thus, find the interval = [x2 − x1] × 1 μs. The approach used here is called the delay routine approach.

Programming steps for programming T0 are as follows:

  1. CH = 0 higher byte of x1 in R4.

  2. CL = 0 lower byte of x1 in R3.

  3. C′H = 0 higher byte of x2 in R6.

  4. C′L = 0 lower byte of x2 in R5.

  5. Let T0 mode is set for counting upto 216. Let start and stop counting be done by instruction. Let instruction execute according to the state of the external pin inputs.

  6. Load 0 in the counter (TH0 =0 and TL0 = 0).

  7. Reset TF0 = 0 [Note: Resetting of TF0 ensures that the ISR corresponding to the pending service from the overflow of timer 0 (in some earlier program) does not take place]. The timer does not start, it will start on external input on the first event.

  8. While (external_input = = 0) {}; Wait till the external input becomes 1.

  9. Disable all interrupts and set cH = TH0 and cL = TL0;

  10. Set TR0 (timer/counter T0 run bit = 1)

  11. While (external_input = = 1) {}; wait till the external input becomes 0.

  12. Reset TR0 (timer/counter T0 run bit =0).

  13. C′H = TH0 and C′L = TL0; enable all interrupts.

Steps 9 and 13 disable at the beginning and enable interrupts at the end, respectively. This is because while reading counts in the timer, there should not be any other interrupts. Suppose some ISR from another source startsjust before stopping T0, then the timer reading will be more than the actual. After reading the timer the second time, the interrupts are enabled. Figure 6.3 shows the timing diagram related to various actions while running the program for finding the interval between two events.

Figure 6.3 Timing Diagram Related to Various Actions While Running the Program for Determining the Time Interval Between Two Events (The Interval is Short Such That the Timer Does Not Overflow)

Example 6.8

Using a timer, find the period between two events. Assume the interval between successive clock pulses to timer = 1 μs. Assume that the time interval between the event is small and there is no overflow of the timer. Assume that each event generates a negative going pulse. Assume that the period between the events is small and there is no overflow of the timer. Use ISR for external pin interrupts.

 

The problem is with having to wait for a long time between steps 8 and 13 in Example 6.7. It increases the latency for service of interrupts from other sources.

Instead of using the external port input state for starting and stopping the timer using delay routine, the better approach will be of using external interrupts. Start the timer on external interrupt 0 on event 1 and read x1 and start the timer on second external interrupt 0 and read x2.

The programming steps for programming T0 in a foreground program are as follows:

  1. Program negative edge type for external interrupt 0

  2. Reset n = 0 in R7 (number of interrupts at INT0 = 0)

  3. CH = 0 higher byte of x1 in R4 for

  4. CL = 0 lower byte of x1 in R3

  5. C′H = 0 higher byte of x2 in R6

  6. C′L = 0 lower byte of x2 in R5

  7. Program Timer 0 as timer for counts in 16-bit mode 1

  8. Load 0 in the counter (TH0 = CH and TL0 = CL)

  9. Reset TF0 = 0 [Note: Resetting TF1 ensures that ISR corresponding to pending service from the overflow of timer 1 does not take place.] The timer does not start. The timer will start on INT0 interrupt on the first event.

  10. Enable INT0 interrupts

    The programming steps in an ISR for INT0 interrupt are as follows:

     

  11. If (n = 0) then {Set TR0 (timer/counter T0 run bit = 1), disable interrupts, CH = TH0 and CL = TL0; enable T0 and INT0 interrupts}

  12. If (n = 1) then {Reset TR0 (timer/counter T0 run bit =0), C′H = TH0 and C′L = TL0, disable T0 and INT0 interrupts}

  13. Increase n

  14. Return

Steps 11 and 12 disable at the beginning and enable interrupts at the end during read of the counts. This is because during reading of timer, there should not be any interrupts. Figure 6.4 shows the timing diagram related to various actions during running of the program for finding the interval between two events at external interrupt pin 0.

Figure 6.4 Timing Diagram Related to Various Actions During Program for the Time Interval Between Two Events at External Interrupt Pin 0

6.1.3 Timer Overflow in MCUs

On overflow to 0 there is an interrupt. Overflow also sets a flag (bit) = 1 in order to indicate this overflow as well as to indicate pending execution of ISR. An example is TF0 in case of T0 of 8051. TF0 autoresets flag (bit) = 0 at the start of the execution of ISR for T0. Thus, T0 can again be used for servicing (taking the action) for the next overflow and interrupt as soon as the present ISR starts.

  1. An overflow event indicated by the overflow interrupt is used to initiate an external event using the ISR servicing (taking the action). For example, on the event an output at MCU can be used to stop (or start), for example, a robot-arm movement.
  2. Certain MCUs can also be programmed to issue automatically (without using the ISR instruction) a time-out signal (bit) at an output port, and this output bit can be pre-programmed to be either 0 or 1 or complement of the previous state (refer Section 6.2.2).
  3. The ISR for interrupt on overflow can be used to update a memory location, which saves the number of overflows, for example, M2 in Example 6.6.

Action after Very Short Intervals

Application of ISR on the first instance of overflow is shown in the following subsection:

  1. Use of 8-bit timer overflows: Setting or complementing a port bit after a time interval (action after a delay less than the maximum time interval of one overflow) is shown by the following example:

Output square pulses at a port bit (Successive Toggling after short delay)

Example 6.9

How can we get the pulses at port bit P1.1 using toggling (making 0 when 1 and 1 when 0 is called toggling)? Assume the pulse intervals are 100 μs second using 8-bit T1 in 8051, where T = interval between successive clock pulses to timer = 1 μs and output is 0 for 50 μs intervals and 1 for 50 μs intervals.

 

Timer 1 is used in mode 2 auto-reload as an 8-bit timer in TL1 with auto-reload from TH1 and TH1 is loaded with initial value (28 − 100/2) = 206 = CEH. Start the timer by setting TR1 = 1. On each interrupt from T1 after overflow after each interval of 50 × T, an ISR instruction is used to set P1.1 out-bit = complement of the previous output. Thus, the interval between successive pulses will be 100 μs.

The programming steps in the foreground program are as follows:

  1. We program 8051 Timer 1 in Mode 2, which is an 8-bit timer auto-reload mode.

  2. Load initial load value × in TH1 = CEH. This enables overflow interrupt after every 50 μs.

  3. Reset TF1 = 0 and enable timer 1 interrupts.

  4. Set TR1 (timer run bit = 1).

     

    The programming steps in an ISR on overflow are as follows:

    TR1 need not be again set to 1 as the timer continues running from initial value × = CEH in mode 2 after overflow and TF1 automatically resets on execution of the service routine for the timer in 8051.

     

  5. P1.1 = complement of P1.1.

  6. Return.

Figure 6.5 shows the timing diagram related to various actions during the running of a program for a very short time delay. Programming in assembly and C for a similar problem is given in Chapter 9.

Figure 6.5 Timing Diagram Related to Various Actions in a Program for a Very Short Time Delay

Action After long Intervals

Application of ISR on the nth ISR on the nth overflow is shown in the following subsection:

2. 16-bit timer overflows: When we need long delays, a 16-bit timer is required. Further there may be more than one overflow required because clock inputs are every μs. Setting port bit after a long time interval (action after a delay greater than the maximum time interval of one overflow) is shown by the following example:

Setting port bit after a long time interval (action on nth ISR on nth overflow):

Example 6.10

How can we switch off an LED after 2 s using a 16-bit timer with T = interval between successive clock pulses to timer = 1 μs. Assume an LED is connected to the P1.1 pin and switches on when the port bit = 1 and switches off when the bit = 0 after 2 s.

 

Let x0 be the initial value loaded at the timer start. Let nov = number of overflows after the nth overflow. Up to the first overflow, the 16-bit timer gets (216 − x0) clock inputs. After the first overflow, the timer runs by counting clock inputs from all bits at timer output = 0 to all bits = 1, that is, it overflows after 216 (= 65,536) clock inputs. Between each overflow the timer receives 216 inputs. Since the interval between successive clock pulses to timer = 1 μs, [216 − x0 + (nov − 1) × 216] × 1 μs should be equal to 2 s = 20,00,000 μs.

Let us find nov such that nth overflow the time taken is very close to 2 s = 20,00,000 μs. We find that when nov = 31, (nov − 1) × 216 = 19,66,080 μs. Since 20,00,000 − 19,66,080 = 33,920, x0 = (216 − 33,920) = (65,536 − 33,920) = 31,616.

Let timer 1 be used in mode 1 as a 16-bit timer with an initial load value of 31,616. We first write P1.1 = 1 (switching on the LED connected to it) and start the timer by setting TR1 = 1. On 31st overflow interrupt from T1 on overflow, an ISR instruction is used to set P1.1 out-bit = 0.

LED remains ON for (33,920 + 30 × 216) μs, when on first time overflow, ISR skips an instruction for sending the out-bit = 0, and the LED is not switched off by no change in out-bit at P1.1 = 1. Only on the 31st overflow, the ISR does not skip instruction for out-bit at P1.1 = 0 and switches OFF the LED.

Assume that the timer is programmed without auto-reload capability and is pre-loaded with initial value x0 for the first overflow. During the first ISR, the timer is re-programmed and runs from initial values = 0. The timer therefore counts 216 clock pulses 30 times if every time the timer is re-programmed and runs from initial value = 0. During each run of ISR, we count nov and when nov = 31, switch OFF the LED by resetting P1.1 = 0 and the further interrupts from T1 are disabled. Let number of overflows required for long delay = n.

The programming steps in the foreground program are as follows:

  1. Reset nov = 0 in R7.

  2. n = 31 in R6.

  3. Program Timer 1 Mode 1 (16-bit timer mode).

  4. Load initial load value x0 = 31,616 in timer 1.

  5. P1.1 = 1; LED ON.

  6. Reset TF1 = 0, enable timer 1 interrupts and set TR1 (timer run start bit = 1).

The programming steps in an ISR are as follows:

TR1 need not be again set to 1 as timer continues running after overflow from initial count value = 0 and TF1 automatically resets on execution of the service routine for timer in 8051.

  1. Increase nov.

  2. If nov = n then {P1.1 = 0 LED OFF, TR1 = 0, nov = 0, and disable timer 1 interrupts}.

  3. Return.

Figure 6.6 shows the timing diagram related to various actions during the running of a program for long time delay. Programming in assembly and C for a similar problem is given in Chapter 9.

Figure 6.6 Timing Diagram Related to Various Actions During Program for Long Time Interval

Example 6.11

Using a timer, find the period between two events. Assume the interval between successive clock pulses to timer = 1 μs. Assume the time to be long enough, which may cause timer overflow interrupts.

Assume a timer T0. Let 16-bit T0 start by first event by external input. Let T0 with initial value = xv Let 16-bit T0 running timer with count value x2 read on the second event. We thus find the interval = [x2 − x1] × 1 μs if n′ov is zero (no overflow before the second event) and [216 − x1 + x2 + (n′ov − 1) × 216] if n′ov is greater than zero. When there is an overflow, then the timer counts from x1 to 216 and counts from 0 to x2 after the last overflow. Here n′ov = number of overflows of timer 0 at any instant.

 

The programming steps for programming T0 in the foreground program are as follows:

  1. Reset n′ov = 0 in R7.

  2. CH = 0 higher byte of x1 in R4.

  3. CL = 0 lower byte of x1 in R3.

  4. C′H = 0 higher byte of x2 in R6.

  5. C′L = 0 lower byte of x2 in R5.

  6. Program Timer 0 as timer for counts in 16-bit mode 1 with start and stop by external pin inputs.

  7. Load 0 in the counter (TH0 = CH and TL0 = CL).

  8. Reset TF0 = 0, enable timer 0 interrupts. [Note: Reset of TF0 ensures that ISR corresponding to pending service from overflow of timer 0 does not take place.] The timer does not start. The timer will start on external input on the first event.

  9. Disable interrupts.

  10. While (external_input = = 0) {}; Wait till the external input becomes 1.

  11. Set TR0 (timer/counter T0 run bit = 1), CH = TH0 and CL = TL0; enable timer 0 interrupts}

  12. While (external_input = = 1) {}; Wait till the external input becomes 0.

  13. Reset TR0 (timer/counter T0 run bit = 1), disable timer 0 interrupts, C′H = TH0 and C′L = TL0,

  14. Enable interrupts.

    The programming steps in ISR for T0 overflow are as follows:

     

  15. Increas n′ov.

  16. Return.

Figure 6.7 shows the timing diagram related to various actions during the running of a program for finding the interval between two events.

Example 6.12

Using a timer, find the period between two events. Assume an interval between successive clock pulses to timer = 1 μs. Assume a time long enough, which may cause timer overflow interrupts and the events also cause external input interrupts.

 

While loop for the wait is the delay loop. During that period, the other routine cannot run. Instead of using an external input for starting and stopping the timer, the better approach that wait loop approach in Example 6.11 will be as follows: Start the timer on external interrupt 0 on a negative edge event 1 (1 becoming 0) and read x1 and start the timer on the second external interrupt 0 and read x2.

Figure 6.7 Timing Diagram Related to Various Actions During the Program for Time Interval Between Two Events

The programming steps for programming T0 in the foreground program are as follows:

  1. Program negative edge type external interrupt 0.

  2. Reset nov = 0 in R6 (number of interrupts of T0 overflow = 0).

  3. Reset n = 0 in R5 (number of interrupts at INT0 = 0).

  4. CH = 0 higher byte of x1 in R4.

  5. CL = 0 lower byte of x1 in R3.

  6. C′H = 0 higher byte of x2 in R2.

  7. C′L = 0 lower byte of x2 in R1.

  8. Program Timer 0 as timer for counts in 16-bit mode 1.

  9. Load 0 in the counter (TH0 = 0 and TL0 = 0).

  10. Reset TF0 = 0.

  11. Enable timer 0 interrupts. [Note: Resetting of TF1 ensures that ISR corresponding to pending service from overflow of timer 1 does not take place.] The timer does not start. The timer will start on INT0 interrupt on the first event.

  12. Enable INT0 interrupts.

    The programming steps in ISR for INT0 are as follows:

     

  13. If (n = 0) then {Set TR0 (timer/counter T0 run bit = 1), CH = TH0 and CL = TL0; Increase n}.

  14. If (n = 1) then {Reset TR0 (timer/counter T0 run bit =0), C′H = TH0 and C′L = TL0, disable INT0 and T0 interrupts}.

  15. Increase n.

  16. Return.

    The programming steps in T0 ISR are as follows:

     

  17. Increase n′ov.

  18. Return.

Figure 6.8 shows the timing diagram related to various actions during the running of a program for finding long interval between two events at external interrupt pin 0.

Figure 6.8 Timing Diagram Related to Various Actions During the Program for a Long Time Interval Between Two Events at External Interrupt Pin 0

3. Use ofpre-scaling factor for longer intervals for overflows:

Example 6.13

If pre-scaling factor p = 8 and internal clock inputs are at the rate 1 μs, what is the time interval for the 31st overflow in Example 6.10?

 

The total time for the running then equals (30 × 216 + 33920) × 8 × 1 μs = 16 s when the timer is loaded with initial value = 31,616. Foreground-program programs the PR bits to get p = 8, and ISR is programmed as shown in Example 6.10.

Example 6.14

Open a valve for (16 × 216 + 1024).p.T second, where p is the pre-scaling factor. Assume that the timer mode does not auto-reload the counts.

 

Let a memory address M1 be cleared and set as 0. Let us use it for counting the number of overflow events and suppose that we have to stop the current to the solenoid to close the valve after (16 × 216 + 1024).p.T second. Timer 1 is used as a timer with initial load value (216 − 1024) and open the valve by sending an out-bit = 1, which through the interface circuit drives solenoid current in the coil of the valve. The current in it lets the valve remain open till out-bit = 1. Now, start the timer. On interrupt from T1 after overflow after 1024.p.T, we can increment M1 at the service routine instruction. Now, subsequent interrupts will occur at the intervals = (216).pT. When M1 = 16, the service routine resets the out-bit, closes the valve and disables further interrupts from T1.

Figure 6.9 shows the timing diagram related to various actions during the running of a program for showing application of long time interval delay and using the pre-scaling factor. Programming in assembly and C for the problem is given in Chapter 9.

Figure 6.9 Timing Diagram Related to Various Actions During Program for Showing Application of Long Time Interval Delay and Using a Pre-Scaling Factor

Action After Very Long Intervals

Assume that m and n are two 8-bit numbers. The application of ISR on the (m × n)th ISR on the (m × n)th overflow is shown in the following subsection:

4. Use of number of overflows greater than 255 for very long delays: How do we find the interval between 0 and 1 (action at start and then at the end after a delay greater than the maximum time interval of one overflow and number of required overflows greater than 255)? This can be shown by the following example:

Finding the period between events in case of very long interval between them:

Example 6.15

Using two timers, find the interval between two events Assume that interval between successive clock pulses to timer = 1 μs.

 

Assume timer T1 and negative edge external interrupts at INT0. Consider two external interrupts from two events. Assume number of INT0 interrupts are n and T1 interrupts are nov.

The programming steps for programming T0 and T1 in the foreground program are as follows:

  1. Reset nov lower byte = 0 in R7. Reset n=0 in R4.

  2. Reset nov higher byte = 0 in R6.

  3. CH = 0 higher byte in R3.

  4. CL = 0 lower byte in R2.

  5. C′H = 0 higher byte in R1.

  6. C′L = 0 lower byte in R0.

  7. Program interrupt 0 for input event and for starting the as timer T1 operating in 16-bit mode 1.

  8. Program Timer 1 in mode 1 (16-bit timer mode) and Load 0 in the Timer 1 (TH1 = 0 and TL1 = 0).

  9. Reset TF1 = 0, enable timer 1 interrupts. [Note: Resetting of TF1 ensures that ISR corresponding to pending service from overflow of timer 1 does not take place.]

  10. Reset INTX0 flag = 0, enable INT0 interrupts.

    The programming steps in an ISR for INT0 interrupts are as follows:

     

  11. If (n = 0) then {Set TR1 (timer/counter T1 run bit =1), disable interrupts, CH = TH0 and CL = TL0; enable T0 and INT0 interrupts}.

  12. If (n = 1) then {Reset TR0 (timer/counter T1 run bit =0), C′H = TH0 and C′L = TL0, disable INT0 and T1 interrupts}.

  13. Increase n.

  14. Return.

    The programming steps in T1 ISR for overflow are as follows:

     

  15. Add 01H in R7.

  16. Add 00H with carry in R6.

  17. Return.

Figure 6.10 shows the timing diagram related to various actions during the running of a program for a very long time duration between two events. Programming in assembly in Chapter 9 and C for the problem is given in Chapter 10.

Figure 6.10 Timing Diagram Related to Various Actions During the Program for the Very Long Time Interval and for Finding the Interval Between Two Events

Finding the number of revolutions in a minute in a wheel:

Example 6.16

Using two timers, find the number of revolutions in a minute in a motor. Assume interval between successive clock pulses to timer = 1 μs.

 

Assume two timers T0 and T1. Let 16-bit T0 be used as a counter with initial load value x0 = 0. Consider that the count inputs are from a rotating motor with one count per revolution. Then, counting for a minute will give the number of revolutions in a minute. Let 16-bit T1 be used as a timer with initial load value x1 such that it starts the counter 0 on its start and it stops the counter 0 from counting after 1 m. After 1 m, we can note the count value c at T0 and calculate rpm from c and the total number of overflows of T0. We thus find the revolutions in 1 minute = (c + (n′ov × 216), where n′ov = number of overflows from counter 0 at any instant and k = number of overflows from counter 0 at counter 0 stopping.

Since the interval between successive clock pulses to timer = 1 μs, [216 − x + (n − 1) × 216] × m × 1 μs should be equal to 60 s = 6,00,00,000 μs = (30 × 20,00,000) μs.

Let us calculate n such that the nth overflow, the time taken very close to 2 s = 20,00,000 μs, is over. Let n = number of overflows in T1 at any instant. We find that when n = 31, (n − 1) × 216 = 19,66,080 μs. Since 20,00,000 − 19,66,080 = 33,920, x = (216 − 33,920) = 31,616. Now let us repeat the 2 s delay from n overflows 30 times (m times) to get a total delay of 60 s = 1 m.

The programming steps for programming T0 and T1 in foreground program are as follows:

  1. Reset nov = 0 in R7.

  2. Reset mov = 0 in R6.

  3. Reset nov = 0 in R5.

  4. n = 31 in R4.

  5. m = 30 in R3.

  6. Reset k = 0 in R2.

  7. CH = 0 higher byte in R1.

  8. CL = 0 lower byte in R0.

  9. Program Timer 0 as the counter for counts (one count per revolution of motor) using a count pin and counter operating in 16-bit mode 1.

  10. Load 0 in the counter (TH0 =0 and TL0 = 0).

  11. Program Timer 1 in mode 1 (16-bit timer mode).

  12. Load initial load value x = 31,616 in timer 1.

  13. Load initial value c = 0 in R2 (the number of rotations reset at 0).

  14. Reset TF1 = 0, enable timer 1 interrupts and set TR1 (timer T1 run bit = 1). [Note: Resetting of TF1 ensures that ISR corresponding to pending service from overflow of timer 1 does not take place.]

  15. Reset TF0 = 0, enable timer 0 interrupts and set TR0 (timer/counter T0 run bit = 1).

    The programming steps in T1 ISR are as follows:

     

  16. Increase nov.

  17. If (nov = n and mov < m) then (reset nov = 0; load initial load value x = 31,616 in timer 1 and increase mov).

  18. If (nov = n and mov = m) then (TR0 = 0 (stop counter 0), TR1 = 0 (stop timer 1), disable timer 1 and timer 0 interrupts, save 16-bit value C (means save CH and CL), k = n′ov′, save 8-bit value k, nov = 0, mov = 0, n′ov = 0;).

  19. Return.

    The programming steps in T0 ISR are as follows:

     

  20. Increase nov.

  21. Return.

Number of revolutions in 1 m = = (c + (n′ov × 216). Figure 6.11 shows the timing diagram related to various actions during running of program for very long time delay and finding the number of revolutions of a wheel in one minute. Programming in assembly and C for the problem is given in Chapters 9 and 10.

Figure 6.11 Timing Diagram Related to Various Actions During a Program for a Very Long Time Interval and Finding the Number of Revolutions of a Wheel in 1 Minute

6.1.4 Precession Effects in the Timers

The effects on timer precession are shown by the following example:

Precession effects in the timers:

Example 6.17

A count value is read using an external pin interrupt. (a) How much is the delay in reading if due to the external pin interrupt, the latency for service of timer ISR increases by 0.010 ms, the time for executing the instruction for the disable interrupt before the read is 0.002 ms, the time taken in reading the higher byte is 0.002 ms and the time taken in reading the lower byte is 0.002 ms. (b) How will the delay be in the timer reading if conditional test instructions are also executed and take 0. 004 ms at the start of ISR?

 

  1. Timer will have an increased count value because of interrupt latency and instructions before the read of the lower byte by 0.010 ms + 0.002 ms + 0.002 ms (= 0.014 ms) before the lower byte is read.
  2. Delay in timer reading = 0.014 ms + 0.004 ms = 0.018 ms.

Figure 6.12 shows the effect on precise timings.

Figure 6.12 Effect on Precise Timings

6.1.5 Effects on Interrupt Latencies

Effect on interrupt latency is shown by the following example:

Example 6.18

Consider a timer programming for interrupts on overflow after 65.536 ms and started at instance t0. The interrupts on overflow occur at t0 + 65.536 ms, t0 + 2 × 65.536 ms and so on. Consider an instance t0 + 65 just 0.536 ms before the timer-overflow interrupt. (a) What is the maximum period available for execution of main program of ISRs so that there can be immediate response to timer overflow interrupts? (b) What should be the maximum execution time of the ISR instructions so that overflow interrupt is executed just after its occurrence? Assume that the execution of ISR takes 0.800 ms. (c) What is the increase in latency for time overflow interrupt? (d) What will be effects if other than timer interrupts are given lower priorities?

 

  1. Maximum time available = 65.536 ms as interrupts from overflow are occurring after 65.536 ms. Figure 6.13(a) shows time available for ISR instructions in-between timer overflow interrupts.
  2. The ISR instructions must finish before the instance t0 + 65.536 ms. Since the interrupt occurred at t0 + 65 ms, the execution time for ISR instructions should not exceed 0.536 ms. Figure 6.13(b) shows interrupts by the ISR instructions by a timing diagram.
  3. Increase in interrupt latency for timer overflow interrupt is 0.800 ms - 0.536 ms = 0.264 ms. Action on timer overflow interrupt will be delayed by 0.264 ms. Figure 6.13(c) shows timer overflow interrupt latency increase due to the ISR instructions by a timing diagram.
  4. If other than timer interrupts are given lower priority and then preemption by overflow interrupt occurs and latency of that interrupt remain 0.

Latency of other interrupts increases by time that is equal to execution time of the timer overflow interrupt.

Figure 6.13 (a) Time Available for ISR Instructions in Between the Timer Overflow Interrupts; (b) Interrupts by ISR Instructions of Interrupt Just Before the Timer Overflow Interrupt; (c) Timer Overflow Interrupt Latency Increase Due to the ISR Instructions

6.1.6 Timer Features in 68HC11/12 and Other MCUs for Greater Precession in Timings

  1. No programmability for the timer start and stop: In certain MCUs like 68HC11/12 there is a free-running counter where the timer start cannot be programmed.
  2. No programmability for loading a count value at the start: In certain MCUs, The loading count value x as well as the timer starting and stopping cannot be programmed. Example is free-running counter in 68HC11/12 (Section 6.2). In certain MCUs there is pulse accumulator PACNT, for example, in 68HC11/12 and that is programmable.
  3. No programmability for loading at start and auto-reload of a count value: 68HC11/12 free-running counter is not programmable for loading the counts.
  4. Programmability for count-input intervals and overflows interval by pre-scaling the clock pulses: Assume that p is the factor by which the input clock pulses divide before feeding, as an input to the counter and T, is the time interval of a clock pulse before the pre-scaling circuit [Figures 2.12(a) and 6.1(b)]. A count-input interval becomes p times T. An example is 68HC11. In a certain MCU, the count input intervals (p × T) are fixed and are nonprogrammable. An example is 8051.

    Example 6.19

    Pre-scaling factor p is fixed at 1 in 8051 so that p × T = 1 μs for 12 MHz crystal T = 1 μs.

     

    1. When p is fixed at 8 in 8096 so that p × T = 2 μs for 12 MHz crystal T = 0.25 μs.

    2. In certain MCUs like in 68HC11/12 the p is programmable. The 68HC11 has programmability of p by two programmable bits, called PR0 and PR1.

    Example 6.20

    68HC11 with 8 MHz X-tal has a 16-bit timer TCNT. It is internally prefixed to receive internal pulses at the rate of 0.5 μs. The count inputs can also be given by programming the PR0 and PR1 bits, as 00, 10, 1 and 11 for pre-scaling factor p settings as 1, 4, 8 and 16, respectively.

    1. What should be the value of p so that it timeouts and generates overflow interrupt after 216 × 0.5 μs = 32,768 μs?
    2. What should be value p so that it timeouts and generates overflow interrupt after 216 × 16 × 0.5 μs = 0.534288 s?
    3. What would be the rate at which overflow interrupt occurs when the overflow interrupt is not masked and p is programmed to be equal to 4?
    1. A 16-bit timer will overflow on next input after 65536 count inputs. The p should be 1 to overflow after 216 × 1 × 0.5 μ s = 32768 μs = 32.768 ms.
    2. A 16-bit timer will overflow on next input after 65536 count inputs. The p should be 16 to overflow after 216 × 16 × 0.5 μs = 0.534288 s.
    3. When p=4 and T = 0.5 μs, the overflow interrupt intervals shall be 216 × 4 × 0.5 μs = 0.131072 s. The rate of interrupts will be = (1/0.131) = 7.63 per second.
  5. Capturing count value on external input: Certain MCUs provide for capturing the timer count value into a register on an external input positive edge or negative edge or any edge. The edge for the capture, which of the three, can be programmable. This saves the time taken in execution of instructions to the read count values, in disabling interrupts before the read and enabling interrupts after read [refer Section 6.2.3].
  6. Interrupt on capturing count value on external input: MCUs providing for capturing the timer count-value also provide for input-capture interrupts [refer Section 6.2.3].
  7. Comparing count value in a register with the timer counts: Certain MCUs provide for comparison of the timer count value with a register called out-compare register. When they are equal, an output is generated which can be 1 or 0 or toggling of the previous output. The output on successful comparison, which of the three, can be programmable. This saves the time taken by instructions for calling for execution of instructions of the ISR and then ISR instruction setting (or resetting or complementing) the output bit [refer Section 6.2.2].
  8. Interrupt on comparing count value in a register with the timer counts: MCUs providing for OC interrupt on equality on comparing the timer count value with the value in out-compare register [refer Section 6.2.2].
6.2 FREE-RUNNING COUNTER AND REAL-TIME CONTROL

Sections 6.1.1 to 6.1.3 described the programmable timers that can be programmed to start as well as stop and that can be reset or can be loaded with an initial load value. These timers create problems in the real-time control applications due to effects on precise timings (Section 6.1.4) and interrupt latencies (Section 6.1.5).

Real-time control applications are based on regular period interrupts, like a clock or watch that ticks at regular periods of 1 second. A free-running counter is used in real-time control applications to provide actions at scheduled instances.

A free-running counter is a counter, which (i) does not have a counter stop programmability feature as well as a counter value load programmability feature and (ii) once it starts on power-up of the MCU, it keeps running (incrementing) endlessly even after its overflow. Therefore, a free-running counter keeps a record of the actual time (real time) because there is no latency period for the timer before its next cycle starts after overflow and there is no idle interval in the timer.

Intervals for Timer Overflows

A free-running counter means a counter that is running freely never stops once it starts running on resetting the MCU. It gets inputs continuously using clock pulses from an internal clock circuit. An n-bit free-running counter overflows after successive intervals of 2n × p × T.

Features

A list of features of a free-running counter are as follows:

  1. No programmability for the timer start and stop.
  2. No programmability for loading a count value at the start.
  3. No programmability for count value loading at start and then auto-reload.
  4. Programmability for count input intervals by pre-scaling the clock pulses.

There is no loading or reloading or stopping of a free-running counter. The counts can only be read in a capture register and cannot be written (loaded). There is no TR timer run start bit. It is unlike the 8051 timers T0 and T1. A timer running as a free-running counter is a non-reset, unloadable and non-stoppable timer. It is a valuable feature as it enables real-time control of the actions at various instants.

Analogy with a Watch

A free-running counter is like a moving needle that shows the seconds in a watch or clock. The needle keeps freely incrementing after the elapse of each second. When it reaches a terminal value at the end of a minute, the needle starts from 0 without any latency period in the watch—its cycle starts and continuously increments. A watch or a clock has three free-running needles—the hour needle, minute needle and second needle. These three needles increment continuously after an hour, after a minute and after a second, respectively. A watch is equivalent to the running three free-running counters—one ticking by hourly count inputs, one by inputs every minute and one by every second. Therefore, a watch shows real time and can be used to manage the events in the real time. Similarly, the free-running counter can manage the events in real-time space.

6.2.1 Overflows of Free-Running Counter

The following examples describe the overflows in a free-running counter:

Example 6.21

A 16-bit free-running counter is regularly getting inputs at 1 μs.

  1. What will be the time interval for its successive overflows?
  2. How many overflows will occur in 1 s?
  3. If the counter reads 0000H now, then what will be its reading after 1 s.
  4. If the counter reads F000H now, then what will be its reading after 1 s. How many overflows will now occur in 1 s?

  1. An overflow in a 16-bit counter occurs after 216 inputs. Hence, it will overflow after every 65,536 μs (refer Figure 6.14(a)).

  2. Number ofoverflows in 1 s = Integer part of (106 μs /216 μs) = (106 μs / 65,536 μs) = 15.

  3. When the initial reading is 0000H, after 15 overflows also the counter will read 0000H. After 1 s the reading will be as per the interval between 1 s and the time taken in 15 overflows, which is = [0 + (106 − 216 × 15)] = 16,960d = 4240H. Figure 6.14(a) shows free-running counter overflows and reading in 1 s when there are clock inputs for a count every 1 μs when its initial reading is 0000H at an instance.

  4. When the initial reading is F000H, the first overflow will be quicker and after 15 overflows, the counter will read F000H. After 1 s, the reading should be [F000H + (106 − 65,536× 15)d] = F000H + 4240H = one overflow plus 3240H. Therefore, there will now be a total of 16 overflows. After 1 s, the counter reads 3240H. Figure 6.14(b) shows free-running counter overflows and reading after 1 s when its initial reading is F000H at an instance.

Example 6.22

Intel 8096, when operated and driven by a 12 MHz X-tal, generates the clock outputs for the timers at 4 MHz internally. The 12-Hz clock pulse has the positive rising edge at start and it also has symmetrical intervals for 1s and 0s. The 4-MHz clock output pulse starts with a negative edge and is asymmetrical. It starts with 0 at 0 ns up to (500/3) ns and has 1 from (500/3) ns to 250 ns [refer Figure 6.15(a)]. It thus has a total clock period of T = 0.25 μs. It internally drives after pre-scaling by a fixed factor p = 8. Therefore, the count inputs to the 16-bit timer (a free-running counter) are at intervals of 2 μs.

Figure 6.14 (a) Free-Running Counter Overflows in 1 s and Reading after 1 s when there are Clock Inputs for a Count Every 1 μs and the Initial Reading is 0000H and (b) the Free-Running Counter Overflows in 1 s and the Reading when its Initial Reading is F000H at an Instance

  1. What shall be the time elapsed when its count value at an instant t1 is F0A3H from its last overflow?
  2. What shall be the time elapsed when its count value at an instant t2 is F1A3H assuming that t2 is before the timer overflow?
  3. What shall be the time elapsed between instants t3 and t2, assuming its count value at t3 is 02A3H and t3 instance is after one overflow?
  4. What shall be the time elapsed between instants t4 and t2, assuming its count value at t4 is 11A3H and the t4 instance occurs after four overflows?

Assume that an ISR that executes on the timer overflow continuously updates a memory location to keep track of the number of overflows.

  1. The time elapsed up to the instant from the last overflow will be (F0A3H − 0000H)×2 μs = (15 × 163 + 0 × 162 + 10 × 161 + 3 × 160) × 2 μs.

  2. The time elapsed between two instants t2 and t1 (with no in between overflow) will be (F1A3H − F0A3H). 2 μs = (0100H). 2 μs = (0 × 163 + 1 × 162 + 0 × 161 + 0 × 160) × 2 μs = 512 μs.

  3. The time elapsed between two instants, t2 and the next overflow will be (1 + FFFFH − F1A3H). 2 μs, and t3 and the overflow will be (02A3H − 0000H). 2 μs. Therefore, the timer interval between t3 and t2 = [(1 + FFFFH − F1A3H) + (02A3H − 0000H)]. 2 μs = 1100H × 2 μs = (1 × 163 + 1 × 162 + 0 × 161 + 0 × 160) × 2 μs = 8704 μs.

  4. The time elapsed (a) between two instants, t2 and the next overflow will be (1 + FFFFH − F1A3H). 2 μs, (b) between three more overflows will be 3 × (1 + FFFFH) × 2 μs and (c) the last overflow and t4 will be (11A3H − 0000H) × 2 μs. Therefore, the timer interval between t4 and t2 = [(1 + FFFFH − F1A3H) + (10000H × 3) + (01A3H − 0000H)]×2 μs = 31000H × 2 μs = (3 × 164 + 1 × 163 + 0 × 162 + 0 × 161 + 0 × 160) × 2 μs = 3 × 65,536 × 2 μs + 8192 μs = 401,408 μs = ~0.4 s.

Figure 6.15(b) shows the time elapsed between different instances t1, t2, t3 and t4 of a free-running counter.

Figure 6.15 (a) Clock Pulses Input in 8096 and (b) Time Elapsed Between Different Instances t1, t2, t3 and t4 of a Free-Running Counter

6.2.2 Using an Output-Compare Register Along with a Timer Running as a Free-Running Counter

One of the uses of a clock is that it can be used to raise an alarm at a pre-fixed instance. The real-time shown by the clock continuously compares with a preset value. As soon as the real time shown by the clock equals the preset time value, the alarm is raised.

Similarly, one of the uses of a timer (running as a free-running counter) is that it can be used to raise an interrupt (and also set or reset or toggle an output port-bit in case an MCU-timer feature facilitates that) when the timer count value equals a preset value in an out-compare register associated with the timer. (Figure 2.12(d) shows a free-running counter with an output compare register and its working.)

Output as well as interrupt on equality on comparing count value in a register with the counts in timer: Assume that there is an out-compare register OC2R. MCUs provides for comparison of the timer count value x with OC2R and other out-compare registers. Let OC2R be loaded with a value = xOC2. When x increments up to xOC2, an output is generated, which can be 1 or 0 or toggling of the previous output. It can be programmed which of the three can be used. This saves the time taken by the instructions for calling for the ISR and then the ISR instruction setting (or resetting or complementing) the output bit. MCUs also provide for OC2 interrupt when x becomes equal to xOC2. Figure 6.16 shows the output as well as interrupt on equality on comparing the count value in a register with the timer counts.

Figure 6.16 Output as well as Interrupt on Equality on Comparing the Count Value in a Register with the Timer Counts

A timer running as a free-running counter along with an output compare register enables the start o an event at a prefixed instant or in initiating a chain of events at prefixed instances. The examples fo application of OC outputs and interrupts are as follows:

Example 6.23

A 16-bit free-running counter is regularly getting inputs at 2 μs.

  1. Out-compare 0 register OC2R is loaded with 8000H and out-compare 1 register OC1R is loaded with C000H. What will be the time interval between OC2 output and OC1 output?
  2. What will be the time interval between OC2 interrupt and OC1 interrupt?
  3. OC1 and OC2 outputs are 0 and 1 before the comparison. Out-compare 0 output level (OC2L) is programmed to give logic 1 at a port bit and out-compare 1 output level (OC1L) is programmed to toggle the logic bit. What will be the OC1 and OC2 outputs after equality with a timer of OC2? What will be the OC1 and OC2 outputs after equality with a timer of OC2?

  1. The OC2 output occurs when the timer counts become = 8000H, and the OC1 output occurs when = C000H. The time interval between changes in OC2 output and OC1 output will be equal to the time interval between timer counts on the equalities with OC2R and OC1R = (C000H − 8000H) × 2 μs = 32,768 μs.

  2. The time interval between OC2 interrupt and OC1 interrupt will be the same as the time interval between OC2 output and OC1 output = 32,768 μs.

  3. As OC2L is programmed for 1, the OC2 output will be 1 when OC2 interrupts occur at count = 8000H. As OC1L is programmed for toggling of the output, the OC1 output will be 0 before OC1 output change occurs at count = C000H and 1 after OC1 output change.

Figure 6.17 shows the timings of OC2 and OC1 output changes, interrupts and changes in output levels.

Figure 6.17 Timings of OC2 and OC1 Output Changes, Interrupts and Changes in Output Levels

Suppose, we have to initiate five actions at five distinct instances, using five out-compare registers, OC1R, OC2R, OC3R, OC4R and OC5R (Section 14.5.3), we can compare the five prefixed count values x0 to x4 at these five registers. We program each OC similar to steps explained in Example 6.24. We can control a robot with five degrees of freedom of movements using the five OCs.

Example 6.24

Assume that an MCU has a 16-bit timer (free-running counter) with the count inputs at intervals of 2 μs and has an out-compare register, OC1. Using OC1, how will you move a robotic arm for 16 s?

 

  1. Assume that the clock inputs to a free-running counter are at intervals of 2 μs. Therefore, overflow intervals are 65,536 × 2 μs = 0.131072 s. The number of overflows in 16 s = integer part of 1,60,00,000/131,072 = 122. We can, therefore, write 16 s = (122 × 0.131072 + 0.009216) s. This means that a free-running counter should run for a time interval of 9,216 μs (= 4,608 = 1200H clock inputs) plus 122 overflows (= 122 × 65,536 clock inputs due to increments from 0000H to FFFFH) and then overflow to 0000H. Let us save nov = 0 at memory location M1, n = 122 at a memory location M2 and 16-bit numberx0 = 65,536 − 4,608 = 60,928 = EE00H at memory location M and M + 1.

  2. Let the arm movement start by making out-bit = 1. The timer is supposed to run for interval of 1200H inputs plus after the first overflow, for an interval of overflow n times where n is the integer part of (80,00,000/65,536) = 122 times = 7AH times. Then stop the arm by out-bit = 0 on last overflow.

  3. Assume that timer overflow and OC interrupts are used. They are masked at the beginning of the program. Now three steps are taken: (i) OC2R (out-compare 0 register) is loaded with x0, (ii) out-bit level OC2L which will be used on comparison for equality is set as 1. It will start the arm on equality of counts with x0. (iii) OC2 output and interrupt are enabled.

  4. Let x is the counts in TCNT at any instance. The output bit will become OC2L on OC2 output when count = x0 = EE00H in the counter. When the arm starts on execution of the first OC2 interrupt, then the timer count value = EE00H. After 16 s, the timer count value will be = 0000H because EE00H + 1200H = 0000H, and the value after 122 overflows is also 0000H. The time elapsed will be [4,608 + 122 × 65,536] × 2 μs = 16 s. Therefore, OC2R is loaded with 0000H and OC2L = 0 on the last but one overflow and the second time the OC interrupt is enabled.

  5. After the desired number of overflows, a routine executes on the second time OC interrupt. It stops the arm movement.

The programming steps for programming overflows and out-comparison in the foreground program are as follows:

  1. nov = 00H (number of overflow at start = 0) in M1. (The variable nov is the number of times a timer overflow ISR executes.)

  2. n = 7AH (The n is constant for the number of overflows on which overflow interrupts should execute) saved in M″

  3. x0 higher byte EEH in M.

  4. x0 lower byte 00H in M + 1.

  5. Reset out-bit = 0. Disable OC2 output.

  6. m∝ = 00H byte in M2 (The variable m∝ is the number of times OC ISR executes).

  7. m = 02H byte in M3 (The m is constant for the number of times for which OC interrupts should execute).

  8. Disable OC and TCNT overflow interrupts.

  9. Load 16-bit register OC2R = x0.

  10. Make OC2L = 1 so that when the timer counts equals OC2R, then the out-bit becomes 1 in the first time run of OC2 and the robot’s arm starts moving.

  11. Enable OC2 interrupts.

    The programming steps in an ISR (ISR2) for OC interrupts are as follows:

     

  12. Increase mor. Enable OC2 output [Note that the out-bit becomes = OC2L = 1;]

  13. If (m∝ = 1) then {disable OC interrupt;

    Enable TCNT overflow interrupts; enable interrupts other than OC interrupt;

    }

  14. If (m∝ = m) then {OC2L = 0; disable next OC interrupt disable OC2 output and m∝ = 0). [Note that the out-bit becomes = OC2L = 0;]

  15. Return.

    The programming steps in TCNT overflow ISR (ISR2) for overflow are as follows:

     

  16. Increase nov; Readx; while (x==0) {};

  17. If (nov < n − 1) then {disable OC interrupt;}

  18. If (nov = = n − 1) then {while (x = 0) {}; OC2R = 0000H; Enable OC2 interrupt;}

  19. If (nv == n) then {disable TCNT interrupts; nov = 0}

  20. Return.

Figure 6.18 shows the steps involved in using the OC for moving a robotic arm for 16 s.

Figure 6.18 Different Instances and Actions for Using the OC Interrupts and Timer Overflow Interrupts for Running the Motor of a Robotic Arm for 16 s

6.2.3 Using an Input-Capture Register on an External Input Capturing of Counts at a Timer Running as a Free-Running Counter

Assume that the time at which an event occurred is to be noted by capturing the exact instance or th time interval between two events is to be noted by capturing these instances, and then an input-captur register is used along with a timer running as a free-running counter. Figure 2.12(c) showed the input capture feature.

Let us assume that an event gives an input at a pin IC0 of MCU that can either be as a positive edge o negative edge or toggling of the logic state. It is possible in certain MCUs, 68HC11/12 (Section 14.5.2 that the input pin IC0 event is programmable for defining the capturing instance. The instance can b programmed either as a positive edge or a negative edge or any of the two edge transitions occurring a IC0 pin.

Time Interval Between Two Events

The following example explains an application of provisions for the input-capture mechanism in th MCU to find the time interval for lifting a weight by a weight lifter. Suppose we have to find the tim interval between two pulses as well as a pulse width (period between a positive and the following nega tive edge) then also we program similar to steps explained in Example 6.25.

Example 6.25

Consider an MCU having a capture register, ICi that captures the count value, xi, on the event, when it is programmed to capture the event and generate an input-capture (IC) interrupt. There are 3 captur input pins. The i can be = 1, 2 or 3 in 68HC11. MCU has a timer (TCNT), which is a 16-bit timer (a free-running counter). Assume a pre-scaling factor programmed with count inputs at intervals of 2 μs Using an ICi how can we find the time taken from the start to end by a weightlifter for lifting the load with both hands? Assume that an input port bit gets an edge transition in both the instances (start and end of lifting) from an appropriate interfacing circuit.

 

Figure 6.19 shows the steps involved in using an ICi to find the time taken by the weightlifter in lifting the weight.

  1. ISR3 that executes on the timer overflow continuously updates a memory location M1 to keep track of the number of overflows nov. M1 + 1 is for saving the result number of overflows actually that have taken place till second capture.

  2. ISR4 executes on ICi interrupt and it captures counts into ICiR (ith input-capture register) if the capture is enabled using a bit in a control register.

  3. To begin with the timer overflow and ICi interrupts are masked.

  4. 8 bits at memory location M1 are stored = FFH. M1 = FFH indicates the initial starting condition before initiating the counting of nov′, the number of overflow interrupts in ISR3.

  5. M1 + 1 memory address saves n the number of overflows taken place.

  6. 16-bits at M2 (actually at M2 and M2 + 1, because there is 1 byte at each address) are stored 0000H.

  7. 16-bits at M3 (actually M3 and M3 + 1) are stored 0000H. The M2 and M3 = 0000H and are thus reset to the initial start count values, xi0 and xi1 before the weightlifting starts.

  8. (a) Program the input-capture for any input edge transition (at the start or end of the lifting), (b) unmask (enable) input-capture interrupt; (means enable the execution of ISR4 on interrupt), (c) enable input-capture by ICi and (d) unmask timer overflow interrupt (TOVI).

  9. When ISR3 executes on overflow, (a) if ICi interrupt is enabled, it increments M1 and then enables the next overflow interrupt if M1 does not equal FFH (When M1 = FFH then number of overflows already taken place is 256) and ICi is not masked, else mask the further overflow interrupts.

  10. When ISR4 starts on ICi interrupt, assume the captured value = xi0 in ICiR: (a) If M2 = 0000H, store the ICiR 16-bits at M2 and M2 + 1 and (b) enable the next ICi interrupt.

  11. When ISR4 starts on the next ICi interrupt, the captured value xi1 is taken in ICiR and (a) If M3 equals 0000H, store the ICiR 16-bits at M3 and M3 + 1 and (b) mask the next ICi interrupt and mask timer overflow interrupts.

  12. Store the difference of M3 and M2 at M4 and the total number of timer overflows taken place in M5.

The programming steps for programming overflows and input-capture in a foreground program are as follows:

  1. Save nov − 1 = FFH (number of overflow at start minus 1 in M1. (nov is the number of times the timer overflow ISR is executed.)

  2. n = 0 (number of overflows on which overflow interrupts finally take place before the second capture) in M1 + 1.

  3. x0 higher byte 00H in M2.

  4. x0 lower byte 00H in M2 + 1.

  5. x1 higher byte 00H in M3.

  6. x1 lower byte 00H in M3 + 1.

  7. Disable timer overflow interrupt (TOVI).

  8. Disable TCNT overflow interrupts.

  9. Program the input-capture for any input edge transition (at the start or end of the lifting).

  10. Unmask (enable) input-capture interrupt; (means enable the execution of ISR4 on interrupt).

  11. Enable input-capture by ICi.

  12. If (M2 is not equal to 0000H and M3 is not equal to 0000H) {Find M3 − M2, save the result at M4 and save M1 + 1 byte at M5. M1 = FFH, M2 = 0000H and M3 = 0000H}.

Figure 6.19 Steps Involved in Using the ICi to Find the Time Taken by the Weightlifter in Lifting the Weight

The programming steps in an ISR (ISR4) for ICi interrupts are as follows:

 

13. If (M1 = FFH and M2 = 0000H) {xi0 in M2 and M2 + 1 is stored from ICiR, enable the next ICi interrupt, enable next TOVI interrupt}.

14. If (M1 < FFH and M2 is not equal to 0000H and M3 = 0000H) then {xi1 in M3 and M3 + 1 is stored from ICiR ; Mask next ICi interrupt and mask TOVI interrupts}.

15. Increase M1. [Number of overflows now reset to 0.]

16. Return.

The programming steps in TCNT overflow ISR (ISR3) for overflow are as follows:

 

17. If (ICi interrupt is enabled and M1 < FFH and M2 > 0000H and M3 = 0000H) then {increments M1, enables next overflow interrupt}.

18. If (M1 < FFH) {Save M1 having number of overflow so far taken place at M1 + 1}.

19. Return.

M2 and M3 now have the 16-bit count values, xi0 and xi1. M1 + 1 memory address saves total number of overflows = n. From these values, the time interval can be calculated. Interval ΔT = (M3 − M2). 2 μs if nov = 0, else it equals the time taken between x0 count value and first overflow interrupt plus time taken in nov overflows stored at M1 plus time taken up to xi1 count value after the last overflow. Therefore, ΔT = [{FFFFH + 1− (M2)} + (nov) × 216 + M3] × 2 μs, where M2 and M3 are the 16-bits at M2 and M3, respectively, and (M1) are the 8 bits at M1.

M4 and M4 + 1 have the 16-bit value of ΔT. The initial conditions (M1 = FFH, M2 = 0000H and M3 = 0000H).

Programmed for Actions From More Than One External Inputs

Example 6.26

How do we find the time taken by three racers, for example, in a 100-m race, using three input-capture registers, IC1R, IC2R and IC3R?

 

Capture the starting events of all the three racers and the finishing events of all the three racers.

At the last program step, the gold, silver and bronze medals among them can be decided by the ΔT values from IC1, IC2 and IC3 interrupts by the procedure shown in Example 6.25.

6.2.4 Programming for a Delay Using Out-Compare after an External Input-Capture

An input-capture register running with a free-running counter helps in finding the instance(s) of occurrence of an event (or chain of events). Using the time capture feature, we can initiate an action and then using the out-compare feature, we can initiate another action after a programmed time interval. Let us show this by the following example in which an oven is started after 32 μs from the instance when a switch is pressed. The oven is switched on for 16 s.

Example 6.27

Assume that there is a microwave oven to be started by a switching-on event, and the oven is to be programmed to run for a prefixed interval of 16 s. Write the steps for using the IC1 and OC2 interrupts.

We use start out-compare initiated action(s) for starting and stopping the oven. Out-comparison for 16 s starts after the 16 count inputs in 32 μs from the input-capture event. We load the captured value as the initial reference instance, add this value in the value to be prefixed in OC2R to start and define the number of overflows needed before the oven is switched off. We use both IC1R and OC2R as shown below.

First, recapitulate from Example 6.24. We can use the following steps: (a) Count inputs to the timer should be (16 s/ 2 μs) [= 80,00,000] between two instances, one to start the oven by sending an out-bit = 1 and another to stop the oven after sending the bit = 0. (b) The oven starts on execution of an OC interrupt ISR. It starts after 32 μs from input-capture in IC1R. Let the captured value = x2. The captured value is transferred after adding count inputs = 16 to OC2R interrupt; let the timer count value be x2 + 16 when the out bit becomes 1 and the oven starts. The timer should then overflow n times where n = integer part of (80,00,000/ 65,536) = 122 times = 7AH times before stopping the oven. Overflow after counts between 0000H to FFFFH + 1 results in the same count value. After 16 s, the timer count value should therefore be x2 + 16 + (80,00,000 − 122 × 65,536) = x2 + 4,608 + 16. If x2 + 4,608 + 16 > 65,635, then there will be one more overflow and the timer count value should be x2 + 4608 + 16 − 65,536 before stopping the oven.

 

The programming steps for programming overflows and out-comparison in the foreground program are as follows:

  1. Save nov = FFH (number of overflow at start minus 1 in M1. This indicates the starting initial value when nov is used for number of overflow ISR executed.

  2. n = 0 (number of overflows after which the overflow interrupt is disabled) in M1 + 1.

  3. x0 higher byte 00H in M2.

  4. x0 lower byte 10H in M2 + 1 (x0 is 16-bit value 0010H (=16) used to increment the counts captured on external input. This enables OC2L and OC2 interrupt after 16 × 2 μs from input-capture).

  5. x1 higher byte 12H in M3.

  6. x1 lower byte 00H in M3 + 1 (x1 is 16-bit value 1200H (= 4,608) used to make the next action exactly after 16 s).

  7. x2 higher byte will be in M4.

  8. x2 lower byte in M4 + 1 (x2 is a 16-bit value captured value on external input at IC1 pin).

  9. x highest byte will be in M5.

  10. x highest but 1 byte in M5 + 1.

  11. x lowest but 1 byte will be in M5 + 2.

  12. x highest but 1 byte in M5+2 (x is a 16-bit value in OC2R for the second event after 16 s calculated from x0 + x1 + x2).

  13. Disable TCNT timer overflow interrupt (TOVI), IC1 interrupt, OC interrupt and OC output.

  14. Program the input-capture for any input edge transition (at the action start or end).

  15. n = 7AH (number of overflows on which overflow interrupts should execute) in M″.

  16. Reset out-bit = 0.

  17. m∝ = 00H byte in M″(m∝ is the number of times OC ISR is executed).

  18. m = 02H byte in M‴ (number of times on which OC interrupts should execute).

  19. Make OC2L = 1 so that when the timer counts equals OC2R then the out-bit becomes 1 in the first time run of OC2 and the robot’s arm starts moving.

  20. Unmask (enable) input-capture interrupt; (means enable the execution of ISR4 on interrupt).

  21. Enable input-capture by IC1 and IC1 interrupt.

    The programming steps in an ISR (ISR6) for IC interrupts are as follows:

     

  22. If (nov = FFH) {disable interrupts;

    read x2 in M4

    OC2R = x2 + x0 (Note: OC2R equals x2 plus 16);

    Enable OC2 output and OC interrupt. disable next IC1 interrupt,

    Increase nov (note the number of overflows now reset to 0]

    }.

  23. Return.

    The programming steps in an ISR (ISR7) for OC interrupts are as follows:

     

  24. Increase m∝. [Note that the out-bit becomes = OC2L = 1;]

  25. If (m∝ = 1) then {disable output change on OC2;

    enable all interrupts other than OC2;

    }.

  26. If (m∝ = m) then {disable next OC interrupts, disable output change on OC2; and m∝ = 0). [Note that the out-bit becomes = OC2L = 0;]

  27. Return.

    The programming steps in TCNT overflow ISR (ISR6) for overflow are as follows:

     

  28. Increase nov;

    if (nov = = n) then {

    x = OC2R + x1 (Note: Increment OC2R by 1200H);

    Reset OC2L = 0 (for use after n overflows);}.

  29. If (x < 65,536 or nov = = n + 1) then {Disable TOVI interrupt and nov = 0;

    load x in OC2R and enable OC2 output and interrupt so that out-bit will be OC2L (= 0) on successful

    next comparison of equality of TCNT count value to x (it means x2 + 32 μs after 123rd overflow)

    in OC2R;}.

  30. If (x > 65,536) then (x = x − 65,536; enable TOVI interrupt).

  31. Return.

Figure 6.20 shows the different instances and actions for using the input-capture on external input and then OC interrupts and timer overflow interrupts for running the oven for exactly 16 s.

Figure 6.20 Different Instances and Actions for Using the Input-Capture on External Input and Then OC Interrupts and Timer Overflow Interrupts for Running the Oven for Exactly 16 s

6.3 REAL-TIME CLOCK INTERRUPTS

Interrupts at regular intervals will facilitate scheduling of different system tasks at regular intervals. Real-time is time which once set at the system-start, it is never reset again and which continues to increment and tick at regular intervals till the system is off. All system tasks, follow this time as reference. Suppose, we have to initiate interrupts called real-time interrupts or system clock interrupts or real-time clock interrupts (RTCI) at regular intervals of c × T, where T is the interval at which the clock inputs are being given to a timer running as a free-running counter and c is a constant. Let r be the real time clock input rate factor when the RTCIs are used. Here, T is the clock input period.

Example 6.28

How does real time clock interrupts programmed in 68HC11? RTCI in 68HC11: Figure 6.21 shows RTC in 68HC11. c = r × 213. With 8 MHz X-tal the T = 0.5 μs. Rate r can be programmed to be 1, 2, 4 and 8. 1013 × T = 4096 μs ~ 4 ms. The interval between successive interrupts running of the tasks can be preset to r times 4 or 8 or 16 or 32 ms for 8 MHz X-tal with 68HC11. The pre-scaling factor p using PR0-PRI is set within the first 64-clock periods after power up in 68HC11. This p is applicable for all TOV, OC and IC interrupts. On the other hand, p is set to 1, and r is programmed 1, 2, 4 and 8 for RTCIs. Further, r can be programmed anytime using RT1-RT0 bits, while p is programmed at the power up only.

When two bits RT0 and RT1 are programmed as 00, 10, 01 or 11, then r is set = 1, 2, 4 or 8, respectively. RTIE is real-time clock interrupt enable or mask bit. It is bit 6 in TMASK 2 control register. RTIF is a real-time clock interrupt flag bit. It is bit 6 in TFLAG 2 status register.

There is a separate vector address for the RTC_ISR. RTCI, when generates, initiates execution of RTC ISR. When RTCI occurs, the MCU vectors to vectoring to RTC_ISR address. 68HC11 MCU vectors to FFF0H-FFF1H for fetching the ISR-ADDR higher and lower bytes for the RTCI.

Figure 6.21 Real-Time Clocked Interrupts Feature in 68HC11

Uses of RTCI: RTC_ISR can perform one of the following services:

  1. Step 1: Read a memory location M that can represent the system time at that instance.

    Step 2: Increment M. This updates the system time information.

    Step 3: Enable the next RTC interrupt. (Figure 2.13 showed the use of RTCI ISR for updating the time and number of system ticks from the system-start.)

  2. Perform a system-specific task and enable the next RTC interrupt. Therefore, after successive intervals of c x T, the RTC interrupts are generated. Figure 6.22 shows the RTCI feature for running the system software at regular intervals. RTCOV means overflow of RTC.

    Figure 6.22 Real-Time Clock Interrupt Feature for Running the Software to Initiate and Synchronize the Execution of a Task at Regular Intervals

    Figure 6.23 shows the timing diagram for initiating the N tasks in a sequence every 8.192 ms within N × 8.192 ms.

     

  3. Difference between RTCIs and Out-Compare Interrupts:

A real-time clock interrupt using the timer differs from the interrupts generated by m-bit free-running counter using an output-compare register. RTCI can assumed to interrupt with only one fixed value either value = 2n × r × T and there can be only 4 or 8 specific programmable values of r and the value of n different from m but has a fixed value. Therefore, the rate by which the interrupts occur can be selected at specific values only (for example, 4, 8, 16 or 32 ms). The selection can be any time after the system start. However, if the RTC interrupt feature is not there or if RTC like interrupts are needed at a greater frequency than feasible using RTCIs, then out-compare feature can be used in place of the RTCIs. OCR (out compare register) can be loaded any value between 0000H and FFFFH.

Figure 6.23 Real-Time Clock Interrupt Feature for Running the Software to Initiate and Synchronize the Execution of the NTasks (Task 0, Task 1, … Task (N-1)) at Regular Intervals

We can program interrupts with any value of x and intervals can be set = x × T in case the OC interrupt feature is used. Further, the OC interrupt can also change an output level without the need to run the ISR. Further, real-time clocked interrupts have separate vector address for ISR or the ISR address pointer.

RTCIs are used for interrupts in periods in multiples of a time of the order of ms. The OC feature is used for interrupts in periods in multiples of a time of the order of us.

Example 6.29

(i) What will be the intervals between successive real-time interrupts in 68HC11 with 8 MHz X-tal when p using PR0-PRI is set as 1 within the first 64-clock periods after power up, and r is programmed as 1, 2, 4 and 8? (ii) Assume that the ISR for the RTC interrupt service uses a memory location M with initial value = 64 and decrements M on each successive interrupt. When M = 0, it calls a task j? What are the time intervals after which task j is called successively? Assume r = 1. (iii) What should be the M initial value if a stepper motor is to be moved one step after every 20 ms? (iv) How will you initiate the tasks i, j, k, l at the 28th ms, 56th ms, 84th and 100th ms?

  1. The interval for the interrupts = c × T = 213. T = 8,192 × 0.5 μs = 4.096 ms, when r = 1 and p = 1. The interrupt will occur at intervals of 4.096 ms.
  2. When r = 2, 4 and 8, the periods will be 8.192 ms, 16.384 ms and 0.032768 s.
  3. First, ISR finds M = 64 and it decreases M to 63. Then, it executes after 4.096 ms, as r is programmed as 1. When RTC ISR runs for the 64th time, it finds M = 0 and calls task j. Therefore, task j is called after 64 × 4.096 ms = 0.262144 s.
  4. We can program r = 1 and M = 5 to move the motor by task j every 20 ms. (5 × 4.096 ms = ~ 20 ms.)
  5. The maximum common factor of (28, 56, 84, 100) is 4 ms. Hence, we keep r = 1. ISR RTC can be programmed with four initial values, M. = 7, M. = 14, Mt = 21 and M. = 25.
  1. Real-time clock interrupt differs from the OC interrupt in the following—distinct vector address for its ISR and rate by which the interrupts occur is programmable to specific few select values only. The OC interrupt also sets or resets or toggles the state of a port bit.
  2. Real-time clocked interrupt differs from the overflow interrupt by the following—distinct vector address for its ISR—and can be at tens of millisecond rates by which the interrupts occur, which is programmable to specific few select values only.
  3. For example, the overflow interrupts in 68HC11 can be programmed for p = 1, 4, 8 or 16 times 216. T. The RTC interrupts can be programmed to r = 1, 2, 4 or 8 times 213. r.T. The OC interrupts can be programmed to x × p × t, where x can be anywhere between 0 and 65,535, and p = 1, 4, 8 or 16. The p can be programmed only between the first 64-clock periods after reset or power up, and r can be programmed at any instant in the program.
6.4 OFTWARE TIMERS

Certain MCUs provide software timers. 8096 has four software timers (SWTs). An SWT is a timer, which generates interrupts and execute software (instructions) when the instructions are used for (i) set following bits—software timer (SWT enable) and interrupt-enable command bits and (ii) load the count value in a register for comparing it with the timer/counter. The timing actions are initiated by writing to the register similar to HSO_TIME register. When there is equality on comparison with a count value in a free-running counter or event timer, then the SWT interrupt flag is set in IO status register IOS1. The interrupt generates like an OC interrupt. There is no output level change for external devices control when using an SWT. The ISR instructions can be used for actions similar to the actions initiated on the OC or RTC interrupts.

Figure 6.24 shows the actions of four software timers of 80x96. Program is for actions for initiating Task i, Task j, Task k and Task l at the interrupts from SQT0, SWT1, SWT2 and SWT3 interrupts.

Figure 6.24 Actions of a Software Timer Provided in the 8096 MCU

8096 provides for four software timer bits for four software timers. There are four SWT enable flags SWT.0, SWT.1, SWT.2 and SWT.3 in a register HSO_COMMAND (high speed output command register. The register saves the number of HSO_COMMANDS with HSO_TIME for each command.

  1. HSO_COMMAND lower bits are written 1000, 1001, 1010 and 1011, respectively, for enabling SWT0, SWT1, SWT2 and SWT3, respectively.
  2. HSO_TIME register is loaded with a time/counter value for an SWT. HSO_TIME register is similar to an OC register.
  3. HSO_COMMAND bit 4 is set to enable interrupt on comparison of the counts loaded in HSO_ TIME register. This bit is common for all SWTs as well as other timer interrupts related to comparison of HSO_TIME.
  4. HSO_COMMAND bit 6 is set to use timer 2 and reset to use timer 1. [There are 2 timers in 880x96.] This bit is common for all SWTs as well as other timer 2 or 1 related interrupts after comparison of HSO_TIME.

There are four SWT interrupt (SWTI) status flags. An SWTI flag is set for initiating the interrupts for software timer 0, 1, 2 or 3 (SWT0, SWT1, SWT2 or SWT3), respectively, when the timer shows the counts = HSO_Time for an SWT. Other features are as follows:

  1. When an IOS1.0 or 1 or 2 or 3 bit is set on interrupt on comparison on equality of HSO_TIME with the timer 2 or timer 1 (hardware timers) then an ISR is called to service the SWT interrupt (provided the SWT interrupt is enabled). There is a common vector address 200A–200B for lower and higher bytes of the ISR address pointer. It is common for all the four SWTs. It is similar to the common vector address for serial receive and transmit functions. These flags are reset as soon as IOS1 is read. Therefore, IOS1 flags are first moved to a memory address M in the ISR and then they are used.
  2. There is a common enabling bit (HSO_COMMAND bit 4) for generating all the four SWT interrupts and other timers using HSO_TIME register.
  3. PSW (processor status word) bit 5 is a common SWT interrupt enable for all the four SWTs and timer 2 reset interrupt and analog to digital conversion start. When PSW.5 is set then interrupt enable all bit I must also be set.
  4. INT_PENDING register bit 5 is also common for pending interrupt service for all the four SWTs and timer 2 reset interrupt and analog to digital conversion start.
  5. IOS1 bits 0, 1, 2 and 3 will be set on SWT interrupt SWT0, SWT1, SWT2 and SWT3, respectively. The ISR of the SWT pointed by the vector address will sort this out by finding which IOS1 bits from bit 0 to bit 3 is set.

Using SWT ISR for OC and RTC Interrupts

Software instructions for programming HSO_COMMAND and HSO_TIME and PSW bit 5 are used for SWT interrupts. Software interrupt status flag IOSI 0 or 1 or 2 or 3 can also initiate a specific set of timer using actions.

The SWT_ISR can alternatively initiate RTC interrupts by loading the HSO_TIME with an appropriate value and re-enable interrupts for repeated interrupts like the one from the RTC. For example, SWT_ISR can read count value x from the timer and add x′ = 8,192 and save in HSO_TIME register to generate interrupt after 8,192 count inputs to a free-running counter. By repeatedly loading x + x′ in the HSO_TIME register and re-enabling interrupts, the OCIs functioning as the RTCIs can be generated every 8,192 μs.

SWT_ISR for RTC or OCI like ISRs can alternatively perform multiple applications, one of the following services:

  1. Read a memory location M that can represent the system time at that instance and increment M. This updates the system time information. Then it enables the next SWT interrupt.
  2. Perform a system-specific task and enable the next SWT interrupt. Therefore, after successive intervals of c × T, the SWT interrupts are generated.

SWT ISR can be used to generate RTCIs as follows:

  1. Read a memory address M.
  2. Increments system time at M.
  3. Update the system (time) clock information at a memory location(s).
  4. Enable the next real-time system time out-compare interrupt.
  5. Enable real-time out-compare for the next time.

Therefore, after successive intervals of c × T, the SWT interrupts will be perpetually generated following are differences with other interrupts related to the timers.

  1. Difference between the real-time clock interrupts, SWT and out-compare interrupts: Software timer interrupt(s) differs from the out-compare interrupt by the following: Distinct vector address(es) and initiation of running of a user-specific task. An SWT interrupt initiates an ISR only, while an OC interrupt initiates an ISR as well as it sets or resets or toggles an out-bit (called high speed output in 80x96) for an external devices control.
  2. Difference between timer overflow interrupts and SWT ISR using SWT interrupts: Software timer interrupt (SWTI) differs from the overflow-interrupt by the following: Distinct vector address, initiation of an ISR and a user-specific task after the equality of the specific count value x0 is continuously compared with the count value in a specific timer. The overflow interrupt thus occurs only after 216 × p × T where p is fixed (80x96) or programmed within specific 64-clock periods (68HC11). SWTI is when the timer shows the count value = x′ and the x′ can be defined for any instant, and SWTs can also be defined for interrupts in quick succession.
  3. Difference between RTCIs and OC ISR using SWT interrupts: Software timer interrupt(s) differs from the RTC interrupt by the following: Distinct vector address, initiation of an ISR. The RTC interrupt occurs only after r.213.p.T where p is fixed or programmed within specific 64-clock periods and r is programmed at any instant to one of the four specific values. SWT interrupt is when the timer shows the count value = x and x can be defined at any instant in any value between 0 and 65,536.
6.5 INTERRUPT INTERVAL AND DENSITY CONSTRAINTS

Interrupt latency can be defined as the interval between the occurrence of the interrupt event and the start of the interrupt service for that event (refer Section 5.4).

6.5.1 Interrupt Service Latency

Latency of Presently Highest Priority Interrupting Source

Assume that an ISR, ISRL is running. An interrupting source of highest priority (presently) interrupts. The service by ISRH becomes pending. The latency longest period TL for starting the ISRH is dependent on the following factors:

  1. Presently running instruction must finish: Longest instruction execution period, Tinst, when an interrupt occurs to a foreground program (or routine). This is because on occurrence of an interrupt event, the servicing actions will initiate only after finishing the instruction currently under execution at ISRL. A long instruction example is the division instruction.
  2. Critical set of instructions must finish: The period, Tenwait, during which the ISRL remains disabled and waits for enabling of the interrupts. This enables the ISRL preemption by higher priority interrupts. [A set of codes before execution of which interrupts are disabled and enabled after their execution is called critical set of codes. This is because no other interrupt can execute during that period.]

    Example 6.30

    Instructions for reading a free-running counter after input-capture are in a critical set of codes. Otherwise, a free-running counter will increment or change its count value if there is an interrupt by any source, and reading of the counts will not be correct.

     

  3. Ending action and initial actions must finish: The period of initial actions Tend. Tend is the time taken in reassigning priorities, re-enabling and retrieving the stack when the ISRl execution ends. The period of initial actions Tinitial like disabling of the other interrupts and saving the CPU registers onto the stack when the ISRH execution starts.

Therefore, latency is T + T + T.

Figure 6.25 shows the critical instructions region effect on interrupt latency for a highest priority interrupt.

Figure 6.25 Effects on Interrupt Latency Due to the Long Instruction and the Delay Due to a Critical Region in the Running ISR

8051,80x96 and 68HC11 MCUs

Critical region disabling of interrupts is needed in case of 8051, 80x96 and not in 68HC11. The 68HC11 automatically disables the interrupt system when an ISR starts executing and automatically enables the interrupt system when there is return from the ISR.

Latency of Higher Priority Interrupting Source When Other Higher Priority Interrupts Also Pending Service

Assume that an ISR, ISRL, is running. An interrupting source of higher priority (presently) H2 interrupts and service by ISRH2 becomes pending. At this instance other higher priority interrupt service ISRH1 is also pending and this interrupt has a higher priority H1 than H2. The services by ISRH1 and ISRH1 become pending at t of that instance.

The worst case latency period will be the sum of the Tinst + Timsal + Tend + TH, where TH is the time of initializing, execution and ending of each of the higher than the present priority interrupt that requires the service.

Figure 5.11 showed an example of latency calculation for 80x96 or 8051. MCUs at which a running ISR can be pre-empted by a higher priority ISR. Figure 5.12 showed another example of latency calculation for 68HC11 MCUs at which a running ISR cannot be pre-empted by higher priority ISR and that can run after the return. Figure 6.25 shows the effects on interrupt latency because of the long instruction and the delay because of critical instructions in the running ISR. TH = (t′ − t) and worst case TH = (t′ − t0).

6.5.2 Examples of Interrupt Service Latency Calculation

The following examples show how we can calculate interrupt service latency:

Example 6.31

A foreground program executes a long instruction of 20.5 μs duration when the interrupt event occurs. The initial actions, before the execution of the task-related instructions starts, take 6 μs. (i) What is the latency period? (ii) What would have been the period if a short 2 μs instruction is executing at the event instance?

 

  1. Latent period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR. Therefore, TL is equal to 20.5 μs + 6 μs = 26.5 μs.

  2. Latent period TL is the interval between the instance when an event occurs and when the servicing task starts by the ISR. Therefore, TL is equal to 2 μs + 6 μs = 8 μs.

Example 6.32

A service routine ISRL is executing an instruction, which takes 3 μs when the interrupt event occurs. The longest instruction in ISRL can, however, take 20.5 μs. The initial terminating actions, before the execution of the task-related instructions starts, take 10.25 μs before switching to the new routine ISRH and the initial actions, before the execution of the task-elated instructions in ISRH starts; take 8.25 μs.

  1. What is the latency period if the new service routine ISRH is called instantaneously, as feasible in 8051 or 80x96 when the new routine has higher priority? (Refer Figure 5.11. ISR1, preempting the currently executing ISR3. Pre-empting means the starting of higher priority ISR by suspending the presently executing ISR.)
  2. What is the latency period if the present service routine ISRL has a critical region of codes which take duration of 24 μs. The ISRL disables the interrupts on entering and enables on exiting the region and then a new service routine is called instantaneously, as in 8051 or 80x96? [8051 or 80x96 provisions for running ISRH any time after an ISRL finishes, provided the interrupt to ISRh has been enabled earlier.]
  3. What is the latency period if the new service routine ISRH cannot start instantaneously but only at the end of the present routine ISRL as in 68HC11? [68HC11 provisions for running ISRH only after ISRL finishes.]

Assume that the present routine ISRL takes total 60 μs to execute all its instructions. Assume that initial terminating actions, before the execution of the task-related instructions starts, take 0 μs before switching to the new routine and the initial actions, before the execution of the task-related instructions starts, take 1 μs.

  1. Latent period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR. Therefore, TL is equal to 3 μs + 10.25 μs + 8.25 μs = 21.5 μs. (= Tinst + Tend + Tinitial). In the worst case, latency will be 17.5 μs extra as the longest instruction can take 20.5 μs instead of 3 μs.

  2. Latent period TL is the interval between instants when an event occurs and when the servicing task starts by the ISRH delays by the duration of the critical instructions region. Therefore, TL is equal to 21.5 μs + 24 μs (= Tinst + Tend + Tinitial + Tenwait) when Tinst = 3 μs. Worst case = 24 μs + 17.5 μs = 41.5 μs extra over 21.5 μs when Tinst = 20.5 μs.

  3. Latent period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR delays by the duration of the presently running ISR duration in 68HC11. Therefore, TL is equal to 0 μs + 1 μs + 60 μs = 61 μs.

68HC11 MCU

Example 6.33

A service routine ISRL is executing an instruction of 3 ms when the interrupt event occurs. (i) What is the worst case latency period for ISRH on an interrupt of priority H when three other interrupts may be pending, highest priority, second highest priority and third highest priority, which can take 80 ms, 40 ms and 100 ms, respectively, and if the new service routine cannot start instantaneously but only at the end of the present routine as in 68HC11? Assume that the present routine takes 60 ms. (ii) What is the latency for the highest priority routine? (iii) What is the latency for the second highest priority routine? (iv) What is the latency for the highest but two priority routines?

 

Assume that the initial terminating actions, before the execution of the task-related instructions starts, take 0 μs before switching to the new routine, and the initial actions, before the execution of the task- related instructions starts, take 1 μs. Refer Figure 5.6. ISR1 does not pre-empt the currently executing ISR3. ISR 1 starts running only on return at the end of the ISR3).

  1. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISRH delays = the duration of the presently running ISR duration plus the execution times for the higher than the present priority interrupts. Therefore, TL for the current routine equals to 0 μs + 1 μs + 60 μs + (0 μs + 1 μs + 80 μs) + (0 μs + 1 μs + 40 μs) + (0 μs + 1 μs + 100 μs) = (61 + 81 + 41 + 101) μs = 284 μs.

  2. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR delays by the duration of the presently running ISR duration. Therefore, TL for the highest priority service when the current routine equals to 0 μs + 1 μs + 60 μs = 61 μs.

  3. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR delays by the duration of the presently running ISR duration and the highest priority ISR duration. Therefore, TL for the second highest routine equals to (0 μs + 1 μs + 60 μs) + (0 μs + 1 μs + 80 μs) = 142 μs.

  4. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR delays by the duration of the presently running ISR duration plus the highest priority plus the second highest priority ISR durations. Therefore, TL for the highest but two routine equals to (0 μs + 1 μs + 60 μs) + (0 μs + 1 μs + 80 μs) + (0 μs + 1 μs + 40 μs) = 182 μs.

8096 MCU

Example 6.34

A service routine ISRL is executing an instruction of 3 μs when the interrupt event occurs. (i) What is the worst case latency period for an ISRH of higher priority when other three interrupts may be pending, highest priority H1, second highest priority H2 and third highest priority H3, which can take 80 μs, 40 μs and 100 μs, respectively, if the new service routine can start instantaneously but at the end of the present instruction as in 8096? (ii) What is the latency for the highest priority routine? (iii) What is the latency for the second highest priority routine? (iv) What is the latency for the highest but two priority routine?

 

Assume that the present routine ISRL takes 60 μs. Assume that the initial terminating actions, before the execution of the task-related instructions starts, take 19.25 μs before switching to the new routine ISRH′ and the initial actions, before the execution of the task-related instructions starts, take 8.25 μs.

  1. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR delays by the duration of the presently running instruction in ISRL plus the execution times for the higher than present priority interrupts. Therefore, TL for the current routine equals to (3 μs + 8.25 μs + 10.25 μs) + (8.25 μs + 10.25 μs + 80 μs) + (8.25 μs + 10.25 μs + 40 μs) + (8.25 μs + 10.25 μs + 100 μs) = (21.5 + 98.5 + 58.5 + 118.5) ms = 297 μs.

  2. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR H1 delays by the duration of the presently running ISRL duration. Therefore, TL for the highest priority routine equals to (3 μs + 8.25 μs + 10.25 μs) = 21.5 μs.

  3. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR H2 delays by the duration of the presently running ISRL and the highest priority ISR durations. Therefore, TL for the highest but one routine equals to (21.5 + 98.5) μs = 120 μs.

  4. Latency period TL is the interval between instants when an event occurs and when the servicing task starts by the ISR H3 delays by the duration of the presently running ISRL duration plus the highest priority and the highest priority but one ISR durations. Therefore, TL for the highest but two routines equals to (21.5 ms) + (98.5 ms) + (58.5) = 178.5 μs.

6.5.3 Interrupt Service Intervals

The interrupt service period of an ith interrupt task is Ti = Tinitial + Texecution + Tend. Assume that the interrupt interval between the successive ith interrupt events is Tiintv, then Ti /Tiintv is the fraction of time spent in an interrupt service.

6.5.4 Fraction of Time Spent by the CPU in the RTC Interrupt-Service

The following example shows how to find the fraction of time spent by the CPU for an interrupt service:

Example 6.35

Assume that an RTC interrupt occurs repeatedly every 32.768 ms and RTC ISR executes for 32.768 ϋs. What is the fraction of time spent by the CPU in an RTC interrupt service? The fraction of time spent by the CPU in the RTC interrupt service = 32.768 ms/ 32.768 ms = 0.001 = 0.1%.

6.5.5 Interrupt Density

Assume that the interrupt interval between the ith interrupt events = Tiintv and assume that there are n interrupts. Ti/Tiintv is the fraction of time spent in an interrupt service. Interrupt density = Ξ (Ti/Tiintv), where the summation is for i = 1 to n.

Example 6.36

Assume that the RTC interrupt occurs repeatedly every 32.768 ms and RTC ISR executes for 32.768 μs, the overflow interrupts occur every 500 ms and servicing ISR takes 800 μs and the serial UART interrupts, assuming 10 bits per character, occur at (56 kbps/10) = 5,600 times per second, and ISR for sending a character takes 17.8 μs. What is the fraction of the time spent by the CPU in the interrupts servicing? What is the interrupt density?

 

The fraction of time spent by the CPU in the RTC interrupt service = 32.768 μs/32.768 ms + 800 μs/500 ms + (17.8 μs/178.5 ms) = 0.001 + 0.8/500 + 17.8 μs/178.57 μs. = 0.001 + 0.0016 + 0.1. Interrupt density = 0.1026 = 10.26%. [Note 1/5,600 = 178.57 μs.]

6.5.6 Interrupt Constraints

A constraint on using the interrupts is that the interrupt density should be less than 1. Interrupt density = Ξ (Ti /Tintv where summation is for i = 1 to n should be less than 1. The constraint therefore is that the ISRs should be made as short as possible to reduce Ti. Figure 6.26 shows a high interrupt density case with the constraint for any further interrupts handling.

Another constraint is that the variable x, which is used in two routines or programs when operated, must be protected by defining a critical region. This was shown in steps between 9 and 13 in Example 6.7. The 68HC11 routine need not protect because an ISR executes from the beginning to the end.

When interrupts occur at fast intervals, the service to that can be missed as interrupt density and can become more than 1.

Example 6.37

Assume that the OC interrupt should occur repeatedly every 32 us when the OC ISR adds 0010H in the OC and re-enables the next out-compare and next OC interrupt. What is the time available for initiating the OC ISR, executing and returning from it?

Let the time spent in the OC event servicing = toc. The fraction of time spent by the CPU in the RTC interrupt service = toc μs/32 μs. Interrupt density = toc μs/32 μs should be less than 1.0. Hence, the interrupt constraint is that toc should be less than 32 ms.

Figure 6.26 High Interrupt Density Case with the Constraint for any Further Interrupts Handling

6.5.7 Advantage of Combined Instructions for Reducing Interrupt Density

Recapitulate the DJNZ instruction. It is a combined instruction. It decreases a register and also tests whether the result is 0 and then jump if the result is not zero. Two other examples of instructions which help in reducing the ISR execution time and thus interrupt densities are as follows.

Example 6.38

What is the advantage of an 8051 instruction, which clears or sets or toggles a port bit directly or which sends a byte directly to the port without using the accumulator or RAM?

 

A constraint is that defining the critical region by disabling interrupts before entering and enabling before exiting the region and that must protect the variable used in two routines or programs when operated. The instruction, which clears or sets or toggles a port bit directly or sends a byte directly to the port without using the accumulator or RAM, obviates the need to define the critical region as the interrupt can only occur after finishing the port instruction.

Example 6.39

What is the advantage of a two-variable single shot instruction in 80x96, STB BD, (byte_Pointer)+? It uses these variables and also post increments the pointer in a single combined instruction.

A constraint is that the ISR should be short to reduce the interrupt densities. In several applications, for example, the instruction stores the port byte at a pointer, and then increments the pointer. The use of the single combined instruction shortens the ISR and servicing time. An instruction STB SBUF, (Rbyte_Pointer) + reads a byte Rbyte from the serial port and stores at memory address Rbyte_Pointer and then increments the pointer to receive the next byte at the next memory address. There is no need to disable interrupts between an instant after SBUF read and before the pointer increments when we use a single combined instruction.

SUMMARY
  1. A programmable timer can be programmed for start, stop, loading initial value, auto-load on overflow and pre-scaling clock inputs.
  2. A free-running timer can be used for real-time actions as it has no stop, no reset and no reload features.
  3. Out-compare registers help in generating outputs at precise and programmed instants.
  4. Input-capture register helps in capturing the instants at which the events occur.
  5. RTCIs can be serviced and the ticking rate can be programmed. RTCIs can be programmed to execute a task at a specific instant at a specific rate or within the specified time constraints or in a specified sequence using the timers, which are not re-settable, cannot be stopped and not reloadable.
  6. Software timer interrupts in 80x96 can be used to generate RTCIs. Software timers are the timers similar to out-compare interrupts with some difference that they don’t set or reset an out-bit for external devices control. The software instructions are used to enable the software timer interrupts and to define the count value in a timer at which the interrupts from SWT take place.
  7. Each interrupt has a latency period, which depends on the inherent latency and other pending interrupts.
  8. When using a shared variable between the various routines in 8051 and 80x96, we can use the disable interrupt system instruction at the entry into a critical region and enable interrupt at the exit from the region within a routine.
  9. Programming must be done keeping in view the worst-case latency for an interrupt.
  10. Interrupt density depends on the sum of the ratios of the all the ISR execution times and their intervals of occurrences.
KEY TERMS

Auto-reload: A counter is said to be in the auto-reload mode when on the overflow (transition to all bits 0 state), it loads the previously loaded value again and starts counting the count inputs again.

Counter: Counts the count inputs by incrementing or decrementing.

Critical region: One in which if there are incomplete operations then another interrupt service routine can affect the future results when these are completed later.

Free-running counter: A counter that cannot be reset or stopped when once started on power up.

Input-capture: Capturing the time in a register by reading the count value at a timer on an event or on some trigger, for example, on a positive edge or a negative edge or toggling transition at an MCU pin. Capture can also set a flag and generate an interrupt when the capture interrupt is enabled.

Interrupt constraint: A constraint on servicing an interrupt. For example, interrupts occurring at fast intervals may miss the servicing.

Interrupt density: Sum of the fraction of the time spent in the servicing of all the interrupts with respect to the execution times.

Interrupt execution time: Time for executing instructions in the ISR on an interrupt.

Interrupt interval: The period after an interrupt reoccurs.

Interrupt latency: Time interval between the occurrence of an event and start of the service instructions for it. Out-compare (OC): Comparing an instant specified by a preset count value with the time specified by the count value at a free-running timer and sending an output when two values become equal.

Overflow: Timer incrementing its count value after it reaches the maximum value, the value returns to 0. Overflow event can set a flag and if not masked, an interrupt service routine runs.

Pre-scaling factor: A factor by which the clock pulses divide before being internally fed as the count inputs to the timer. The factor must be programmed in 68HC11 to one out of four possible factors within the first 64-clock periods on MCU start.

Real-time clock: A clock perpetually generating a tick (interrupts or outputs) at regular intervals.

Real-time clock interrupt: An interrupt at regular intervals with an interval programmable by pre-scaling factor or by certain specific bits in a register.

Software timer: It is a timer that generates interrupts with the software instructions (i) setting software timer (SWT enable) and interrupt-enable command bits and (ii) load count value in a register for comparing it with a running timer/counter. The timing actions initiate by writing into an out-compare register called the HSO_ TIME register. On out-comparison with the count value in a running timer, the SWT interrupt flag is set in IO status register IOS1. Interrupt generates like an OC interrupt but no output level is changed for external devices control. Software timer interrupts in 80x96 can be used to generate OC and RTC like interrupts.

REVIEW QUESTIONS
  1. List the timer features that are programmable.
  2. List the timer features that are programmable in a timer as a free-running counter.
  3. A timer can be loaded with a count value. The ISR on overflow can set or reset an output bit. Alternatively, the count value at a timer running as a free-running counter can be continuously compared with a preset count value and can set or reset an output bit. Why is the latter solution most appropriate?
  4. How does the timer overflow interrupt differ from the real-time clock interrupts? Give four applications of the real-time clocked interrupt.
  5. What is the advantage of a 68HC11-like feature that ISR once starts, executes till the return irrespective of the priority of in between interrupt? What is the advantage of 80x96-like feature that ISR once starts execution can be pre-empted by a higher priority interrupt provided that interrupt has been enabled? How do you ensure execution of the critical region instructions in 80x96 ISR?
  6. Explain four applications of real -time clock interrupts? How do the real-time clock interrupts in 68HC11 differ from the software timer interrupts in 80x96?
  7. Describe the concepts of interrupt intervals, interrupt density and interrupt constraints.
  8. SBUF is used to send serial bits from one set of characters by one ISR and is used to send another set of characters for another set using another ISR such that a character each is alternately transmitted by each ISR. What should you disable interrupts when sending a character from an ISR? Assume that the events are not synchronized.
PRACTICE EXERCISES
  1. How will you switch on and switch off a heater for 15 s using a programmable timer that is not free running? Use timer overflow interrupts and also write the algorithm and code using the 8051 instruction set.
  2. How will you get an output as the square wave of 200 μs period using an out-compare register, a free-running 16-bit timer having the count inputs every 2 μs each?
  3. How will you measure the pulse width of pulses of an input port using the input-capture feature? If there is a single measurement of the pulse width, then the resolution equals the interval of the count inputs. If the pulse width is around 64 μs and pulses repeat after every 256 μs, explain how the average of 100 measurements will improve the precision assuming that the count inputs and pulses are unsynchronized.
  4. There are five swimmers participating in a competition. A camera and circuit give five input transitions for five input-capture registers two times; once at the start and next at the end of the swimming. How will you program the measurement of swimming periods?
  5. A motor is rotating a shaft that gives a pulse at every 10° angle of rotation (one revolution = 360°). What is the interrupt interval in μs, if the shaft rotates at 100 rpm? How will you find the rpm using an input-capture register?
  6. The software timer uses the out-compare features. It differs only from the point of view of unavailability of the external outputs. There are four tasks, i, j, k and l. These are to be run in a round-robin mode. (i) Task i runs for first, then task j runs, then task k and then l in each cycle. How is the running of the tasks synchronized? (ii) Each task runs for 10 ms each. How do you use RTCI interrupt feature in 68HC11 with 8 MHz X-tal? (iii) Each task runs for 10 ms each. How do you use four software timers of 80x96 with 2 ms intervals for its count inputs to the timer. (iv) Task i runs for the first 10 ms, Task j runs for the next 8 ms, task k for 6 ms and task l for 4 ms in each cycle. How do you use four software timers of 80x96 with 2ms intervals for its count inputs to the timer.
  7. Task i is to be executed for 4 ms at each 20th ms and task j is to be executed at each 25th ms for 15 ms. What are the interrupt latencies of each task? What are the limits on the execution time of each task?
MULTIPLE CHOICE QUESTIONS
  1. A 68HC11 with 8 MHz X-tal has a 16-bit timer TCNT. It is therefore internally prefixed to receive internal pulses at the rate of 0.5 μs. The count inputs can also be given by programming the PR0 and PR1 bits as 00, 10, 01, and for pre-scaling factor p setting as 1, 4, 8 and 16, respectively. For obtaining overflow interrupts every 32,768 μs
    1. p should be set = 1
    2. p should be set = 1 within the first 64-clock periods
    3. p should be set = 1 within the first 64-clock periods and the overflow interrupt should be re-enabled
    4. p should be set = 16 within the first 64-clock periods and the overflow interrupt should be re-enabled
  2. The timer count value incrementing period is not programmable
    1. In 8051
    2. In 68HC11
    3. In 8051 and 80x96 or
    4. In 68HC11 within the first 64-clock periods after the MCU start
  3. Real-time clock interrupt intervals are programmable
    1. By 4 bits in 68HC11, within the first 64-clock periods after the MCU start by two bits PR0 and PR1 and any time from the start by RTR0 and RTR1 bits
    2. By 2 bits in 68HC11, within the first 64-clock periods after the MCU start by two PR0 and PR1 bits
    3. By two bits in 68HC11, any time after the MCU starts by two RTR0 and RTR1 bits
    4. Not programmable
  4. Real-time actions are feasible
    1. With a free -running timer
    2. With a timer that can be started by another timer
    3. With overflow interrupts of any timer
    4. With the 68HC11 RTCI feature only
  5. In a 68HC11 MCU
    1. Timer overflow interrupts are similar to the real-time clocked interrupts with a difference only in the interrupt intervals
    2. Timer overflow interrupts are similar to the real-time clocked interrupts with two differences, one in the interrupt intervals and another in enabling features for the next interrupt
    3. Timer out-compare interrupts are similar to the real-time clocked interrupts with the only difference in the interrupt intervals
    4. Timer out-compare interrupts are not similar to the real-time clocked interrupts
  6. High interrupt density means
    1. Shorter interrupt intervals and longer interrupt servicing periods
    2. Longer interrupt servicing periods
    3. Shorter interrupt intervals
    4. Shorter interrupt intervals and shorter interrupt servicing periods
  7. Which of the statements is correct?
    1. Any interrupt occurring at regular intervals can be used as RTCI
    2. Out-compare interrupt occurring at the regular intervals can be used as RTCI
    3. Overflow interrupt occurring at regular intervals can be used as RTCI
    4. RTCI interrupt in 68HC11 can be used as a software timer
FILL IN THE BLANKS TYPE QUESTIONS
  1. Timer T0 overflow indicating flag =_____ when the counter has completed _____ counts after counting from 0000H.
  2. A 16-bit counter shows 8000H at an instance. It shows 8080H _____ after _____ μs. Assume that the counter is incrementing every 2 μs.
  3. A 16-bit counter shows F000H at an instance. It will overflow after _____ μs. Assume that the counter is incrementing every 2 μs.
  4. 8051 timer T0 bit _____ in the mode register = 0 and when _____ = 1.
  5. 8051 timer T0 bit _____ in the mode register = _____ and when _____ = 1 and when the external input at _____ pin = 1.
  6. When we load 250 in TH0 and run timer in mode _____ then the timer can interrupt after every _____ μs provided _____ bit = _____ in 8051. Assume that X-tal of 12 MHz is used with 8051.
  7. 8051 mode 3 is used when _____ and _____ are used as timers and timer T1 is used for _____.
  8. Interrupt service routine on timer T0 overflow executes after _____.
  9. Interrupt service routine on timer T1 overflow does not execute when _____ bit = _____.
  10. A timer T0 interrupts on overflow. The overflow flag sets at instance t0. However, the overflow interrupt executes at t0 + 50 μs, because _____.
  11. Free-running counter _____ be reset to 0000H by software instruction.
  12. Out-compare register counts are _____ with _____ counts.
  13. Out-compare register counts are loaded with F000H set and output of out-bit will be = 1 when _____ and free-running counter count-value = _____.
  14. Out-compare register counts are loaded at F000H set and the out-compare interrupt runs an ISR. The ISR increments the register counts by 2000H. The next out-compare interrupts will be when _____ provided _____ bit = _____.
  15. Pre-scaling factor = 4 means _____ increases 4 times and _____ decreases 4 times.
  16. If input-capture facility does not exist then _____ is used as an alternative and the timer/counter is run in mode _____, and the timer/counter is started with initial byte = _____ in _____ register of 8051.
  17. Real-time clock interrupts advantage is _____.
  18. Software timer is provided in _____ MCU. Software timer is used by setting _____ and loading _____ register.
  19. A real-time clock interrupts every 4 ms. The ISR instructions when it runs take 0.04 ms. What is the real-time clock interrupts density? The interrupt density must be _____. It is an important constraint in using the interrupts.
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