7

System Design: Peripherals and Interfacing

A microprocessor needs the external peripheral devices. The peripheral devices provide the parallel ports, serial ports, interrupt handling, direct memory access, ADC and DAC when they interface the microprocessor. An MCU possesses the many of the features of peripheral devices.

However, a particular MCU version in the family may not possess analog-to-digital converter, digital-to-analog converter, modem or DMA (direct memory access) or required device or control or interface circuit.

An MCU may have only a limited number of ports available than the required ones for an application. For example, 8051 in expanded mode has only eight or fewer bits of PI (Figure 3.4) available to interface other devices.

Because of the above reasons, it may be desired to interface 8051 to the external ports or peripheral device chips. The interfacing of peripherals enhances the capabilities of the given version in an MCU family for a specific application.

We shall learn in this chapter a few important peripherals. We will learn interfacing of these with the buses of microprocessor and MCU.

I²C serial bus finds many applications. We shall be learning that also.

7.1 SERIAL UART AND USART COMMUNICATION INTERFACES

Figures 7.1(a) and (b) show the serial bit formats in 8051 serial interface and in 8250 or 8251 peripheral IC chips.

7.1.1 Serial Interface in 8051

Serial interface shows that bytes receive and transmit in Universal asynchronous receiver and transmitter (UART) modes 1, 2 and 3. Mode 1 transmits and receives characters in (10-T) format. [one start bit plus 8-data bits and one stop bit in 10 time slots]. Figure 7.1(a) part 4 shows this format. Modes 2 and 3 transmit and receive in (11-T) format. [one start bit plus 8-data bits and one stop bit in 10 time slots].

The 8051 serial interface in mode 0 receives and transmits as shift register-based synchronous receiver and transmitter.

7.1.2 Serial UART Chip 8250

A modem [DCE (data communication equipment)] connects a COM port. The port is interfaced with Intel 8250 UART in a computer. 8250 is a serial communication chip. It finds extensive application for interfacing line driver and line receiver at COM port of an IBM PC. PC is called DTE (data terminal equipment) when it interfaces a DCE. The COM port of the PC interfaces to the modem or DCE.

The 8250 supports options of 5-bit, 6-bit, 7-bit and 8-bit per character (Figure 7.1(a)). It means, the data frame format is of 8T, 9T, 10T, and 11T where T is the reciprocal of the baud rate assuming 1 stop bit. The 8250 inserts one start bit before the character. It can insert one parity and one stop bit after the character bits (Figure 7.1(a) port 4 1, 2, 3 and 4). 8250 supports 1 or 2 or 1½ stop bit insertion. [Start bit means a logic 1 to 0 transition along with 0 for the period T. 1 stop bit means logic 1 for 1T interval, 2 stop bits for 2T and 1½ stop for 1½ T.] Figure 7.1(b) shows options for stop bits.

7.1.3 Serial USART Chip 8251

8051 synchronous-communication format is using the data and shift clock. There are two lines—one for the data and one for the clock. 8251 provides for only one line communication. It is programmable for both asynchronous UART like the 8250 as well as synchronous serial communication. Synchronisation at receiver end is done by synchronisation bits. (not by clock signals from transmitter.) 8251 inserts appropriate synchronization bits (or characters) in this mode. Intel USART 8251 is an enhanced featured chip. It is also a classic communication chip.

The following is a list of 8251 characteristics:

1. Synchronous and asynchronous serial communication modes.
2. Full-duplex transmission and reception. [Full duplex means send and receive both ways simultaneously.]
3. Double buffered transmission and reception. [During reading and writing new character, the previous one is in the buffer.]
4. Synchronous transmission or reception of 5 or 6 or 7 or 8 bits per character. Synchronous transmission or reception bit rate is settable between 0 and 64 kbps (kilo bit per s).
5. Synchronization at the receiver is provided by insertion of a specific synchronization character (called sync character) or by the sync bits as the preceding characters before the data (Figure 7.1(c). Synchronization can be by internal or external sync character. The automatic sync-character insertion is programmable for one sync character or two.

   Insertion can be of a single or double (two bytes or 16 bits) sync-character.

    

6. Asynchronous transmission or reception of characters each of length 5 or 6 or 7 or 8 bits.
7. Asynchronous transmission or reception with insertion of 1 or 2 or 1½ stop bit for each character.
   

   Figure 7.1 (a) 5 Bit, 6 Bit, 7 Bit and 8 Bit Per Character Formats 1, 2, 3 and 4 at an UART Using the 8250/8251. 8051 Shows 8 Bit/character. An Additional Bit (P Bit) is also sent in Certain Modes. (b) 1 or 2 or 1 16 Stop Bit Insertion in 8250/8251 and (c) Synchronization Character (Called Sync-character) or Sync-bits as the Leading Characters Before the Data at USART 8251 Chip

8. Baud rate for asynchronous transmission or reception is set by a clock. The clock frequency can be programmed as 64 or 16 or 1 times ofthe baud rate. Baud rate for asynchronous transmission or reception can be set between 0 and 19.2 K baud per s.
9. Programmable by three ways—odd or even or none parity during an asynchronous mode.
10. Automatic generation of break detection and break character.
11. Parity, overrun and frame error detection.
12. Input and outputs are at TTL levels. [2.8 V to 5 V logic 1 and 0 V to 0.8 V logic 0 at TTL output.]

Figure 7.2(a) shows a block diagram of the subunits at the 8251-chip. The block diagram gives an overview. It gives a preliminary understanding of the internal hardware. Figure 7.2(b) shows the signals and configuration of the pins at 8251-chip. Table 7.1 gives the meanings and uses of the subunits shown in the block diagram. Table 7.2 gives the uses of pins of 8251.

Table 7.1 The Meanings and Uses of the 8251 Subunits

Subunits	Use
Data bus buffer	Internal buffer register on data bus—It holds the data byte from the data bus during write by the processor. It sends the byte to the data bus during the read operation.
Transmit buffer (P-S) and receive buffer (S-P)	Transmit buffer for sending data bits serially through TxD pin and receiver buffer for receiving the data serially through RxD pin. Start, parity and stop bits (or sync- characters during synchronous communication) are appended and detached at these buffers. TxD = 1 (mark) when the line is idle.
Transmit control	A transmitter-control subunit for generating the signal TxRDY (transmitter ready to receive data from processor for transmission) and TxEmpty transmitter empty (transmission of last bit completed)—connects to and from—TxC (transmitter clock), which controls the bit or baud rate of transmission. (TxRDY and RxRDY reset automatically on the processor write to the transmit buffer and processor read from the receive buffer).
Receive control	A receiver-control subunit generating the RxRDY (receiver ready for data read by the processor) and SynDet/BrkDet (on a sync-character or break-character detection)— connects to and from RxC (receiver clock), which controls the bit or baud rate of the synchronous or asynchronous reception.
Read/write logic	A read/write control logic with signals as follows. (a) Reset (to reset control the programming logic of 8251) connects to processor reset-out. (b) (to read the data bus buffer) connects to control signal of the processor (c) (to write the data bus buffer) connects to control signal of the processor (d) CLK (clock for the 8251) connects to a CLK signal of the processor. It enables setting of the baud rate or bit rate by appropriate internal division at 8251. (e) C/ (control/data connects to A0 address signal of the processor address bus (after latching AD0 using the ALE). When it is 1, the data bus buffer writes into the control in place of transmit register or reads from the status register in place of receive register. When it is 0, the data bus writes (when WR = 0) into the transmit register or reads (when RD = 0) from receive buffer. (f) (chip-select) connects to A1-A15 address signals of the processor address-bus after appropriate decodinga.
Modem control subunit	This has four handshaking signals. Signals are as follows: (a) DSR (to detect that data set ready, at the modem), (b) DTR (to signal to the modem, that data terminal ready), (c) CTS (to detect that the modem is clear to send), (d) RTS (to signal to the modem a request to send from the terminal (all the four are active 0 signals).

Firstly, the two addresses for the USART device are decided. Assume that these addresses are F080Hand F081H. The address bus A0 is directly connected to the chip. Upper 15 bits, A1 to A15 are common to both the addresses. Secondly A1-A15 are used for generating the signal for 8251.

1. AD0-AD7 signals are used to latch A0-A7 using ALE.
2. A0 connect to C/ (control/ data ) pin in 8251.
3. Decoder circuit is designed such that when A15, A14, A13, A12 and A7 = 1s, A11, A10, A9, A8, A6, A5, A4, A3, A2 and A1 = 0s then a decoder output is 0 and connects the pin. The A1-A7 and A8-A15 connects to decoder circuit. The output of decoder selects the 8251 chip when the output connects to (chip select) pin in 8251.
4. D0-D7 bits connect to 8251 D0-D7 pins in 8251.
5. and ( and in 80x86) signals connect to and pins in 8251.
6. , , and pins in 8251 connect to RS232C port in computer. The port is called COM port. COM connects to modem (DCE). RS232C COM port has 9 or 25-pin connector.
7. TxEmpty and RxRDY pins can be connected to the external interrupt pins of the processor.

Table 7.3 Addresses and their uses for the 8251 Communication Interface When F080H and F081H are the Addresses Chosen for the Processor Instructions

Direct Address	Use
0xF080	Address for data transmission during write instruction at this address and for data reception during read by the processor instruction. The address is thus common for transmit buffer as well as receive buffer in 8251.
0xF081	Address for sending the control words during write at this address, and for reading status bits by the processor instructions. This address is thus common for control words as well as status bytes for write and read at 8251.

7.1.4 Programming 8251

8251 is programmed y writing the control words for the mode and commands. However, there is only one address in 8251 when writing the words as well as for reading the status bits (byte) and for writing the mode and command words. A0 is 1 in the address and other bus signals A1-A15 in the address depend on how the chip connects to the address bus through a decoder. Assume that the 8251 data register and command word addresses are F080H and F081H, respectively. Then, during the move of a byte to F081H, A0 will be 1, C/ D pin is at 1 and A1-A15 decode accordingly to select the 8251. How can a single address be used for the various control words for the mode and command (control)? The chip is designed to provide this feature. It can be seen from the following.

1. Any byte sent for the first time after the reset is interpreted as mode instruction.
   1. If mode instruction B1 and B2 (b0 and b1 bits) are 00, then the communication mode is a synchronous mode.
   2. (a) If mode instruction b0 and b1 bits are 10, then the communication mode is the asynchronous mode 1x. (b) If bits are 01, then the communication mode is an asynchronous mode 16x. (c) If bits are 11, then the communication mode is asynchronous mode 64x.

      Note that 1x means communication rate and clocking rate are identical. 16x means communication rate is 16 times less than the clocking rate. 64x means communication rate is 64 times less than the clocking rate.

2. If mode instruction is for asynchronous communication (B1 and B2 are not 00), then the following are the interpretations:
   1. (a) If mode instruction S2 and S1 bits meaning b7 and b6 bits (maximum and maximum but one significance bits) are 01, then the asynchronous communication mode is 1½ stop bit at the end. (b) If mode instruction b7 and b6 bits are 10, then the asynchronous communication mode is 1/ stop bit at the end. (c) If mode instruction b7 and b6 bits are 11, then the asynchronous communication mode is 2 stop bit at the end.
   2. If mode instruction EP bit b5 = 0, then parity generated is odd, else even. Parity generation enables only when if PEN bit b4 = 1.
   3. If mode instruction L2 and L1 bits (b3 and b2 bits) are 11, then the asynchronous communication character is of 8 bits, if 10, then 7 bits, if 01, then of 6 bits, and if 00, then of 5 bits.
3. If mode instruction is for synchronous communication (B1 and B2 are 00), then the following are the interpretations: (a) If mode instruction L2 and L1 bits are 11, then the synchronous communication character is of 8 bits, if 10 then of 7 bits, if 01 then of 6 bits and if 00 then of 5 bits. (b) If mode instruction EP bit b5 = 0, then parity generated is odd, else even. Parity generation enables only when PEN bit b4 = 1. (c) If mode instruction ESD bit (b6) = 1, it means SYNDET is input and sync-character detection is from external device, else sync-character detection is internal and SYNDET is output. (d) If mode instruction SCS bit b7 = 1, it means after the mode instruction the next byte will be sent as control word and it will be the sync character to be used for synchronisation. (d) If mode instruction SCS bit b7 = 0, it means after the mode instruction the next two bytes will be sent as control words and there will be thus two sync characters to be used for synchronisation (bisync mode).
4. If mode instruction is for synchronous communication (B1 and B2 are 00) then after the sync-character(s), the next byte will be interpreted as command instruction. If mode instruction is for asynchronous communication (B1 and B2 both are not 0s) then after the mode instruction (first one after reset), the next byte will be interpreted as the command instruction.

The mode instruction bits are interpreted as per Table 7.4.

 

Table 7.4 Meaning of Each Bit of Mode Instruction

Bit Position	Name	Explanation of the Function
(a) Asynchronous Mode
b7	S2	= 0 means 1 stop bit mode asynchronous transmission provided S1 = 1 = 1 means 16 stop bit mode asynchronous transmission provided S1 = 0 = 1 means 1 stop bit mode asynchronous transmission provided S1 = 1
b6	S1	S2 and S1 = 00 invalid code see row above
b5	EP	= 1 means even parity when PEN = 1 = 0 means odd parity when PEN = 1
b4	PEN	parity enable bit (see row above) = 0 means none parity bit
b3	L2	= 0 means 5-bit per character mode communication provided L1 = 0 = 0 means 6-bit per character mode communication provided L1 = 1 = 1 means 7-bit per character mode communication provided L1 = 0 = 1 means 8-bit per character mode communication provided L1 = 1. (Similar to 8051 UART mode at the SI interface)
b2	L1	see row above
b1	B2	= 0 means 1X mode asynchronous communication provided B1 = 1 = 1 means 16X mode asynchronous communication provided B1 = 0 = 1 means 64X mode asynchronous communication provided B1 = 1
b0	B1	see row above
(b) Synchronous Mode
b7	SCS	= 1 means single sync-character after the character (of 8 or 7 or 6 or 5 bits) = 0 means double sync-character (16-bits) after the character (of 8 or 7 or 6 or 5 bits)
b6	ESD	external sync-character detect = 1 means SYNDET input = 0 means SYNDET output (internal sync detection)
b5	EP	= 1 means even parity when PEN = 1 = 0 means odd parity when PEN = 1
b4	PEN	parity enable bit = 0 means none parity bit
b3	L2	= 0 means 5-bit per character mode communication provided L1 = 0 = 0 means 6-bit per character mode communication provided L1 = 1 = 1 means 7-bit per character mode communication provided L1 = 0 = 1 means 8-bit per character mode communication provided L1 = 1 (Similar to 8051 synchronous mode at the SI interface)
b2	L1	see row above
b1	B2	= 0
b0	B1	= 0

The command instruction bits are interpreted as per Table 7.5.

 

Table 7.5 Meaning of Each Bit of Command Instruction

Bit Position	Name	Explanation of the Function
b7	EH	= 1, enter hunt mode and search for sync character. No meaning in asynchronous mode = 0, normal case
b6	IR	internal reset = 1, internal reset, 8251 goes to same state as after power-up or after external reset signal (usually done for rewriting the control words from the beginning by sending the mode instruction first) after the command instruction, next instruction will be interpreted as mode instruction (Table 7.4) = 0, normal case after the command instruction next instruction will also be interpreted as new command instruction.
b5	RTS	= 1, request to send made to a DCE and thus make RTS pin 0 = 0, disable transmitter and RTS pin = 1
b4	ER	error reset = 1, reset FE, OE and PE status flags (usually done after appropriate action on detecting error flags on reading the status by a processor instruction) = 0, normal case error flags same as before
b3	SBK	send break character = 1, force TxD line = 0 = 0, normal case TxD line = 1 when line ready but idle
b2	RxE	= 1, enable receiver = 0, disable receiver
b1	DTR	= 1, data terminal ready and make DTR pin 0 = 0, disable transmitter and DTR pin = 1
b0	TxEN	= 1, enable transmitter = 0, disable transmitter

 

Table 7.6 Meaning of Each Bit of Status Bits Read from the Address Identical to Control Word Address

Bit Position	Name	Explanation of the Function
b7	DSR	= 1 means Data Set Ready and DSR pin has been forced 0 by the DCE. = 0 means DSR pin = 1
b6	SYNDET/BRKDET	reflects 1 or 0 at the pin SYNDET/BRKDET
b5	FE	Frame error valid, stop bit not detected. It does not effect the operations otherwise (asynchronous case only)
b4	OE	Overrun error (next character started at RxD before the processor read, the previously received one from the buffer). It does not affect the operations otherwise but previously overrun character at the receive buffer only affects
b3	PE	Parity error valid parity bit not detected. It does not affect the operations otherwise (parity enable case only)
b2	TxEMPTY	= 1 means transmitter empty. Further, TxRDY pin will also set = 1 when command bit TxEN = 1 and DCE signal CTS = 0
b1	RxRDY	receiver ready; reflects 1 or 0 at the pin RxRDY
b0	TxRDY	Transmitter ready (byte sent by processor into transmit (Tx) buffer already transmitted and Tx buffer is empty). Further, TxEMPTY pin will also set = when command bit TxEN = 1 and DCE signal CTS = 0 as well as Tx buffer is empty.

Example 7.1

1. How will you write program instructions for 8251 for using the 8-bit data, even parity and one-stop bit UART mode? The mode is similar to the 8051 serial interface 11T mode with TB8 bit. Transmission is with a baud rate, which is 64th of clock rate.
2. How will you write program instructions for using the 8-bit data, even parity and 1 byte sync-character = 11010010 in USRT mode? Set bit rate equal to clock frequency.
3. How will you reprogram 8251 for using the 8-bit data, no parity and one-stop bit UART mode? This mode is similar to the 8051 serial interface 10T mode without TB8 bit transmission. Set baud rate 64th of clock frequency.

Example 7.2

Assume addresses of data buffer and control words = FF80H and FF81H. How will you find the status of 8251?

 

7.1.5 Interfacing to Processor and DCE

Processor connects the 8251 using the circuit shown in Figure 7.3. RxD and TxD pins of 8251 pins are at the TTL levels of voltages. Using an appropriate TTL to RS232C and vice versa converter, the 8251 connects to a PC (DTE). Figure 7.3 shows connections between the converter and 8251. DTE COM port 9 pin connector connects to DCE. Now consider interfacing between 8251 and DCE. SYNDET pin is connected to an external device for sending synchronous character. Figure 7.5(a) shows this. Mode instruction is programmed after reset of b6 to 0. The SYNDET/BRKDET pin is connected to a synchronous modem device, as shown in Figure 7.5(b). Mode instruction sets b6 to 1.

When external baud rate generator is used, SYNC device connects to RxC and TxC.

7.2 PARALLEL IO PORTS INTERFACE 8255

When the 8051 is used in the expanded mode, only P1 or its few pins are available for the port operations. Consider the following needs:

1. Port operations are needed, for example, when interfacing a stepper motor. Stepper motor needs four bits. A robot with four stepper motors (one for the waist, one for the hand, one for the elbow and one for the wrist) will need four four-bit port. Total 16 bits at port will be required for interfacing 4 motors. Figure 7.6(a) shows three ports used as two ports of eight bits each and two ports for four bits each. Figure 7.6(b) shows four exemplary applications.
   

   Figure 7.6 (a) Three Ports Used as Two Eight-bit and Two Four-bit Ports and (b) Four Exemplary Applications

2. Assume a system with up to eight subsystems (or subunits). An example is the system with up to eight LEDs or display systems. Another example is a robot with eight degrees of freedom with one DC motor each for movement in each degree of freedom. A complex example is a plant with temperature and pressure controls at the different chambers. Each subunit is to be programmed for either 1 or 0 independently by the direct bit set or reset. It needs eight one-bit ports. Figure 7.7(a) shows an 8-bit port as the eight one-bit ports when we use a direct set-reset mode. Figure 7.7(b) shows the three applications.
   

   Figure 7.7 (a) Eight-bit Port as the Eight One-bit Ports in Direct Set-Reset Mode and (b) Three Application Examples

3. Consider an external peripheral like a keypad that strobes the information about the key out of the eight keys pressed at an instant (Figure 7.8(a)). Three handshaking signals (strobe, acknowledge and interrupt) are used along with an input port. This enables an external peripheral to send the bytes. The bytes are sent to input port in interrupt-driven mode (Section 7.3.1(2)).
4. Consider 3 signals—Two handshaking and one interrupt control signals (out-buffer full, acknowledge and interrupt); Figure 7.8(b) shows a circuit at an output port to enable an external peripheral to receive the bytes in interrupt-driven mode. The external peripheral may be a printer. Only two signals connect the external peripheral in case of the interrupt is internally used by processor which interfaces the port. PC3 or PC0 connects either to external peripheral interrupt input or to the processor interrupt input.
5. Four handshaking signals and one interrupt control signal (Figures 7.8(c) and (d)) are used at an input-output bi-directional port. This enables an external peripheral to receive and send the bytes in interrupt-driven mode (Section 7.3.1(2)). The external peripheral may be disk controller. It needs one interrupt, two for input mode handshaking and two for output mode handshaking.

Programmable peripheral interface (PPI) Intel 8255 is an industry standard chip. It provides the needed interfacing circuitry, particularly to Intel family processors. It is used for many applications.

8255 has the following capabilities:

1. Supports to three ports (24 programmable I/O lines)—two eight bit and two four bits each, ports programmable as input as well as output (Figure 7.6(a)).
2. Supports a port as eight one-bit ports in the direct bit set-reset mode (Figure 7.7(b)).
3. Support to the input port with two handshaking and interrupt-control signals (Figure 7.8(a)) and the output port with two handshaking and an interrupt control signal (Figure 7.8(b)).
4. Support to a bi-directional input-output port with four handshaking and one interrupt control signal (Figure 7.8(c)).
5. It has TTL level inputs and outputs compatibility. It has compatibility with the buses of Intel processor families.

Figure 7.9(a) shows block diagram of subunits in 8255. The block diagram gives an overview of the internal hardware. Figure 7.9(b) shows the signals and configuration of the pins at the 8255 chip. 8255 is a programmable chip.

1. There are 24 port pins. These are programmed in two groups—Group A consists of 8 bits of port A (PA0-PA7) and 4 bits (upper) of port C (PC4-PC7). Group B consists of 8 bits of port B (PB0-PB7) and 4 bits (lower) of port C (PC0-PC3).
2. A group is programmed in three major modes of operations—mode 0, mode 1 and mode 2. The A, B and ports as well as the control instruction for the operational mode has four distinct addresses in 8255. Thus, there are four addresses for an 8255 that used by instructions of the processor.
3. 8255 is a written data byte which latches at the port using the processor write instruction for write of data buffer. The latching is at the addressed port. The 8255 reads the latched data byte. The processor uses read instruction for the read of data buffer. The reading of the latched byte is from the addressed port.
4. 8255 reads Port C status bits (byte) by processor read instructions for the status of pins of Port C. PC status bits are read when these pins are used for the handshaking and interrupt control.
5. Mode bits written earlier can be read back from the same address as for writing the mode word.

Programming aspects of 8255 are described in Section 7.2.1. Programming must follow the reset on power-up. 8255 once programmed by writing just one byte control word only (for the mode instruction), it will continue to work as programmed till power-down or till reprogrammed by writing a fresh set of control bits.

Table 7.7 gives the meanings and use of the subunits shown in the block diagram. Table 7.8 will give the meanings and uses of each pin.

 

Table 7.7 The Meaning and Use of the Subunits Shown in the Block Diagram of 8255

Full Form	Use
Data bus data buffer	An internal buffer register connects the data bus. Buffer holds the data byte from the bus during write and sends the byte to data bus during read operations of processor. Writing can be at any of the four addresses: three for the ports and one for control word.
Group A Port A, Group A Port C upper, Group B Port C lower and Group B Port B	These correspond to 24 pins for the ports. Ports are called PA, PCH (PC upper), PCL (PC lower) and PB, respectively.
Group A control	Group A control subunit for controlling Group A pin operations as per the mode word programmed for the modes
Group B control	Group B control subunit for controlling Group B pin operations as per the mode word programmed for mode control
Read/write control logic	Read/write control logic signals are as follows: (a) Reset (to reset control logic of 8255), connects to reset-out at processor pin, (b) (to read the data bus buffer) connects to control signal of the processor, (c) (to read data bus buffer) connects to control signal of the processor, (d) A1 and A0 (control/port data) connect to A1 and A0 address signals of the processor address-bus (after latching AD1 and AD0 using ALE). When both are 1s, the data bus buffer writes the control bits for the mode in place of the ports or reads the status bits register. When any one of it is 0, the data bus writes (when = 0) into the addressed port or reads (when = 0) from addressed port A1 and A0 = 00 means data buffer connects the port A, A1 and A0 = 01 means connects port B, and A1 and A0 = 10 means connects port C. (e) (chip-select) pin connects to A2-A7 or A2-A15 address signals (as per the address signals issued by the processor during 8255 read or write) of the processor address-bus through appropriate decodinga circuit.

 

 

Table 7.9 Example Addresses Chosen for 8255 PPI for Design of Decoding Circuit

Direct Address	Explanation of the Function
40H	Port A
41H	Port B
42H	Port C
43H	(i) For sending the mode words (when b7 = 1) then during write and (ii) for mode bits read by processor instructions. (iii) When maximum significant bit b7 in word is, written = 0 then is commanded for set or reset of one of the bits at PC.

7.2.1 Programming 8255

8255 programs by writing eight control word bits at the mode (command) address. The control byte is interpreted as the mode when b7 = 1 (b7 is the maximum significant bit sent by the processor) else is interpreted as control word for the port C pin.

The mode instruction bits are interpreted as in Table 7.10. Mode 0 for Group A or B means that the group main port (A or B) operation is without handshaking signal. Mode 1 for a Group A or B means that group main port A or B operation is with the handshaking and interrupt signal (Figures 7.8(a) and (b)). Mode 2 for a Group A means that group main port A operation to the external peripheral is bidirectional with the four handshaking and one interrupt signals (Figures 7.8(c)). [Bi-directional means Port A and associated PC bits are not specifically defined as input only or output only. Bit b4 of mode write instruction is redundant.]

Table 7.10 Meaning of Each Bit of Mode Instruction (b7 Not 0)

Bit Position	Explanation of the Function
b7	= 0, Port C bit direct set-reset instruction and = 1 means mode select active
b6	= 0, mode 0 Group A port communication provided b5 = 0 = 0, mode 1 Group A port communication provided b5 = 1 = 1, mode 2 Group A port communication provided b5 = 0 or 1
b5	Same as above
b4	= 0, Port A output and = 1 means input
b3	= 0, Port C (upper) output and = 1 means input (only available pins are IO in mode 1 or 2)
b2	= 0, mode 0 Group B port communication = 1, mode 1 Group B port communication
b1	= 0, Port B output and = 1 means input
b0	= 0, Port C (lower) output and = 1 means input (only available pins are IO)

The Port C bits direct set-reset instruction bits are interpreted as given in Table 7.11.

 

Table 7.11 Meaning of Each Bit of Set-Reset Instruction for Port C Bits

Bit Position	Explanation of the Function
b7	= 0, Port C bits direct set-reset instruction active = 1, mode select active
b6, b5 and b4	May be 1 or 0
b3, b2 and b1	= 111 means PC7; = 110, PC6; = 101, PC5; = 100, PC4; = 011, PC3; =0101, PC2; = 001, PC1; = 000, PC0
b0	= 1,set = 0, reset (the PC bit set or reset is defined by b3, b2 and b1a)

 

Table 7.12 (a) Status of the 8255 PA, PB and PC Pins in Mode 0

Pins	Function
PA0-PA7	Input or output (as per b4 mode write instruction) 8-bit port when Group A mode 0
PC4-PC7	Input or output (as per b3 mode write instruction) 4-bit port when Group A mode 0
PB0-PB7	Input or output (as per b1 mode write instruction) 8-bit port when Group B mode 0
PC0-PC3	Input or output (as per b0 mode write instruction) 4-bit port when Group B mode 0

(b) Status of the 8255 PA, PB and PC Pins in Group A Mode 1 and Group B Mode 1

Pins	Mode 1 Group	Function
PC3	Group A	Interrupt control to signal to processor for port A
PC7	Group A	Output signal (out buffer full at port A) to an external peripheral when PA0-PA7 is output port, the handshaking signal. Resets to 0 when output buffer is full by a processor write to port instruction else = 1 when output accepted by external peripheral. (PC5 and PC4 are not used for other handshaking signals in mode 1.)
PC6	Group A	Input signal (Acknowledgement to Port A) from an external peripheral when PA0-PA7 is output port, the handshaking signal = 0 when there is acknowledgement. OBFA will become 1 after interrupt service starts following the acknowledgement PC5 and PC4 not used in mode 1).
PC5	Group A	Output signal (input buffer full at port A) to an external peripheral when input buffer is full and previously sent byte by external peripheral is not yet read by the processor of interrupt service routine not started service for the read. ( will become 1 after read of port A starts following the signal = 0). PC7 and PC 6 are not used for other handshaking signals in mode 1.
PC4	Group A	Input signal (Strobe A) from an external peripheral when PA0-PA7 is input port, the handshaking signal = 0 when there is signal to accept the input from the external peripheral. (PC7 and PC 6 are now not used for other handshaking signals.)
PC0	Group B	Interrupt control signal to processor for port B
PC1	Group B	Output signal (out buffer full at port B) to an external peripheral when PB0-PB7 is output port, the handshaking signal = 0 when output buffer is full by a processor write instruction otherwise = 1
PC2	Group B	Input signal (acknowledgement to Port B) from an external peripheral when PB0-PB7 is output port, the handshaking signal = 0 when there is acknowledgement (OBFB will become 1 after interrupt service starts following the acknowledgement).
PC1	Group B	Output signal (input buffer full at port B) to an external peripheral = 0 when input buffer is full or previously sent byte by external peripheral is not yet read by the processor interrupt or service routine has not started service for the read:
PC2	Group B	Input signal (Strobe B) from an external peripheral when PB0-PB7 is input port, the handshaking signal becomes = 0 when the external peripheral strobes and transfers byte to the input port.

(c) Status of the 8255 PA and PC Pins in Group A Mode 2

Pins	Mode 2 Group	Function
PC3	Group A	Interrupt control signal to processor for port A
PC7	Group A	Output signal (out buffer full at Port A) to an external peripheral when PA0-PA7 is output port, the handshaking signal = 0 when output buffer is full by a processor write instruction = 1
PC6	Group A	Input signal (acknowledgement to Port A) from an external peripheral when PA0-PA7 is output port, the handshaking signal = 0 when there is acknowledgement (OBFA will become 1 after interrupt service starts following the acknowledgement).
PC5	Group A	Output signal (input buffer full at Port A) to an external peripheral when input buffer is full and previously sent byte by external peripheral is not yet read by the processor or interrupt service routine not started service for the read.
PC4	Group A	Input signal (Strobe A) from an external peripheral when PA0-PA7 is input port, the handshaking signal = 0 when there is a request to accept the input from the external peripheral (IBFA will become 1 after an interrupt service or processor read starts following the IFBA).

 

Let us assume that in the following examples, 8255 is interfaced to the processor buses such that it is addressed using the addresses given in Table 7.9.

Example 7.3

1. How do we program 8255 for 8-bit data output to port A and 8-bit input at port B pins? Assume no handshaking or interrupt signals are used at each of these ports.
2. How do we program the 8255 for (i) 8-bit data input to port A with two handshaking and one interrupt signals and (ii) 8-bit input at port B pins with no handshaking or interrupt signals? Assume that mode instruction address 43H is as per Table 7.9.

Example 7.4

(i) How will you reset PC3? Assume PC3 connects an interface to a valve. (ii) How will you set PC0? Assume PC3 connects to an LED circuit.

 

7.2.2 Interfacing 8255 to Processor

Firstly, four addresses for 8255 are chosen. Let us assume that these addresses are 40H, 41H, 42H and 43H. Upper 14 bits A2 to A15 are common to all four addresses. Hence, these are used for generating the signal for 8255. Decoder circuit is designed in such a way that when A7, A6, A5, A4, A3 = 0s and A2 = 1 the decoder output is equal to 0 and connects pin.

Figure 7.10 showed the interfacing of the 8255 chip with address and data buses of processor (such as 8085 or 80x86, 8051 or 68HC11), A0 and A1 connecting to A0 and A1 bus signals and (chip-select) is from a decoding circuit. Decoding circuit decodes A2-A15 or A2-A7 (or A10-A15 in case of 8085) bus signals and sends when address bus addresses any of the address among 40H, 41H, 42H and 43H.

1. When AD0-AD7 are the signals, using ALE at the processor, the address A0-A7 bus signals are latched before decoding. Address bus signals A0-A1 after latching are connected to the chip A0 and A1 pins.
2. D0-D7 bus signals connect to 8255 D0-D7 pins (Table 7.8).
3. and (IORD and in 80x86) signals connect to and pins of 8255. Reset pin connects the reset out pin of the processor.

7.3 DMA CONTROLLER 8257

7.3.1 Methods for IO Transactions

Assume that IO transactions take place between the peripheral device and system-memory. Peripheral needs to send data into the system memory or receive data from the memory.

Consider the following:

1. A peripheral like a hard disk needs to load the program or file into the memory. It needs bulk (1 kB plus) transfer and there is need of large number of IO transactions between memory and disk. Alternatively, a file is to be written into the disk. It needs bulk (1 kB plus) transfer and there is need for large number of the transactions.
2. A memory location needs to be read and rewritten at the same location again and again because memory happens to be DRAM (dynamic RAM) and RAM needs refreshing within a specified interval.

There are three methods for the IO transactions which occur between peripheral device and system (Figures 7.11(a), (b) and (c)).

1. Programmed IO transfer (busy and wait IO) mode
   1. Read: A byte or word is read using an instruction. Then wait is done for the period in which the next byte or word will be available and then transfer that by the read instruction when ready. Continue wait and transfer till all the bytes are transferred as programmed.
   2. Write: A byte or word is written using a processor instruction. Wait for the period within which next byte or word can be written into the peripheral and then again transfer the byte or words using the processor write instruction when ready. Continue till all the bytes are transferred as programmed (Figure 7.11(a)).

   The method is therefore, also called busy and wait IO method. The 8255 mode 0, Group A or B transactions are the busy and wait IO mode transfers. Note: a status flag will show when the peripheral is ready for a next read or write operation.

    

2. Interrupt-driven IO transfer mode
   1. Read: A byte or word is read using a processor instruction on an interrupt using an ISR. Wait for the next interrupt and till then execution of the foreground program continue or other tasks run. Read on next ISR call on interrupt.
   2. Write: A byte or word is written using a processor instruction on an interrupt using an ISR. Wait for the next interrupt and till then perform other tasks or continue the foreground program. Write on the next ISR run on the next interrupt (Figure 7.11(b)). The 8255 mode 1 Group A or B or mode 2 Group A transactions are data transfers interrupt-driven IO mode.
3. Direct memory access (DMA) by DMAC
   1. Read: A byte or word is read from the peripheral not by using a processor instruction but by using a DMAC (DMA controller), which transfers it to the memory at address block. A block of addresses is programmed for data transfer using direct memory (RAM) access. The method is such that processor do not wait for input port to be ready. The method is also such that processor do not wait for completion of output. DMAC sends a hold request and processor acknowledging as and when the processor buses are available to DMAC. Transfers do not use the processor instructions and fetches from peripheral during read instructions. DMAC continues to read and transfer to the memory till the programmed number of bytes is transferred. After the transfer is complete, it interrupts the processor so that the processor can reprogram the DMAC.
      

      Figure 7.11 (a) Programmed IO (Bus-wait IO) Transfer Mode, (b) Interrupt-driven IO Transfer Mode and (c) Direct Memory Access by DMAC (Peripheral Transactions Server (PTS)) Driven IO Transfer Mode

      The method is such that processor programs only once by sending (i) instructions to the DMAC, (ii) start address of the memory and the programmed number of bytes, which are to be transferred. The processor continues other tasks and waits for the ISR run on interrupt from DMAC after the terminal last byte is transferred from the peripheral.

       

   2. Write: A byte or word is sent to the peripheral not by using a processor write instruction but by the DMAC, which transfers it from the memory (at a programmed address block). Transfer is by DMAC sending a hold request and processor acknowledging as and when the processor buses are available to it. Transfers do not use the processor using the write instructions. DMAC follows the course as described above. The method is such that processor programs the DMAC once. The processor continues other tasks till requisite number of bytes are transmitted during idle state of the buses.

When the transfer completes, the processor is interrupted. Processor then takes further step as required. A DMAC is a PTS (peripheral transactions server), which reduces the need of running of an ISR for each byte or word transfer. A context switch to ISR and return switch from ISR takes many cycles. The method of using PTS is such that Processor just initialises the DMAC by running a few instructions to send the data in registers and commands (sends start address, count-value and mode instruction). The ISR runs on terminal count in the end only.

DMAC is the most efficient way of using the idle time of processor buses. It is used for the bulk transfers in between the memory and peripheral when required. Figure 7.11(c) shows the block diagram, signals and buses when using a DMAC.

A multi-channel DMAC facilitates transactions with several peripherals. For example, a four channel DMAC can perform transactions with the floppy and hard disks as well as DRAM refresh controller in a computer.

The 8051 does not facilitate use of DMA. 8257 is Intel DMAC chip for the same. Several MCU family versions provide the on-chip PTS (single channel or multiple channels). 80196 MCU has built-in PTS device (DMAC). 80960 MCU has built-in PTS device for DMAC as well as IOP (input-output processor).

Programmable direct memory access controller (DMAC) Intel 8257 is for the much needed DMA transactions, particularly suited to Intel family processors in the computers as well as for many applications.

The 8257 DMAC has the following capabilities:

1. It supports four channels.
2. Priority DMA requests control logic exits so that higher priority peripheral transaction channel can transfer with higher priority and a channel can also be inhibited.
3. Output on each terminal count (after last DMA-byte transaction) as well as after each completion of the 128 transactions.
4. Facilitates auto load, (of DMAC registers) after the last byte transfer.
5. TTL level inputs and outputs compatibility and a compatibility with the buses of the Intel processor families.

The 8257 is a programmable chip. It can be commanded to transfer a maximum of 16 kB data between the memory and peripheral device without further processor instructions. There are four bidirectional address pins A0-A3 and four unidirectional address pins A4-A7 and 8-data bus pins D0-D7. A0-A7 thus outputs LSB (least significant byte) for address for the memory. It outputs MSB (maximum significant byte) to the memory through a decoder 8212 using the D0-D7 lines (8212 decoding is similar to decoding of AD0-AD7 by a latch using the ALE). For each channel there is a separate 16-bit terminal count register. For each channel there is a separate 16- bit DMA address register. The 8257 channels generate DACK0, DACK1, DACK2 and DACK3 active 0 signals to the peripherals, when these request the DMA transactions through DRQ0, DRQ1, DRQ2 and DRQ3 active 1 signals.

7.3.2 Programming 8257

Once the 8257 is programmed, the IO transactions using DMA can take place. 8257 chip is assigned 16 addresses using which the processor can write chip internal registers and MODESET register (for mode instruction).

Each channel has one 16-bit register for ADDR [DMA address (start address for read or write at RAM) and one 16-bit register for TC [terminal count (number of bytes to be transferred)] using DMA transactions. It should be noted that the 16-bit register has the same address for LSB and MSB. Whatever byte is written first by processor instruction is presumed as LSB and whatever next as MSB. Next to MSB the next write will be accepted as LSB. These are loaded for initialising the DMAC using A0-A3.

When A0-A3 are inputs to DMAC and A3 = 0, one of the above 8257 internal registers selects when these are written or read by the processor (or master) (Ch0 DMA address = 0000; Ch0 TC address = 0001; Ch1 DMA address = 0010; Ch0 TC address = 0011;…). When A3 = 1, in place of the above internal registers, the MODE SET register is selected. It is programmed (written) after all the TCs and DMA addresses are written. When A3 = 1 and the 8257 is read, then the status register is selected. Table 7.13 gives the meaning of the bits at the MODESET and status register.

 

Table 7.13 (a) Meaning of Each Bit of Mode Instruction at Mode Set Register^a

Bit position	Function
b7	= 0, disable auto reload (initialisation) after the terminal count = 0 on transaction of last byte = 1, enable auto reload (as per earlier initialization)
b6	= 0, disable terminal counter stop = 1, enable terminal counter stop
b5	= 1, enable extended write = 0, disable extended write
b4	= 0, disable rotating priority among Ch0, Ch1, Ch2 and Ch3 = 1, enable rotating priority among Ch0, Ch1, Ch2 and Ch3
b3	= 1, enableb Ch3 = 0, disable Ch3
b2	= 1, enableb Ch2 = 0, disable Ch2
b1	= 1, enableb Ch1 = 0, disable Ch1
b0	= 1, enableb Ch0 = 0, disable Ch0

 

(b) Meaning of Each Byte Sent (or read) into Internal Registers^a

Address Bits	Function When 8257 is Addressed at that Address
0000	Ch0 DMA Address 16-bit register
0001	Ch0 TC 16-bit register
0010	Ch1 DMA Address 16-bit register
0011	Ch1 TC16-bit register
0100	Ch2 DMA Address 16-bit register
0101	Ch2 TC16-bit register
0110	Ch3 DMA Address 16-bit register
0111	Ch3 TC 16-bit register
1000	Mode Set 8-bit register (when written) and Status register 8-bit when read

(c) Meaning of Each Bit of Status Register (Accessed/read From Address with A3A2A1A0 = 1000)

Bit position	Function
b7	= 0 (always reset)
b6	= 0 (always reset)
b5	= 0 (always reset)
b4	= 1, update flag (No effect of status register read instruction)a = 0, on 8257 reset or on mode register instruction is in non-auto reload mode (b7 = 0)
b3	= 1, Ch3 TC output activated, after reaching 0b = 0, Ch3 TC not activated, transactions still incomplete
b2	= 1, Ch2 TC output activated after reaching 0b = 0, Ch2 TC not activated, transactions still incomplete
b1	= 1, Ch1 TC output activated after reaching 0b = 0, Ch1 TC not activated, transactions still incomplete
b0	= 1, Ch0 TC output activated after reaching 0b = 0, Ch0 TC not activated, transactions still incomplete

Figure 7.12(a) shows the block diagram of the subunits at 8257 chip. The block diagram gives a simple overview (for a preliminary understanding) of the internal hardware. Figure 7.12(b) shows the signals and configuration of the pins at the 8257 chip.

Table 7.14 gives the meaning and use of each subunit shown in the block diagram.

 

Table 7.14 The Meaning and Use of the Subunits Shown in 8257 Block Diagram

Subunits	Use
Data bus buffer	Internal buffer register for the data bus. It holds data byte from the data bus or the address A8-A15.
Control logic and mode setting	It sends HRQ (hold request) to the processor to get access to the buses and processor grants that request through HLDA (hold acknowledge). It issues terminal count (TC) signal to processor, at which processor can interrupt and run an ISR to modify DMAC program or stop further DMAC use. It also issues mark signal after each 128th cycle also. It sends A4-A7 address signals to the memory along with the A0-A3 by read-write logic and along with the A8-A15 using D0-D7 lines. It sends MEMR and MEMW signals to memory for memory-read and memory-write. It sends ADSTB (address strobe) signal so that 8212 or other decoder can latch A8-A15 from the D0-D7 lines. It sends AEN (address enable) to disable system data bus or inhibit other peripherals not attached to the DMAC to send the address. Ready signal to the logic extends a read or write cycle in case the memory chip needs longer cycles for a transaction.
Priority resolver	To resolve the priorities as per the program written at the 8257 register for mode instruction
Ch0 Address/counter	For channel 0 memory start address and counts (programmed number of bytes for the transfer before DMAC issues TC signal)
Ch1 Address/counter	For channel 1 memory start address and counts (programmed number of bytes for the transfer before DMAC issues TC signal)
Ch2 Address/counter	For channel 2 memory start address and counts (programmed number of bytes for the transfer before DMAC issues TC signal)
Ch3 Address/counter	For channel 3 memory start address and counts (programmed number of bytes for the transfer before DMAC issues TC signal)
Read/write control logic	A read/write control logic subunit. Signals are as follows: (a) Reset (to reset the programming logic of 8257), it connects to processor reset-out. (b) Active 0 (to read) when input to processor using the data bus buffer which connects to DMAC registers for a channel. When input to processor the data bus buffer connects to D0-D7 lines. (c) Active 0 (to read) the data bus buffer, which connects when input to DMAC to mode set register of the DMAC. The buffer connects when output is such that logic allows data output on D0-D7 lines. (d) CLK (clock) for the 8257, it connects to a CLK control signal of the processor. (e) A0-A3 bi-directional when input, selects the DMAC registers and when output gives A0-A3 signals to address bus. (f) (chip-select), it connects to IO address signals A4-A7 of the processor on the address bus after appropriate decoding

Table 7.15 gives the meaning and uses of each pin.

 

7.3.3 Interfacing to 8086, 8051, 8096 and 68HC11/12

Figure 7.13 shows interfacing of 8257 DMAC with the external peripherals and processor.

80x86. Address and data buses A0-A3 connecting to A0-A3 and (chip-select) connect to A4-A7 through a decoder. Port pins of 8051 or 68HCC can be made of use for the ADSTB, , , , , hold, hold acknowledge signals.

1. When AD0-AD7 are the signals, using ALE at the processor, the address A0-A7 bits are latched before decoding.
2. The D0-D7 bits connect to latch D0-D7 pins (Table 7.15).
3. , ( and signals connect directly or through appropriate logic. Reset connects the processor reset out signal.

Firstly, 16 addresses for the 8257 DMAC device are decided. Assume that the addresses chosen are C0H to C3H. Address bus A0-A3 signals are directly connected to the chip. Upper 4 bits A4 to A7 are common to both the addresses. Hence, these are used for generating the signal for 8257. Decoder circuit is designed such that when A7-A6 = 11 and A5A4, = 00, then the decoder output = 0 and connects the pin.

7.4 PROGRAMMABLE INTERRUPT CONTROLLER 8259

The interrupt-handling mechanism and interrupts handling in 8051 are described in Section 3.7. Interrupt-handling structures in MCUs are described in detail in Chapter 5. Most MCUs may support just two external pins as interrupts. The 8051 supports two external interrupts—INT0 and INT1. Several systems need to connect externally to more than two interrupting sources and devices. For example, a PC connects to two COM port devices (like modem and mouse), printer and CRT interfaces, time of the day signal, CD disk drive and hard disk drive. There is a need for one external interrupt input pin for each device. When there is need for more than one or two hardware interrupts from the external sources, additional circuitory is required. Programmable interrupt controller (PIC) Intel chip 8259 provides the needed circuitory. It is now an industry standard chip. It finds extensive application as an interrupt handler.

Intel 8259 is a classic interrupt controller. It is programmable for masking the interrupts, priority resolution and vectors for the interrupts. [Vector means the address from where the processor finds new service routine (or new service routine address) in case an interrupt occurs.] The 8259 has the following capabilities:

1. Eight interrupt request pins. There are 8-levels of priority for the interrupts. These are expandable by cascading up to 64 levels. 8-level means interrupts can be assigned priority 0, 1, …, 7. The 64 level means 0, 1, 2026;, 63.
2. Each interrupt request is separately maskable.
3. Priority resolution when more than one interrupt is pending service.
4. TTL level inputs and outputs.

Figure 7.14(a) shows the block diagram of subunits at 8259 chip. The block diagram gives an overview (for a preliminary understanding) of internal hardware. Figure 7.14(b) shows the configuration of pins at 8259 chip.

Table 7.16 gives the meanings and use of subunits shown in block diagram.

 

Table 7.16 The Meaning and Use of Subunits in 8259

Subunits	Use
Data bus buffer	An internal buffer register with the data bus. It holds the byte from data bus during write and sends the byte to the data bus during read operations of processor. Write operation is done for programming ICWs (initial command words) and OCWs (operational command words) at 8259. Read operation is for the 8259 status read.
Priority resolver (P register)	8-bit register to resolve the priority stores the priorities of 8-interrupts at request (IRQ) pins. Priority sets as per OCW. Default is fully nested priority in order IRQ0 (highest) and IRQ7 (lowest). Priority can also be set to auto rotate (higher priority one after servicing becomes the lowest one) and specific rotation (changing priorities by specifying a device of lowest priority and the next to it as highest).
Interrupt request register (IRR)	8-bit register to store the requests from the 8 interrupt-request (IRQ) pins. When a request is services, the corresponding to the request the bit in the register resets.
Interrupt control logic	Control logic.
Interrupt mask register (IMR)	8-bit register to store the interrupt masks for the 8 IRQ pins. OCW1 programs the IMR.
In service register (IS register bits)	8-bit register for in service operations. If 7th IS Register bit = 0, means serviced or service not pending and = 1 means IRQ7 to be or being serviced. (Issuing INTR signal and placing the appropriate bytes during the cycles through D0-D7 enables vectoring to the ISR address for the IRQ7).
Read/write control logic	A read/write control logic subunit. Signals are as follows: (a) (to read) the data bus buffer, it connects to control signal of processor (for example, to P3.6 in 8051 as shown in Figure 3.4.), (b) (to read) the data bus buffer, it connects to control signal of the processor (For example, to P3.7 in 8051 as shown in Figure 3.4.), (c) A0, it connects to A0 address signal of the processor address-bus (after latching AD0 using the ALE) and (d) (chip-select), it connects to A1-A15 or A1-A7 address signals of the processor address-bus after appropriate decodinga
Cascade buffer Comparator subunit	Used when the 8259 is cascaded with other 8259 to increase the IRQs up to maximum 64 levels. CAS0, CAS1 and CAS2 IO pins selects or shows which of the 8259 out of 8 cascaded together is to be used. [0 at CAS2-CAS1-CAS0 means 0th 8259 and 111 means 7th 8259.] SP-EN pin is to enable the cascade buffer. When SP is input and = 0, it means this 8259 is slave. EN is output and = 0 means this 8259 enabled and presently holds the buses.

 

Table 7.17 gives the meanings and uses of each pin.

 

 

Table 7.18 Addresses for the Programmable Interrupt Controller (PIC) 8259

Direct Address	Use
0x20	Initial Command Word ICW1. Sequences of codes for the type (level) for the IRQ0 to IRQ7 are written.
0x21	Initial Command Words 2 (For cascade or normal mode), 3 (for automatic or manual end of interrupt) and 4 (for fully nested, automatic or specific rotation mode).

7.4.1 Interfacing 8259 to Processors

Figure 7.15 shows the interfacing of the 8259 chip with processors (such as 80x86, 8051 or 68HC11) address and data buses, A0 connecting to A0 and (chip select) connecting to A1-A15 through a decoder.

1. When AD0-AD7 are the signals, using ALE at the processor, the address A0-A7 bits are latched and then decoded by a decoding circuit.
2. The D0-D7 connect to 8259 D0-D7 pins.
3. and ( and in 80x86) signals connect to 8259 and pins directly.
4. Two addresses for the 8259 device are decided. Assume that these addresses are 20H and 21H. Address bus A0 is directly connected to chip. Upper 7 or 15 bits A1 to A15 are common to both the addresses. Hence, these are used for generating the signal for 8259. Decoder circuit is designed such that when A1 = 1 and A2-A7 = 0s then the decoder output = 0 and connects the ADDR0, ADDR1 and ADDR2 pin.
5. The INTR and connect INTR and pins at processor.

7.5 ADC CIRCUIT INTERFACING

Analog-to-digital Conversion (ADC)

There are six steps in analog-to-digital conversion:

(1) An ADC (analog digital conversion) circuit is given an analog input; (2) The analog input is given after a sample hold amplifier; (3) The sample hold amplifier samples the signal for a small time interval t_s after which it holds the output amplifier and thus analog input V_in remains constant at the ADC for the holding interval t_h; (4) The ADC is given a start of conversion () signal for starting the conversion of V_in to n-bits; (5) ADC converts into digital bits in a time interval t_conv. The time interval is called conversoin time; (6) The ADC issues an EOC (end of conversion) signal after the conversion is over. Assume an n-bit ADC. Then the conversion formula is as follows:

V_in is analog input voltage. n is the number of ADC bits after conversion. Here (V_ref+ − V_ref−) is voltage difference between + and − pins for applying reference voltage input.

Example 7.5

Assume (V_ref+ − V_ref−) = 2.04 V, V_in = 1.032 V. n = 8. Maximum digital value = (2⁸ − 1) = 255. (i) What is the output of an ADC? (ii) What is the resolution of the ADC? (iii) What are the limits for V_in?

 

ADC Conversion Accuracy, Speed and Time

Conversion accuracy is defined by how accurate is the conversion in an ADC with respect to a given reference voltage at ADC. Conversion speed is defined by how fast is the conversion in an ADC. It is measured by number of conversions successfully made per second. Conversion time is defined by after how much time the conversion will be over and end of conversion interrupt generates with respect to a start of conversion signal.

Internal ADC in an MCU

Figure 2.12 showed an internal ADC in an MCU. It showed reference inputs with three possible options in the MCU. Section 2.3.10 described the on-chip ADC features in specific versions of a family. For example, 80535 has an 8-bit ADC and reference voltages V_ref+ − V_ref− are separately programmable. The 80552 has a 10-bit ADC. It has 8-channel MUX (multiplexer). The MUX enables the use of the same ADC for eight different analog channels.

External ADC Interfaced to an MCU

An external ADC chip interfacing provides the requisite conversion time and other features. These may not be available on the chip in a version of an MCU family or the external ADC may be a cost effective proposition after interfacing it with the low cost ADC-less version. ADC 0804, ADC 0808, and ADC 0816 are the examples of 8-bit ADCs for 1, 8 and 16 channels, respectively. Figures 7.16(a) to (c) show block diagrams of interfacing units for ADC 0804, ADC 0808 and ADC 0816. The block diagrams show the overviews (for preliminary understanding) of hardware. These chips do not have command (control) register. Therefore, these directly interface to port bits of MCU.

Table 7.19 gives the meanings and use of the ADC interfacing in Figure 7.16.

 

Table 7.19 Meanings and Uses of ADC Interfacing Units

Subunits	Use
IC chip voltage reference generator	A circuit for generating the voltage reference (Vref /2) or Vref+ and Vref−.
Sample-hold circuit	To sample the analog input for a period which is set for time interval ts and then hold it till the conversion interval.
Read/write control logic and channel address latch and out enable circuit	Circuit enables the ADC to get channel number through the data bus lower four bits when ALE = 1. The circuit inputs are external and are read, write and address-latch enable from the system bus. Circuit enables the ADC to place on data bus the converted bits, when = 0.
Start of conversion, end of conversion (EOC), interrupt and timer-circuit for sampling rate	There are one output and three inputs (to ADC) through four tristate buffers. EOC generates an interrupt signal to the processor or PIC when interrupt select (INTS) is set (enabled). Timer clock can also generate the periodic interrupts when timer clock by INTS reset is selected. Timer clock signal can also periodically start the conversion or an external start conversion signal (STC) can also start conversion.

Table 7.20 gives the meanings and uses of each pin for ADC 0816.

 

Assume that ADC chip selects when addresses are between 0x40 and 0x4F. Table 7.21 gives the addresses of the analog channels. Using an address, the converted bits of a channel are read by a processor read instruction.

Figure 7.17(a) shows the interfacing circuit of the ADC chip with the LSB of lower address and data buses. addr0, addr1, addr2 and addr3 are the addresses of channel sent through AD0-AD3 lines for 16 channels. (chip-select) connects through a decoder. Decoding circuit is such that when the processor addresses the ADC chip for read or write, then only = 0, else itis 1 for other peripherals or memory addresses. ADC 0816 conversion time is 110 μs plus there is S/ acquisition time plus S/ settling time and IN/OUT instructions execution time. Figure 7.17(b) shows the interfacing circuit of the ADC chip ADC 0808 with the LSB of lower address and data buses. addr0, addr1and addr2 are the addresses of channel sent through AD0-AD2 lines. Figure 7.17(c) shows interfacing the ADC internal device with 68HC11.

 

Table 7.21 Addresses for the 16 channel ADC Interface when 40H-4FH are the Addresses Used by the Processor Instructions

Direct Address	Function
40H	Analog Channel 0 Select
41H	Analog Channel 1 Select
4EH	Analog Channel 14 Select
4FH	Analog Channel 15 Select

Figure 7.18 shows the programming steps for reading the ADC channels.

Considerations when Selecting or Using an ADC

Following are the considerations when selecting or using an ADC:

1. Location : Location of ADC should be near the transducer and then converted bits are sent to MCU at a remote location. This arrangement reduces the noise pick-ups during the signal path. It reduces ground loop related error. (Error due to path to ground potential is longer than the active pin signal path.) A transducer is one that gives the form of a value observed for a resistance, capacity or voltage or current or frequency, which is in accordance with the physical value of a parameter. The parameter could be pressure, temperature, light-intensity, linear or angular position. Transducer with appropriate signal conditioner and sample-hold amplifier generates the desired parameter-related analog signal. The signal is the ADC input at an instance. Signal conditioner is a circuit to give outputs for the ADC such that the minimum and maximum values of the parameter being measured give the ADC analog inputs between V_ref+ and V_ref−. For example, human body temperature can be between 98°F and 105°F. Signal conditioner at the transducer output can generate 0 V for 98°F and 2 V for 105°F.

   Example 7.6

   Assume that temperature is measured between −40°C minimum to +40°C maximum, and V_ref+ = 2.048 V and V_ref− = 0.000 V at the ADC. Assume that the transducer is such that it gives 233 μA current when T = −40°C and 313 μA current when T = +40°C. The transducer output should be signal conditioned by an amplifier circuit such that the ADC input is between 0.000 V and 2.048 V when temperatures is between −40°C and +40°C.

2. Sampling and data throughput rates: Need for recording more samples per second may be there when recording an analog waveform (for example, an ECG signal). Need of a higher sampling rate may inhibit use of a single ADC for the multiple analog channels. Sample-hold amplifier samples the signal for a specific period to reduce the sharp transitions and noise effects. However, sampling rate is inversely related to sampling time. Sample-hold circuit should use very low-leakage capacitor like polystyrene capacitor.
3. Number of analog channels: The number of analog channels may be required in a specific system like data acquisition system.
4. CMOS or bipolar-based ADC selection: A CMOS-based ADC advantage is low power dissipation and easy circuitry for multiplexing, latching and decoding. The disadvantage is the low precision of reference voltage and low conversion speed.
5. Conversion accuracy: The desired accuracy in conversion is an important criterion. Use of ADC full input range helps in enhancing the accuracy. For example, assume that reference voltage is +2.023 V and input ADC signal is of maximum = +0.5 V. (Assume that negative reference point is at ground level.) We can amplify the input four times before conversion to enhance the conversion accuracy. Consider another example, assume that reference voltage is positive 2.023 V and input ADC signal is of +0.5 V maximum and +0.3 V minimum. (Assume negative reference point is also programmable or can also be fixed) We can amplify the input four times before conversion and fix negative reference at +1.2 V to enhance the conversion accuracy. [Fixing −ve reference other that analog ground is feasible in certain ADC circuits or MCUs.]
6. Reference signal: Reference signal precision affects the ADC precision. Hence, reference signal source circuit can be important criteria. Also, choose dual reference (positive and negative) references and programmable references for better accuracy, resolution, and precision (Figure 2.12).
7. Separation of analog and digital grounds: Digital ground electrical line carries end noise. The noise arises due to sharp 1 to 0 and 0 to 1 transitions at the logic circuits which cause induced voltages in the neighbouring lines. A decoupling capacitor is placed near the digital circuits for reducing the noise signal. The separation of analog and digital ground lines further reduces the noise and that is the best proposition.

7.6 DAC CIRCUIT INTERFACING

Digital-to-analog Conversion (DAC)

There are three steps in digital conversion from analog:

(1) A DAC (digital-to-analog conversion) circuit is given the digital inputs. For example, 8 bits from 8-port pins. The analog output is obtained after a current amplifier. V_out remains constant at the DAC for the holding interval t_h, till another pulse for start of conversion (STC) signal is applied to DAC. (2) DAC converts digital bits in a time interval t_conv to analog current. The time interval is called conversion time; (3) After the conversion is over, the dAc gives V_out as per conversion formula:

k is a constant dependent on current amplifier at the DAC output. n is the number of DAC bits for conversion. Here (V_ref+ − V_ref−) is the voltage difference between + and − pins for applying reference voltage input to DAC.

Example 7.7

(V_ref+ − V_ref−) = 2.04 V. n = 8, Digital input = 1000 0000 = 128 decimal. (i) What is V_out? Assume k = 1. (ii) What is the resolution of DAC?

(i) Using Equation (7.2) the output will be 1.024 V (ii) The DAC resolution is 2.04 V/(2⁸ − 1) = 2.04 V/255 = 8 mV. Resolution multiplied by 128 decimal gives 1.024 V.

DAC Conversion Accuracy and Time

Conversion accuracy is defined by how accurate the conversion is in a DAC with respect to a given reference voltage at DAC. Conversion time is defined by after how much time the conversion will be over and analog output obtained after the change of bits at the DAC input.

Internal PWM in MCU for DAC

On-chip PWM has DAC features. Section 2.3.9 and 2.3.6 explained the PWM feature. Specific versions of a family, for example, 80552 and 80C580 have on-chip PWM. Figure 2.11(b) shows internal PWM (pulse width modulation) feature for the DAC operations using the external integrator with an MCU. The MC68HC11N4 series versions have two channels DAC outputs. Two DAC outputs (at port G bits 5 and 4) are according to the bytes programmed at two data registers of 8-bit each. A control register DCON bits (b0 and b1) are programmed to enable or disable the DA channel 1 and 2, respectively, according to the data registers DA1 and DA2, respectively.

External DAC for Interfacing with MCU

Interface circuit with an external DAC chip provides the requisite conversion time and other features that may not be available on-chip in a version of an MCU family or the external DAC may be a cost-effective proposition after interfacing it with the low cost PWM or DAC-less version MCU. DAC808 and MC1408 are the examples of 8-bit DACs (for 1 channel). Figure 7.19 shows interfacing circuit using DAC 808. These chips have no internal command register. They can also directly interface to port pins of MCU.

Table 7.22 gives the meaning and use of each pin for DAC 808.

 

Figure 7.20(a) shows interfacing the DAC chip with an MCU or CPU address and data buses, and Figure 7.20(b) shows interfacing the ADC chip with 8051 ports.

Example 7.8

Show the programming steps for generating RAMP-like waveform.

Figure 7.21 shows the programming steps for generating a RAMP waveform output.

Considerations when Selecting or Using a DAC

Following are the considerations when selecting or using an ADC:

1. OPAMP amplifier or integrator: An amplifier converts the DAC current output into output voltage of actuator. An actuator is one that gives the output of voltage or current or frequency or power in accordance with physical value of analog input to control a parameter like pressure, temperature, light intensity, linear or angular position. The DAC and appropriate signal conditioner or amplifier generates the desired analog signal for actuator.
   

   Figure 7.20 (a) Interfacing the DAC Chip with any MCU or CPU Address and Data Buses AD0-AD7 and (b) Interfacing the ADC Chip with 8051 Ports

   

   Figure 7.21 Programming Steps for DAC Generating a RAMP Waveform Output

2. Conversion rate: This is for changing the analog outputs frequently and generating analog wave-form (for example, a ramp signal for a signal plotter) for higher conversion rate.
3. Number of analog output channels: The number of analog output channels may be required in a specific system like an automatic environment control plant or a robot with multiple degrees of freedom with a DC motor for each degree movements.
4. Reference signal: Reference signal precision affects the DAC precision. Hence, reference signal source circuit can be an important criterion.
5. Separation of analog and digital grounds: Digital ground carries noise. It arises due to the sharp 1 to 0 and 0 to 1 transitions in digital circuits. A decoupling capacitor is placed near the digital chips to reduce noise. The separation of analog and digital grounds is also done.

7.7 INTER-INTEGRATED CIRCUITS INTERFACING (I²C BUS STANDARD)

Interconnection Using a Bus

Advantage of doing interconnection using a bus is simplicity of wiring. Though several devices and systems or units are interconnected but only the destined unit accepts (receives) or sends (transmits) the data and others ignore the bus signals. Consider address and data buses. These are parallel buses as all address signals A0 to A15 are sent in parallel and all D0-D7 signals are parallel [Figure 1.1]. Parallel buses are difficult to use for interconnecting the remote units and devices.

Interconnection Using a Serial Bus

Advantage of doing interconnection using serial bus is that the interconnection of the units is done with one or two or four wires only. Only the destined unit accepts (receives) or sends (transmits) the data, and others ignore the serial signals

Interconnection Using a UART Serial Bus

One possible way, we have learnt for interprocessor serial communication in Section 3.6.3. We learnt how to use theSM2, TB8 and RB8 bits for serial bus communication and 8051 in UART mode This method is for the serial UART communication between interconnected 8051 MCUs only.

Interconnection Using a Synchronous Serial Bus

I²C synchronous serial bus is originally from Philips since 1970. It provides one of the standard methods (protocol). It serially interconnects the integrated circuits (ICs). It is popularly used in the serial communication networks of embedded devices.

It can be used for systems with multiple masters and slaves on the bus. Master means a smart device that can initiate data transfers. Slave means a device that acknowledges and responds to the request of the master device. A device can also work in master mode at one instance and in slave mode in another instance.

Built-in Interface for I²C Bus in 8051 Versions

A version of 8051 family may also have a built-in interface for I²C bus. There are two signals on I²C bus—SDA (serial data) and SCL (serial clock). Philips P83C528 is an 8051 version from Philips with P1.6 pin for SCL and P1.7 pin for SCL.

I²C Bus Signals and Serial Communication Rate

I²C bus operates at 100 kbps, 400 kpbs and 3.4 Mbps (2 m). Figure 7.22(a) shows I²C bus interface. There are two signals SDA (Serial Data) and SCL (Serial Clock) between 8051 and four I²C devices at P1.7 and P1.6, respectively.

The signals have internal pull ups. Internal pull up means the transistor at output stage internally connected to 5 V through a resistance to draw (pull) finite currents on logic 0 or 1. External bus current requirement increases when the multiple devices interconnect. Therefore, intervals of 1 μs between clock pulses and of 0.5 μs intervals between SDA and SCL increase. An external R = 1 kOhm to 2.2 kOhm pull up to 5 V with each of these signals can be additionally placed. This ensures that the intervals do not get extended because of loading.

Figure 7.22(b) shows the delay between the positive edges of SCL with respect to SDA.

Logic 1 is for ΔT = 4 μs in standard bus and for 0.6 μs in fast bus. Bit transmits during logic 1. Start bit is at logic 0. Start bit minimum interval ΔT is 1.3 μs in fast bus and 4.7 μs in standard bus. A protocol is used for sending the bits or bytes on a serial line. It gives the sequencing of the bits before and after the data bits.

I²C Bus Protocol

A protocol is followed for sending the bits or bytes on a serial line. It specifies sequencing of the bits before and after the data (message) bits. Assume one bit time interval = ΔT. Figure 7.23 shows the bits sequencing in I²C bus.

Protocol provides for addressing to slaves by a master and sending messages between the master and slave. (Addressed slave sends the response when master sends (places) the request for that on the bus). The following are the fields in bit sequences on I²C bus:

1. The master sends the output at SDA line for 8×ΔT for the first and second fields. First field is the start bit. Second field has next seven bits. These are bits for slave address. The maximum significance bit (msb) is sent first and least significance bit (lsb) at the last. Usually, four msbs can be used to specify the device type and the next three lsbs to select one of the 8 devices of that type. For example, 0010 specifies RF tuning control, 0100 audio tone generating device, 0011 PCM audio-interface and 1000 video-interface as the device type.
2. Third field has 1 control bit for ΔT. It specifies whether write or read cycle is in progress. The slave can put the acknowledgement bit after that during the fourth field. Master goes in input mode for SDA for that ACK bit time interval of AT. Fourth field thus specifies whether the present data is acknowledgement from slave.
3. Fifth field is of 8-bit data (or command) from master. Sixth field is 1 bit NACK (negative acknowledgement). If active, then it means acknowledgement not needed from the slave if transfer successful, else acknowledgement is expected from the slave.
4. The last (seventh) field is stop bit like in an UART.

Figure 7.24 shows the example of steps in programming of serial transfer from master and first and second fields in 8051 built-in I²C bus interface. Assume that there is only one master.

I²C bus is relatively slow. CAN (Controller Area Network) bus, USB (Universal Serial Bus) and IEEE 1394b are three other popular serial buses.

SUMMARY

1. External UART 8250 or USART 8251 are programmable serial communication devices. It can be interfaced to the DCE like a modem. It can be programmed for 1 or 2 or 1½ stop bit.
2. There are three modes of data transfer between the system memory and external peripherals: (a) busy and wait programmed IO, (b) interrupt- driven and (c) DMA controlled transfer.
3. External PPI 8255 is a programmable parallel ports device.
4. Ports can be programmed in the without handshake, handshake, bi-directional handshake modes.
5. DMAC 8257 is a four-channel DMAC that provides direct memory access channel to a device once it is programmed for DMA address (start address of the memory block) and terminal counts for that channel for that channel.
6. PIC 8259 is an interrupt controller for the eight interrupt request signals from the external devices. It can mask a request and has programmable priority resolver.
7. ADC 0804, 0808 and 0816 are the one, eight and sixteen channel ADCs. Each converts analog input into 8 bits. Analog input is from the sample hold amplifier. The voltage reference source, read-write logic and start and end of conversion circuits are required for the operations. Signals from transducer connect a signal conditioning circuit when measuring a physical parameter like temperature. The signal conditioner adjusts the range of analog input to the ADC.
8. DAC 808 is an 8-bit DAC. It has no internal command register and can thus directly interface the port bits also.
9. I²C is a synchronous serial bus that can be used to interconnect several masters and slaves in a microcontroller or ICs network.
10. CAN, USB and IEEE1394 are other device network interface protocols.

KEY TERMS

Actuator: A circuit that generates voltage or current or power or frequency in a system that controls physical conditions like temperature, pressure and sound. A loudspeaker is an example of actuator.

ADC: Analog-to-digital conversion after comparison with a reference voltage. When analog input equals one at +ve reference pin, the outputs are all 1s and when equal to one at the −ve reference pin, the outputs are all 0s.

CAN: Controller area network is a serial bus standard popular particularly devices and controllers networks in the automobile system.

Command instruction: A control byte or word written by a processor instruction into a programmable device to program the actions at the device, for example, enables the device by setting a bit or by resetting a bit. Control word(s): A byte or word written by a processor instruction into a programmable device to program the device modes and to command the device.

Conversion accuracy: With respect to a given reference voltage how accurate is the conversion in an ADC or DAC.

Conversion speed: How fast is the conversion in an ADC or DAC, it is measured by number of conversions successfully made per second.

Conversion time: With respect to a start of conversion signal, after how much time the conversion will be over and end of conversion interrupt generates.

DAC: Digital-to-analog converter after comparison with a reference voltage. The analog output equals reference when the input bits are all 1s and equals −ve reference when the bits are all 0s.

DACK: A signal generated as acknowledgement by the DMAC after a peripheral requests the DMA transfer. Data bus buffer: A buffer to hold a byte before it is read by the processor instruction or after it is written by the processor instruction.

DCE: Data communication equipment that uses a line or channel such as a mobile or wired or wireless link for communicating with the serial data. It interconnects the DTE. DCE example is a modem.

DMA address register: A register where the address of the memory is loaded to enable DMAC to read or write there by direct transfer, which takes place using the system buses when accessible.

DMA controller: A device to facilitate direct transfer of bytes between the system memory and external peripherals such as CD disk controller and hard disk controller and transfers the needed bulk data without frequent processor interrupt.

DRQ: A signal generated by peripheral for DMAC to request the DMA transfers and the DMAC sends back the DACK to enable the peripheral to start the transfer.

DTE: Data terminal equipment that uses a port like COM port (RS232C port) to link a line or channel like a telephone link using the DCE between. Example of DTE is an IBM PC.

Handshaking signals: Signals between a device and another device and one is for request and other is for acknowledgement of that request. Using handshaking signals and a control signal (interrupt), the device is able to transfer the bytes an in interrupt-driven mode or vice versa.

I²C bus: A synchronous serial bus for inter-integrated circuits communication.

In-service register: A register in 8259 to hold the bytes for a specific request being serviced by PIC.

Interrupt control signal: An interrupt to CPU after an output transfer is complete or after a input becomes available.

Interrupt mask register: A register in 8259 to hold the bits that are set for the requests that are masked and reset for those which are unmasked. For example, when bit 0 = 0, IRQ0 request is unmasked and when bit 4 = 1, IRQ4 request is masked.

Interrupt request register: A register in 8259 to hold the bits that are set for the requests that are pending and needing service and reset for those which are either serviced or not pending. For example, when bit 0 = 0, IRQ0 request is not pending and when bit 4 = 1, IRQ4 request is pending.

Keypad: A set of about 16 keys, for example, in a mobile phone or telephone or calculator to give input to the systems using a port(s) directly or through a keypad controller.

Mode instruction: A control byte or word written by a processor instruction into a programmable device to program the device mode by setting a bit(s) or by resetting a bit(s).

Modem control: The signals DSR (data set ready from DCE), DTR (data terminal ready from DTE), RTS (request to send from DTE), CTS (clear to send from DCE), RI (ring indicator), DCD (data carrier detect) are the modem control (by handshaking) signals between the DCE and DTE.

Parallel port: A port that can connect using data bus line to the processor and using IO pins to the external device (peripheral).

PIC: Programmable interrupt controller 8259 chip from Intel.

PPI: Programmable peripheral interface 8255 chip from Intel.

Priority resolver: A unit to resolve the priority before the service in a PIC or DMAC when there are several sources of interrupt or devices. Priority can be resolved in nested mode or rotation mode or specific rotation mode as per the control bits (operation command bits).

Protocol: A standard program or standard method by which the serial or parallel bits are sequenced on the line in a network.

PTS (peripheral transaction server): A DMAC called as PTS in 80960 and 80196 MCUs.

Reference signal: A signal acting a reference in an ADC or DAC. It is compared with the analog signal and ratio of that is as per the digital bits generated at outputs of ADC or inputs of DAC.

Sensor: An element or circuit used to modify the current or voltage or state of circuit according to the physical parameter such as light or pressure or magnetic field.

Signal conditioner: An amplifier, scalar, adder or integrator circuit so that the range of the outputs is between the maximum and minimum in order to get maximum conversion accuracy. For example, human body temperature can be between 98°F and 105°F. Signal conditioner can generate 0 V for 98°F and 2V for 105°F.

Status word: A word (byte or bytes) in a programmable device that is read by a processor instruction to get the current status of the device.

Stepper motor: A motor with four inputs and left or right shifting the bits rotate the motor by one step. For example, input 0001 changed to 0010 by shifting will rotate the motor by one step.

Stop bit: A mark bit (=1) for minimum one unit interval after a byte is communicated by an UART. Two stop bits mean two unit intervals and it is minimum time before the next byte can be started.

Synchronization character(s): Character(s) preceding the data bits. This enables synchronization of the receiver clock and also enables the use ofjust one serial line in place of two (SDA and SCLK).

Terminal count register: A register where the number of bytes are loaded to enable DMAC to read or write there by direct transfer, which takes place using the system buses when accessible. It decrements on each transfer. When it becomes 0 on continuous decrements, an interrupt or TC signal becomes active to enable the processor to intervene. Every decrease of TC by 128 can also generate a Mark signal, for example, in 8257.

Transducer: A unit to generate a transfer signal to enable the acquisition system to find the physical value of the parameter, like sound level, temperature. A microphone is an example of a transducer.

USB: Universal serial bus standard that enables us to connect the scanner, joystick and other devices serially. Devices can network in a tree-like structure also when using USB.

REVIEW QUESTIONS

1. If an MCU has asynchronous and synchronous communication interface, when do you need the additional 8251 USART chip?
2. List the programmable features of 8251.
3. List the various units within the 8251.
4. Describe the use of modem-control and read-write logic pins at 8251.
5. When do you need the additional 8255 PPI chip when an MCU has ports?
6. List the programmable features of 8255.
7. List the various units of 8255.
8. Describe the uses of 8255 read-write logic and Port C pins.
9. Explain with an example each of the following: busy and wait programmed IO, interrupt-driven and DMA controlled transfer modes.
10. When will you prefer DMAC 8257 and when do you prefer interrupt-driven transfers using 8255? [Hint: Consider the number of bytes that need to be transferred.]
11. How will you program Port A as a bi-directional port with handshake and interrupt control signals?
12. How will you program Port A and B for the programmed I/O transfer?
13. How will you interface the 8051 with the ADC 0816 using Port P0 and P2 for address and data buses?
14. List the programmable features of 8257.
15. List the various units within the 8257.
16. Describe the use of the 8257 read-write logic and control logic. Explain the mode set register subunit. Write the use of each 8257 pin. What is the possible application of mark pin to signal every 128th transfer?
17. Explain the uses mode set register bits of DMAC 8257.
18. How will you interface the 8051 and 8257 with two IO peripherals? Illustrate with a circuit diagram.
19. If an MCU has built-in interrupt-handling mechanism, when do we need the additional 8259 PIC?
20. List the programmable features of 8259.
21. List the various units within the 8259.
22. Describe the uses of 8259 internal registers.
23. Explain the use of cascading pins of 8259.
24. What are the merits and demerits of CMOS- based ADCs?
25. How do you interface ADC 0804 with the port pins of 8051?
26. What are the advantages of the (i) ADC with dual polarity analog inputs, and (ii) feasibility and internal programmability of both +ve and −ve reference voltages?
27. Describe DAC 808 circuit and its operation when interfaced to 8051.
28. How does the serial line differ from serial bus?
29. Describe all the bits during the serial transfer from the master in an I²C interface device.
30. List the advanced serial buses.

PRACTICE EXERCISES

1. How will you reprogram 8251 as 7-bit data, even parity and 1½ stop bit UART mode transmission with baud rate (one-sixteenth) of clock rate? (Assume address of data buffer 0060H and of control words 61H.)
2. How will you program the 8251 for 7-bit data, odd parity and two sync character byte as 11010010 and 00101101 USRT mode with bit-clock rate?
3. Make a table as follows. Command instruction bits that you will program in different modes of serial communication.
   
4. How will you interconnect the 8251 with a modem?
5. How will you interconnect the 8251 at the addresses F000H and F001H?
6. There are 8 motors (0th to 7th) in a robot for each degree of freedom. How will you interface these to switch the 3rd motor using the 8051 and 8255 direct bit set-reset mode?
7. There are 8 LEDs (0th to 7th) in a row. How will you interface these to show the time in minutes for which the washing is ON in a washing machine? Assume that time (in unit of a minute) stores at in a memory location 2000H. Use the 8051 and 8255 direct bit set-reset mode to switch 0 th LED flashing during the first minute, after the first minute, the LED is permanently ON and the 1st LED flashing, after the second minute the 0th and 1st LED are permanently ON and 2nd LED flashing.
8. How will you program the DMA address register and Terminal Count register of Ch0 and Ch1?
9. How will you mask the IRQ3 and IRQ4 in 8259?
10. Assume use of nested priority resolution in 8259. How will you allocate the IRQ pins for: Keypad, printer and timer interrupts?
    
11. Draw the interfacing circuit of 8257 with 8051 address and data buses. Assume Ch0 register starts from F020H.
12. How will you interface the 8051 with 8255 port bits connected to the ADC 0816?
13. Search the Web for an 8051 version having internal ADC with both +ve and -ve reference voltages internal programmability.
14. Search the Web and make a table for finding the following:
15. Search the Web and find five versions of MCUs with I²C bus interface pins.
16. Show the timing diagram for SDA and SCLK signals in I²C bus interface. Show the time slot in which the receiver acknowledgement is expected.

MULTIPLE CHOICE QUESTIONS

1. Which of the options is/are correct?
   1. 8251 can interface with the RS232C TxD and RxD while 8051 SI cannot
   2. Both can interface with the RS232C TxD and RxD
   3. 8051 provides both synchronous and asynchronous communication
   4. 8251 provides both synchronous and asynchronous communication with a modem or DCE control signals.
2. A 8251 mode instruction, two sync characters and command instruction programming will require
   1. four addresses
   2. two addresses
   3. eight addresses
   4. one address only
3. In 8251
   1. TxEmpty signal is at the external pin
   2. TxEmpty is a flag, which sets in the status register
   3. TxEmpty is a flag, which resets in the status register on transmitter buffer empty
   4. TxEmpty signal is at the external pin as well as sets a flag in the status register on Tx buffer empty.
4. 8255 Port’s A bit 7 is to be toggled (if 1 to be made 0 and if 0 then 1). Which of the following processor write instruction will do that?
   1. Send accumulator byte to Port A after XOR operation with 1000 0000
   2. Send accumulator byte to Port A after XOR operation with 0111 1111
   3. Send accumulator byte to Port A after subtracting with 1000 0000
   4. Use bit set-reset mode of 8255
5. 8255 Modes 0, 1 and 2 and bit set-reset mode are programmed by bits
   1. b7, b6 and b5
   2. b7, b6, b5 and b2
   3. b7
   4. b0-b7
6. 8255 control word bit 0 = 0 means
   1. Port C lower four bits as input in Mode 0 Group B
   2. PC0 as output
   3. Port C lowest bit as output in Mode 1 Group B
   4. Port C lower four bits as output in Mode 0 Group B
7. 8257 is for DMA transfer
   1. from peripheral to RAM
   2. from RAM to peripheral
   3. between peripheral and RAM
   4. between floppy disk controller and RAM
8. 8257 DMAC can transfer
   1. with Ch0 highest priority
   2. with Ch0 highest priority as well as rotating priority
   3. with Ch3 highest priority
   4. with Ch3 highest priority as well as rotating priority
9. 8059 PIC
   1. provides the interrupt type on D0-D7 in 80x86 mode of operation
   2. provides the interrupt vector LSB address on D0-D7 in 80x86 mode of operation
   3. provides the interrupt type on A0-A7 in 80x86 mode of operation
   4. provides the interrupt vector LSB address on A0-A7 in 80x86 mode of operation
10. 8259 mask register byte is written as 01010000. Then
    1. IRQ6 and IRQ4 are unmasked
    2. IRQ6 and IRQ4 are masked
    3. IRQ is unmasked and cannot be masked again
    4. IRQ6 and IRQ4 are masked and cannot be unmasked again
11. An ADC 0804 is measuring analog inputs up to 500 mV. Which one will you prefer?
    1. Use 1.023 V as (reference volatge/2) input and amplifier with a gain of 2
    2. Use 1.023 V as (reference volatge/2 ) input and amplifier with a gain of 4
    3. Use 1.023 V as (reference volatge) input and amplifier with a gain of 1
    4. Use 5 V as (reference volatge ) input and amplifier with a gain of 4
12. A DAC output uses a low pass filter
    1. for line noise filtering
    2. to reduce the effect of sharp 1 to 0 transition and 0 to 1 transitions at the DAC input
    3. to drive low frequency output
    4. to drive dc motor
13. Serial line for interprocess communication and serial bus differs in the following:
    1. serial bus can address several processors and type of devices with bus interface and inter connects multiple masters and slaves
    2. serial line cannot address the several processors
    3. serial line can connect up to 16 processors only
    4. serial bus can address several processors and type of devices with bus interface and inter connects a master with the multiple slaves
14. DMAC uses the bus access
    1. till the end of the TC is reached after which, it sends the hold signal to the processor
    2. uses the IO bus access only
    3. till the end of the TC is reached after which, it sends the processor the hold acknowledge signal
    4. during the intervals in which the bus access is provided at the regular intervals by the processor and when the latter does not need the buses

FILL IN THE BLANKS TYPE QUESTIONS

1. 1. 8251 _____ on power up reset.
2. 8251 _____ is a chip and is used for _____.
3. 8255 has _____ addresses, which are used for Port _____, _____, _____ and control word.
4. 8255 facilitates _____ set or reset of individual _____ at Port _____.
5. Number of handshaking signals when using 8225 Port as bi-directional buffer = _____ and their names are _____.
6. 8255 has total _____ port pins and _____ groups of ports.
7. Decoding circuit is used for _____ before a peripheral chip.
8. 8237 is used for _____.
9. Direct memory access advantage is _____ and it is used when _____.
10. 8259 is used for _____.
11. Functions of priority resolver in 8259 is _____.
12. Functions of in-service register in 8259 is _____.
13. Transducer is used for _____ and interfaces to ADC through _____ circuits.
14. Actuator is used for _____ and interfaces to DAC through _____ circuits.
15. Assume (V_ref+ − V_ref−) = 2.048 V, V_in = 1.2024 V. n = 8. The output of an ADC _____ _____ when V_in = 0.512 V.
16. (V_ref+ − V_ref−) = _____ when V_in = 1.024 V and n = 8 and output of an ADC = 10000000.
17. V_in = 0.024 V then output = 00000011. Resolution of the ADC is _____.
18. V_ref+ − V_ref− = V. n = 8, Digital input = 1000 0000 = 128 decimal. V_out =1.024 V.
19. The resolution of DAC is _____ when DAC input 00000010 gives analog output = 0.016 V?
20. I²C bus is used for _____. The time interval between SDA bits = _____.