The Long March to a Silicon-Photonics Union
Abstract
Electronics may be the driving force behind today’s technology, but increasingly it is calling upon optics for help. Silicon photonics promises to marry the two domains: electronics and photonics. The technology will benefit photonics by bringing it to the mass market while, working along with electronics, silicon photonics will benefit systems.
The two component industries—semiconductors and optics—have developed vastly different problem-solving methodologies and solutions. The semiconductor industry routinely integrates billions of electronic transistors on a chip, whereas photonic circuits use tens or hundreds of components at most. And while the component count on optical chips is rising, there is no photonic equivalent of Moore’s law.
Photonic circuits offer unprecedented bandwidth over a range of distances, from linking equipment within a data center to connecting sites across continents. With Moore’s law coming to an end and the bandwidth demands of the telecom and datacom industries showing no sign of abating, combining the strengths of semiconductors and photonics is set to benefit both industries.
Keywords
Moore’s law; CMOS; laser; optical waveguide; modulator; photodetector; fiber; gratings; silicon photonics
You can’t really understand what is going on now unless you understand what came before.
Steve Jobs [1]
By making things smaller, everything gets better. The performance of devices improves; the amount of power dissipated decreases; the reliability increases as we put more stuff on a single chip. It’s a marvelous deal.
Gordon E. Moore [2]
Photons and electrons are like cats and dogs. Electrons are dogs: they behave, they stick by you, they are loyal, they do exactly as you tell them, whereas cats are their own animals and they do what they like. And that is what photons are like.
Mehdi Asghari [3]
The exciting thing about silicon photonics is that it is the only vector for scaling after [transistor] dimensional shrink.
Lionel Kimerling [4]
3.1 Moore’s Law and 50 Years of the Chip Industry
It is rare for a trade magazine article to remain relevant for long, never mind 50 years after publication, nor is it often that an article’s observation becomes a law—one whose consequences for the semiconductor industry the author foresaw decades in advance.
The article in question is by chip pioneer Gordon E. Moore and appeared in Electronics in 1965 [5]. Dr. Moore was the director of the R&D labs at Fairchild Semiconductor, an early maker of transistors. He also went on to cofound Intel and was the company’s second CEO, following legendary chip pioneer Robert Noyce, the coinventor of the integrated circuit [1].
Moore’s article was written in the early days of integrated circuits. At the time, silicon wafers were 1 in. (25 mm) in diameter, and integrating 50 components on a chip was considered state of the art.
Moore observed that, in any period, there was an ideal number of components that could be included on a chip at a minimum cost. Add just a few more components and the balance would tip: the design would become overly complex, wafer yields would drop, and costs would rise.
His key insight, to become known as Moore’s law, was that the complexity of an integrated circuit at this minimum cost was advancing over time. Moore expected this complexity to double each year for at least another decade.
He also predicted that, by 1970, the manufacturing cost per component would be a tenth of the cost in 1965. Extrapolating the trend further, Moore believed that by 1975, the number of components per integrated circuit for this minimum cost would be 65,000 components. Moore was overly optimistic, but only just: by 1975, Intel was developing a chip with 32,000 transistors.
Moore amended his law in 1975 to predict a doubling of complexity every 24 months. Moore’s article talked about components, the basic elements of electrical circuits: transistors, resistors, and capacitors. But by 1975 the industry was focused on the transistor, which had become the building block for all the required circuit elements. The industry was also starting to alight on complementary metal-oxide semiconductor (CMOS) technology to make chips. And in the years that followed 1975, the period of complexity doubling became every 18 months.
Moore showed remarkable foresight regarding the importance of integrated circuits, especially when, in 1965, their merits were far from obvious. Such devices would bring a proliferation of electronics, he said, “pushing this science into many new areas.”
He foresaw home computers (or at least “terminals connected to a central computer”), automatic control for automobiles, and even the mobile phone—personal portable communications equipment, as he called it.
The biggest potential of chips, he said, would be in the making of systems, with Moore highlighting computing, telephone communications, and switches. Fifty years on, such systems underpin datacom and telecom.
3.1.1 The Shrinking Transistor—But Not for Much Longer
The shrinking of the transistor has continued since Gordon E. Moore published his 1965 article, with remarkable technological and economic consequences [6].
The cost of making a transistor in 1965 was $30 in today’s currency; in 2016 it is one billionth of a dollar. And in 2014, the semiconductor industry made 250 billion billion transistors, more than were made in all the years of the semiconductor industry up to 2011 [7].
As explained in the 50th anniversary issue on Moore’s law in the IEEE Spectrum magazine, the miniaturization of transistors to date has been achieved with much engineering ingenuity and investment. Device yield—the proportion of working chips that come from a given wafer—has gone up from 20% in the 1970s to between 80% and 90% today. The size of the silicon wafers on which the chips are made has also increased, from 200 mm (8 in.) to 300 mm (12 in.). And while the lithography tools now cost 100 times more than they did 35 years ago, they also pattern the large wafers 100 times faster [7].
But the shrinking of the transistor cannot continue indefinitely, especially as certain transistor dimensions approach the atomic scale. Each new generation of CMOS process node is defined around a feature size of a transistor based on its gate length. Voltage is applied to the gate to turn the transistor off and on.
Leading chip companies are now using a 14-nm CMOS node to make their chips and are already targeting a 7-nm CMOS process [8]. The Belgium semiconductor research center, imec, is working on 7-, 5-, and 3-nm feature-size CMOS process technologies and claims that it sees a clear roadmap to achieve the 3-nm target [9].
But the industry is fast approaching the point where fewer benefits remain associated with smaller-sized transistors. Even the cost of making a transistor has stopped declining, with the transition point being around 28-nm CMOS (see Fig. 3.1) [10].
Silicon manufacturing innovation will continue and transistors will shrink further. But no longer does the latest CMOS process deliver both improved performance and cheaper transistors.
The International Technology Roadmap for Semiconductors (ITRS) is an organization sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. In its 2015 report [11], it describes how the physical gate length of the transistor is set to remain at 10 nm from 2021 (see Fig. 3.2) ostensibly signaling the end of Moore’s law. Smaller CMOS process nodes will continue to be developed, but the shrinking of the transistor gate length is almost done.
3.1.2 Post-Moore’s Law: The Future of Optics and the Future of Chips
The industry may debate how many years of Moore’s law are left, but it hardly matters. Moore’s law has done a remarkable job, bringing the chip industry a half-century-long bounty such that it can now employ billions of transistors for integrated circuit designs [12].
To keep advancing computing performance beyond Moore’s law, new thinking is required on many levels, from materials and circuit design to architectures and systems.
IBM illustrated this new thinking when it announced in 2014 a $3 billion research program over 5 years to extend chip development [13]. Areas it is exploring include quantum computing, neurosynaptic computing (a style of computing that mimics the brain) [14], III-V materials (combinations of column III and column V elements of the periodic table) to speed up electron mobility, carbon nanotubes, graphene, next-generation low-power transistors, and silicon photonics.
Like IBM, the industry group the ITRS recognizes that Moore’s Law needs a rethink. The organization, as suggested by the name, regularly published future roadmaps for the chip industry based on the relentless scaling progress reflected in Moore’s law. But in 2012 it became clear to the ITRS that the model was broken and a rethink was needed.
It resulted in the revamping of the organization, which became the ITRS 2.0, and it replaced its 17 International Technology Working Groups with seven focus teams (see Table 3.1) with an agenda of charting the chip industry’s progress over the next 15 years: 2015–30 [11].
Table 3.1
The ITRS 2.0’s Seven Focus Teams
| ITRS 2.0 Focus Teams | Comment |
| System Integration | Studies and recommends system architectures for the semiconductor industry for applications such as mobile, the data center and the Internet of Things |
| Heterogeneous Integration | The combination of differently manufactured components to create a packaged design with enhanced functionality |
| Heterogeneous Components | Micro and nano fabrication technologies that will be needed to create components for heterogeneous systems |
| Outside System Connectivity | Technologies to connect different parts of systems—such as wireless but also optical interconnect |
| More Moore | Developments to keep shrinking horizontal and vertical physical feature sizes for reduced cost and improved performance |
| Beyond CMOS | Identifying technologies to extend CMOS using heterogeneous integration, as well as new information processing approaches |
| Factory Integration | Tools needed to ensure that the semiconductor industry can continue to produce cost-effective designs in volume |
Source: ITRS
Only one of the seven focus teams is looking at techniques to extend Moore’s law. The remaining six are concerned with a wide range of techniques and technologies that the industry will need to keep progressing computing and related technologies now that Moore’s law is ending.
Interestingly, silicon photonics can play a role in six of the seven focus areas.
Mention of silicon photonics returns us to Gordon E. Moore’s 1965 article. The article opened with a bold and prescient statement: “The future of integrated electronics is the future of electronics itself.”
Can the same be said of photonics? Is the future of integrated photonics the future of photonics itself?
The answer is yes. While the bulk of optical components made today are not integrated [15], integrated devices will play an increasingly important role going forward. Integrated photonic circuits will be increasingly required as transmission speeds rise in the data center and for long-haul optical transport.
Photonic integrated circuits are different from electronic integrated circuits. Photonics uses several optical building blocks to make an integrated circuit (as described in Section 3.4), whereas electronics uses one, the transistor, as the basis of all chips. And while shrinking photonic functions does not deliver continual optical performance benefits as the shrinking of transistors has, integration of photonics using silicon promises to lower the cost of devices.
Refining the statement further: instead of integrated photonics, is the future of silicon photonics the future of photonics itself?
Here, as implied by IBM’s investment program, the answer is that silicon photonics is bigger than photonics itself. Silicon photonics can be viewed as a semiconductor technology. A more accurate statement, therefore, is that the future of silicon photonics is the future of electronics itself, or at least one of its futures.
But there is another consequence, as we argue in Chapter 8, The Likely Course of Silicon Photonics, that the chip industry is the future of photonics itself.
3.2 How Photonics Can Benefit Semiconductors
The semiconductor industry’s billion-fold increase in transistor count over the past half-century has resulted in huge improvements to manufacturing techniques.
Large 300-mm silicon wafers—the size of a family pizza—are patterned and processed in controlled environments known as clean rooms to make chips with high yields. The industry also has advanced testing techniques to check that each chip is working while it is still on the wafer, as well as chip packaging technologies that can also benefit silicon photonics.
But now that Moore’s law is faltering, chip manufacturing is becoming trickier. Transistors continue to shrink, but the speed at which chips are clocked is no longer rising.
Up till a decade ago, smaller transistors meant faster and cheaper transistors. Microprocessors—chips designed to run software—in particular made good use of the greater number of transistors to make more complex designs that could also be clocked faster. But this inevitably raised the chip’s power consumption—an acceptable outcome for a costly device like a microprocessor until the thermal limits of integrated circuits started to be approached.
The industry then faced a tough decision: either to keep increasing the number of transistors or keep raising the clock speed at which the transistors are switched on and off, but not both. Chip designers chose to benefit from a greater transistor count with each process node and stopped ramping up the clock. As a result, processor clock speeds have stalled at a few gigahertz [16].
Processor designers are using the extra transistors to include several central processing units or processing cores on a chip to boost overall computing performance. Tasks are partitioned and distributed across the cores and processed in parallel. But some operations are inherently serial such that having multiple cores does nothing to accelerate the processing of code. Cores can thus be idle at times.
Designers must also contend with heat and power consumption issues as chips grow in complexity. And the continual need for higher processing performance raises system design issues. As chips advance, they need to be fed ever-increasing amounts of data, especially as the number of cores on a chip grows. EZchip, now part of Mellanox, is developing a networking chip that uses 100 ARM processor cores [17]. And a team at the University of California, Davis, Department of Electrical and Computer Engineering, has developed a chip containing 1000 independent programmable cores [18].
Multicore chip designs require faster internal data buses and more sophisticated hierarchical memory schemes, where the most important data is keep closest to a core in a high-speed on-chip store while the slower, larger memory located off-chip houses less urgent data (see Fig. 3.3). The chips also need to send and receive data, and this input–output is also getting faster over time.
All these requirements add to the chip’s design complexity and overall power consumption. Fortunately, photonics can address many of these issues, in particular power and data input–output issues.
An optical waveguide, unlike a metal trace or a copper wire, does not suffer heating due to resistance. In turn, the resistance and capacitance of metal traces that connect different parts of a chip determine signal delay and hence signal speed, whereas the speed of light through an optical waveguide is a function of the speed of light divided by the waveguide’s refractive index.
And as the electrical signal speed increases, whether due to a faster input–output signal or a faster internal bus, the distance the signal travels diminishes. Optical transmission offers information-carrying capacity and distances that far exceed those of electrical transmission.
Indeed, the reach of optical communication offers the intriguing prospect of separating device functions to reduce the heat concentration without the equivalent of having to consume additional power to transmit electrons over distances in the electrical domain. In this way photonics can benefit chip design and enable novel system designs. An example of such a system is the disaggregated server, a topic discussed in Chapter 7, Data Center Architectures and Opportunities for Silicon Photonics.
For all these reasons, if integrated circuits are to evolve, comingling optical component technology with electronics makes sense.
3.2.1 Adapting Silicon for Optics
The optical component industry is much less mature than the chip industry and makes nowhere near the same unit volumes each year. And while there is a need for greater integration, the industry has no Moore’s law driving relentless progress.
Optical components are made using materials such as indium phosphide, gallium arsenide, lithium niobate, and silica—a naturally occurring oxidized mineral source of silicon in the form of silicon dioxide. The idea of using silicon for photonics appeared radical at first, but the success of the semiconductor industry had long been noted by the optical industry, and silicon started to be researched for photonics and even as a single substrate to combine electronics with optics.
It turns out that silicon is an excellent material for optics. It is an abundant material and, thanks to the chip industry, is well understood. Silicon also has helpful material characteristics: it has good thermal properties as well as electrical ones. Silicon can be easily oxidized, as mentioned, and benefits from 300-mm silicon-on-insulator wafers developed for the CMOS industry. Such wafers are ideal for optics as they host silicon and silicon dioxide layers, ideal for optical waveguides to guide light as detailed in Section 3.4.1.
But to get silicon to work for optics has taken years of research effort. The good news is that silicon photonics is now moving to commercialization, and the design work that will deliver new devices and systems is in progress. These themes are discussed in Chapter 4, The Route to Market for Silicon Photonics.
3.3 Silicon Photonics: From Building Blocks to Superchips
The early research into optical components in the 1970s involved materials that now form the bedrock of optical communications.
Lithium niobate is one such material, used to modulate light for long-haul transmission since its optical properties—its refractive index—can be changed with the application of an electric field.
Modulation is used to transmit data over a transmission medium—fiber, optical waveguides, and even free space in the case of photonics—a task of key importance in communications. The modulator changes, or modulates, a particular parameter of a carrier signal. The carrier’s signal role is to match the communication medium’s characteristics. The modulator can change the carrier signal’s amplitude, phase, or frequency, or combinations of these parameters. The modulator encodes the data to be sent by modifying one or more of the carrier signal’s parameters. At the destination, the changes in the carrier signal are noted and the data is recovered. For optics, a modulator typically affects the amplitude or amplitude and phase of the light signal. Silicon photonics modulation is discussed in Section 3.4.2.
Other core optical materials include indium phosphide and gallium arsenide, III-V compounds that are ideal for generating, modulating, and detecting light. Indium phosphide has become the optical industry’s monolithic photonic chip platform of choice due to its ability to implement all the main optical functions: laser, modulator, waveguide, and photodetector. Not surprisingly, it is the key-established technology that newcomer silicon photonics must compete with.
Research into the suitability of silicon for photonic circuits only began in the mid-1980s. What deterred progress until then was the fact that silicon does not lase; unlike indium phosphide and gallium arsenide, silicon is very inefficient at emitting light. Equally, silicon, unlike lithium niobate, does not exhibit the same linear electrooptic effect where its refractive index can be changed with an electric field. Thus silicon alone cannot be used as a laser source—a considerable negative—and at first glance, silicon looked unpromising as a modulator technology [19].
Once silicon photonics research started, a top-down concept—using silicon to make a monolithic superchip—was proposed. Such a chip, referred to as an optoelectronic integrated circuit, would combine optical functions with electrical circuits, as outlined by the founding father of silicon photonics, Professor Richard Soref [20]. This showed the potential of what could be offered: an integrated device combining electronics and optics (see Fig. 3.4).
The proposed superchip’s optical functions were rich. The optical functions included waveguides, modulators, photodetectors, light sources, switches, and amplifiers. There were also built-in structures to aid the coupling of fiber to the chip.
The superchip’s electrical circuits included a range of specialist transistor types. These included the HBT (Heterojunction Bipolar Transistor) and HEMT (High Electron Mobility Transistor), which are used for radio frequencies and millimeter wave frequencies, respectively. Another transistor technology is BiCMOS, which is used to process the received optical signals. BiCMOS combines two transistor types: bipolar and CMOS transistors. BiCMOS is a faster transistor technology than CMOS alone and was used to make advanced microprocessors for mainframes [16] and is used for radio designs.
But to be able to implement such a superchip, a bottoms-up approach would be needed: to develop the chip’s basic building-block optical functions using silicon-based optics. First, techniques needed to be refined to improve the optical performance of each of the functions. And once the devices reached an acceptable performance, the challenge would be to combine them to create optical systems without compromising their individual optical performance.
These basic silicon photonics building blocks are discussed in the remainder of the chapter.
3.4 The Building Blocks of Silicon Photonics Integrated Circuits
There are two approaches used to combine optical functions to make integrated optical devices: monolithic integration and hybrid integration.
• Monolithic integration refers to a chip where the optical functions are all implemented using the same material system such as indium phosphide or gallium arsenide. Examples include an externally modulated laser that combines the laser and modulator or Infinera’s latest 1.2 terabit photonic integrated circuit that combines hundreds of optical functions [21]. It is also possible to implement an optoelectronic IC monolithically. Such circuits typically combine the photonics with driver and receiver electronic circuitry.
• Hybrid integration involves constructing a photonic integrated circuit using two or more materials. The advantage of the hybrid approach is that the best material can be used for each individual optical function. But the different materials need to be combined, presenting its own design and manufacturing challenges.
Silicon photonics can implement hybrid or monolithic designs. Since silicon cannot lase, a silicon photonics monolithic chip is one that combines various optical functions but not the laser; if the circuit requires a laser, the design can only be a hybrid implementation. Silicon photonics has been used to make complex optical circuits and optical circuits combined with electronics. But such circuits typically require the laser and that means a hybrid design with the laser coupled to the chip.
However, using a hybrid technique known as heterogeneous integration, the laser can be bonded onto the silicon during the device’s manufacturing. According to Professor John Bowers, bonding to silicon is attractive as it enables the integration of optical features that have not been widely integrated using any other platform [22]. These include not only lasers but also other active devices such as modulators and photodetectors, as well as passive functions such as optical isolators and circulators.
Moreover, using heterogeneous integration results in a single chip. The chip is made using hybrid integration in which two or more materials are used—e.g., silicon and indium phosphide—but the result is a chip with the laser integrated and aligned with other optical functions, just like a monolithic photonic integrated circuit.
In summary, silicon photonics chips can be implemented using monolithic or hybrid integration. However, if the photonic circuit requires a light source, the silicon photonics design is a hybrid one: either the laser is externally coupled, or bonded onto the silicon using heterogeneous integration. However, using heterogeneous integration results in a single die; it has all the attributes of a monolithic chip except two materials were used for its construction. Hence the overlap of heterogeneous integration with monolithic integration is shown in Fig. 3.5.
Having discussed how silicon photonics is used to make optically integrated circuits, it is time to discuss the building blocks used to make optical integrated circuits.
When sending data optically between two points, there needs to be a light source—a laser—a modulator, and a photodetector. In a photonic integrated circuit, optical waveguides are used to guide the light between the different optical functions. If data is to be sent in both directions, each end of the link has to have the transmitter (laser and modulator) and receiver (photodetector) functions. Such an optical system is referred to as a transceiver (see Appendix 1, Optical Communications Primer).
Of these optical building-block functions—the light source, waveguide, modulator, and photodetector—arguably the most important and simplest is the optical waveguide, as it forms the basis of the three other optical functions (see Fig. 3.6).
3.4.1 The Optical Waveguide
An optical waveguide routes light down a low-loss path. In effect the waveguide plays a similar role to optical fiber, except the waveguide is part of the silicon photonics chip. Like fiber, the light is confined using two materials with contrasting refractive indexes. The silicon-on-insulator wafers with their layers of silicon and silicon dioxide are ideal for constructing optical waveguides given the large refractive index contrast between the two: silicon has a refractive index of 3.5, while silicon dioxide’s is 1.6 [23].
Two common waveguide structures are the channel or strip waveguide, and the rib waveguide.
The channel waveguide is a strip of silicon surrounded by oxide—cladding from above and a buried oxide from below. In contrast, the rib waveguide is shaped like an inverted T with a wide silicon base on which sits a narrower silicon ridge.
The typical dimensions of the waveguide are sub-micron—several hundred nanometers wide and high. There is a trade-off between waveguide density on a chip and how lossy the waveguide is. Waveguides larger than a micron have lower loss, but their size limits the number that can be crammed on a chip. Submicron waveguides, in contrast, increase device density but are lossier.
The roughness of a waveguide’s sidewalls is also a factor when it comes to light loss. The loss arises due to light scattering; smoothing the sidewalls reduces this loss. Another approach is crafting the geometry of the waveguide such that the strength of the light on the sidewalls is reduced. Typical losses for high-confinement waveguides are of the order of 2 dB/cm [24], although some companies report lower losses.
3.4.2 Modulation
Modulation is used to imprint information onto light prior to transmission, as described in Section 3.3. A silicon photonics modulator sits in front of the laser and either impedes or passes light. This is done by altering the modulator’s optical properties—either its refractive index, which can be used to affect the speed of the light to enable interference between two light paths, or its absorption coefficient, a measure of the modulator’s light blocking ability.
Desirable modulator characteristics include a small size to allow more optical channels to be crammed on a chip. The modulator also needs to be of low-power, operate over a wide range of wavelengths to enable wavelength-division multiplexing, have low insertion loss, and be of high-speed that typically means working at speeds of at least 50 Gb/s.
If it is the modulator’s refractive index that is changed, two common modulator structures are used: the Mach–Zehnder interferometer and the ring resonator. These designs modify the refractive index and use phase changes in the light to create either constructive or destructive interference to induce light intensity changes.
Mach–Zehnder modulators have been optimized dramatically over the past decade and now work at high bit rates, but they are physically large—1 mm or more. Silicon photonics designs using a Mach–Zehnder structure have already been demonstrated for long-haul transmission.
Ring resonators are far more compact and have been shown to work at 50 Gb/s. But they are wavelength-specific and thermally dependent: a 1°C temperature change can detune the ring’s resonance from the laser’s wavelength. Ranovus is one silicon photonics player using ring resonator modulators for its optical transceiver products.
The second approach, changing the modulator’s absorption coefficient, uses an electric field to vary the absorption coefficient of the material. Electroabsorption modulators use silicon germanium or indium phosphide and meet the small footprint requirement. Such modulators also have a small capacitance and achieve broadband operation.
Capacitance is important because it defines the modulator’s maximum data rate as well as insertion loss: how much light power is lost passing through the modulator. Capacitance also dictates the modulator’s extinction ratio: the ratio in decibels of the modulator’s output light in the on and off states. The bigger the extinction ratio, the better. However, the resulting capacitance generally requires a trade-off between the modulator’s various performance metrics [25].
The characteristics of the main three silicon photonics modulator types are summarized in Table 3.2.
Table 3.2
| Mach–Zehnder | Ring Resonator | Electroabsorption | |
| Optical mechanism | Refractive index | Refractive index | Absorption coefficient |
| Comments | Speeds of 50 Gb/s demonstrated but has relatively large dimensions—1 mm—that limit future scaling | Small size and reduced capacitance compared to the Mach–Zehnder. Also demonstrated at 50 Gb/s. Its lower capacitance means a reduced dynamic power consumption | Small footprint and small capacitance |
| The modulator also has a relatively large capacitance, which limits its speed of operation and future power consumption reductions | The design must be thermally stable to ensure that its resonance frequency does not drift | Demonstrated operating above 50 Gb/s | |
| Has a level of thermal robustness and works over a broadband of wavelength (tens of nanometers). But the design drifts with temperature, ~0.8 nm/°C |
3.4.3 Photodetection
Photodetectors are a critical component at the optical receiver. This optical functional block converts the received light into an electrical current. Compactness, as with the modulator, is important, as is its bandwidth or speed of operation. A key defining performance parameter of the photodetector is its responsivity—the electric current output that results as a function of a unit of optical power (amp/watt) on the photodetector.
To add the photodetector function to silicon, germanium is added through doping the chip. Alternatively, an external material such as an indium phosphide photodetector can be added using hybrid or heterogeneous integration.
3.4.4 The Light Source
The light source is the critical component of any optical communication link and it is the silicon’s biggest shortfall. Because silicon is an indirect bandgap material, much work has been undertaken to enable silicon to lase. For now, silicon photonics players have circumvented the material’s limitations and use either an external laser coupled to the silicon photonics chip or use hybrid integration by bonding a III-V laser.
One advantage of using an external laser is its separation from the chip: a laser generates heat, and separating it makes temperature management easier. Lasers are also a mature optical component technology with a wide choice of suppliers.
Adding a laser to the photonic chip represents a manufacturing challenge; coupling a laser to the chip has ramifications regarding a design’s optical performance and cost. For an optical transceiver design, the laser-attach approaches include coupling a discrete laser to the chip (attached on-chip or off-chip via fiber) or adding a lasing material on the wafer using hybrid integration (see Fig. 3.7).
A standalone laser is independent of the silicon chip fabrication process. Because the performance and reliability of the discrete laser are already known, the design only needs to be tested once the laser is attached. However, accurate alignment of the laser to the chip is a must, and this is cumbersome, especially as the number of channels (laser count) grows.
The second, hybrid approach, also known as heterogeneous integration, involves attaching indium phosphide to the silicon wafer. Either indium phosphide wafers 50 mm and 75 mm in diameter are bonded to the 300-mm silicon wafer, or “chiplets”—slivers of indium phosphide—are located where needed on the wafer before the two materials are processed in situ [25,26].
The hybrid approach uses wafer-scale processing, with alignment of the laser to the waveguide part of the wafer fabrication process. This makes hybrid better suited for larger-volume applications and for circuits that have higher channel counts. Note that it also leads to lower coupling loss (and, therefore, lower power consumption for the circuit), lower cost, and the opportunity to leverage the silicon structure for more complicated laser functionality such as wide tunability. And since the lasers are buried, they are inherently hermetic. However, the laser cannot be tested until the entire device is assembled.
A third approach, promising the highest efficiency and most suited for volume applications, is to grow indium phosphide directly onto the silicon wafer. Silicon and indium phosphide have different crystal structures such that growing one on the other gives rise to defects. However, researchers are working to localize the defects to create working lasers. Such a monolithic approach remains a challenge, and further research is needed before this is ready for commercialization [25,27].
The light source’s impact on overall cost and optical performance is summarized in Table 3.3.
Table 3.3
Impact on Cost and Performance Using a Discrete, Hybrid, or Monolithic Laser Approach
| Bill of Materials Cost | Processing Cost | Testing Cost | Assembly Cost | Performance Issues | |
| Standalone laser | Purchased device, may need hermetic package, a lens, and isolator | Two separate processes | Test laser, test device, and test laser attached to device | Couple laser to silicon waveguide | Known, trusted, understood, can put laser anywhere, and thermally manage |
| Hybrid laser | Material cost, intrinsically hermetic, lens and isolators not needed | Laser wafer material process and waveguide processes | Test device at wafer level | Wafer bonding or chiplet placement | Performance only known on device completion. Thermal management |
| Laser integrated with waveguide in wafer processing | |||||
| Monolithic laser | Material cost. Indium phosphide growth | One process | Test device at wafer level | Laser integrated with waveguide in wafer processing | Performance only known on device completion. Thermal management |
Devices commercialized by Acacia, Cisco, and Luxtera all use discrete lasers. This is currently the most pragmatic approach and has enabled the companies to get products to market.
The hybrid approach promises lower bill-of-material costs, wafer-scale testing, and fewer assembly steps overall, which reduces overall cost. But the processing is a challenge. The laser is part of the chip and subject to the chip’s high temperature, raising thermal management issues. And yields will be low initially, harming the overall economics. Juniper Networks, Skorpios, and Intel are all pursuing the hybrid approach. Intel’s first commercial products using heterogeneous integration are 100 Gb optical transceivers [28]. As Intel points out, no alignment is needed; the laser is aligned during the silicon chip’s manufacturing using photolithography.
3.4.5 Fibering the Chip
The photonics chip has to be connected optically to the outside world, independent of how the laser is attached. Fiber is used to bring light to and from the chip. In addition, fiber is also an option to attach a laser to the silicon chip.
Attaching fiber to the chip remains the biggest manufacturing challenge for silicon photonics, because optical loss must be minimized in the coupling process to ensure acceptable optical performance.
Coupling fiber to a silicon waveguide is challenging because of the different densities of the confined light, referred to as the mode field diameter mismatch. Light is tightly confined in silicon due to the large refractive index difference between the silicon core and the silica cladding. The resulting core is less than 1 µm in diameter. In contrast, the optical fiber core is about 9 µm with a considerably smaller refractive index difference between the germanium-doped core and the silica cladding. Fig. 3.8 shows the core size differences and the challenge.
Two approaches are used to get light on or off the chip: edge coupling and grating coupling.
Edge coupling is used to butt-couple fiber—or a laser for that matter—to the silicon waveguide. Here the light from the fiber propagates in the same plane as the waveguide. Given the large refractive index difference between the chip’s silicon core and the silica cladding, the beam of light—its mode field—is considerably smaller in a silicon chip than in the optical fiber. A mode-matching technique is needed, such as the inverse taper shown in Fig. 3.9. Here, the silicon waveguide is tapered to gradually match the transition between the two mode field diameters.
As the name implies, a grating coupler requires a grating to be created within the silicon waveguide (Fig. 3.10). The gratings can be broadband, and the approach is attractive because it can be designed with little back-reflection. The coupler can be placed anywhere on the chip, the spot is large and hence it enables easy alignment with the fiber, and the grating supports wafer testing. Here, light is delivered to the grating vertically, perpendicular to the waveguide plane.
Neither coupling technique has yet demonstrated a proven optical performance advantage to become the de facto approach. Designers thus continue to assess which approach best suits their particular designs.
In summary, Table 3.4 lists the main optical functions and their performance issues.
Table 3.4
Optical Functions and Their Performance Issues
| Optical Function | CMOS-Compatible Processing | Optical Performance |
| Laser | Cannot be implemented in silicon. Requires a III-V compound such as indium phosphide either bonded to the silicon wafer or an off-chip laser coupled to the silicon chip | 1310 and 1550 nm wavelengths demonstrated. Multichannel design—wavelength-division multiplexing—has also been demonstrated |
| Modulator | Can be implemented in silicon. Also other materials such as indium phosphide can be bonded and used | Low power, 50 gigabit per second modulation speeds demonstrated. Different modulators available, each with its own merits and shortfalls |
| Waveguide | The size of the silicon waveguide and hence the interface density (how many can be placed side by side) is determined by the diffraction limit of light | Waveguide surface roughness can impact signal loss. There is also insertion loss when coupled to fiber due to mode field mismatch |
| Photodetector | Requires germanium doping | No obvious issues |
Having introduced the key silicon photonics building blocks, the companies and individuals that have helped bring these optical functions to maturity are discussed in Chapter 4, The Route to Market for Silicon Photonics. The history is a recent one, highlighting how rapid silicon photonics’ progress has been. The commercial impact of silicon photonics to date and the challenges facing the technology are also discussed in Chapter 4, The Route to Market for Silicon Photonics.