15.1.1 Design Robustness and Reliability

There are two classes of SoC design specifications to address for product lifetime operation: (1) robust design, in the presence of circuit changes due to parameter drift or noise sources, and (2) reliability, due to failure mechanisms.

Robust design refers to the steps taken to maintain functionality during the operational lifetime. For example, the SoC is subject to high-energy incident particles, either from extraterrestrial sources or radioactive decay of (trace) materials in electronic packages. (Since the initial identification of radioactive decay alpha particles as a major source of soft errors in DRAM modules, package and die attach materials have been modified, reducing this particle flux substantially.) These particles traversing through the die may result in a “collision” and the generation of free electrons and holes. A sufficient concentration of particle collision-related free charge near a sensitive circuit node may disrupt a stored logic value. The soft error rate (SER) in the SoC circuitry can be minimized through robust circuit and layout design so that the magnitude of free charge collection does not cause a flip in stored value (see Section 16.3).

Section 4.2 highlights device-level operational effects that result in parameter drift and device current degradation (e.g., hot carrier injection, bias temperature instability). The SoC methodology team needs to evaluate these device model impacts and establish an appropriate design strategy to maintain functionality. In addition, analog mixed-signal IP needs to ensure proper behavior in response to device noise mechanisms (e.g., thermal, shot, and flicker noise).

Design robustness addresses maintaining the correct circuit response to electrical disruption during operation. SoC reliability relates to wearout mechanisms, typically associated with material stresses that result in (significant) changes in material properties or mechanical fractures. As mentioned earlier, thermal cycling exerts stress on the die and package attach materials due to coefficient of thermal expansion differences; over time, a material fracture may result in a (catastrophic) failure. The major reliability issue within the die relates to electromigration (EM). This chapter briefly reviews EM as a failure mechanism and techniques to evaluate the related die failure rate.

15.1.2 MTTF and FIT Rate Specification

The end customer market for the SoC design defines the acceptable chip failure rate specification over the product lifetime. The SoC methodology and package engineering teams need to demonstrate that these specifications will be met, whether for consumer, automotive, medical, or aerospace applications. There are two common metrics to represent SoC reliability: the mean time to failure (MTTF; this acronym is also used for median time to failure) and the FIT rate.

Mean Time to Failure

Given a population of parts, the MTTF is the expected (mean) time until a part no longer meets the functional specifications. Specifically, if the failure probability density function is denoted as f(t), the expression for the MTTF is given in Figure 15.1.

The failure probability function is related to several other metrics:

• The reliability function, R(t)—R(t) is also referred to as the survival function, as it is the probability of the part surviving until time t:

  R(t)=1−F(t)(Eqn. 15.1)

  where F(t) is in the integral of the failure probability—namely, the cumulative density function (CDF) of the probability density function, f(t).

• The hazard rate, h(t)—The hazard rate at time t is the (conditional) probability of failure among the remaining part population that has survived to time t. Mathematically, the hazard rate is represented by:

  h(t)=f(t)/1(1−F(t))=f(t)/R(t)(Eqn. 15.2)

• The failure rate—In general, the failure rate is the probability that a product will fail at time t among the remaining product population, and the broadest definition includes repaired products that remain in the population. As a failed SoC is not repairable, the hazard rate and failure rate are equivalent. The term failure rate is used in the subsequent discussion, denoted as h(t); the notation f(t) refers to the failure probability density function as opposed to the failure rate.

Failure rate data are measured from a sample and thus represent an estimate of the total population. For reliability calculations due to electromigration, the sample data are derived from fabricated testsites that allow specific failure mechanisms to be isolated. This reliability data is included as part of the foundry PDK release.

The mean time to failure measure is often replaced by median time to failure (also, confusingly, denoted MTTF), which is the solution to the integral in Figure 15.2.

The median time to failure is perhaps a more meaningful metric, given the very asymmetric nature of the typical failure rate function for microelectronics. Figure 15.3 depicts a bathtub curve to illustrate the SoC population failures over time. (Note that infant fails are ideally screened and removed by burn-in stress testing, as discussed in Section 21.1.)

The probability density function f(t) associated with the bathtub curve failure rate h(t) is skewed. A composite Weibull distribution is often used, with shape = 1 for the part of the population representing the constant failure rate and shape > 1 for the wearout region. The mean value of the distribution is significantly larger than the median due to the wearout region. As a result, the median time to failure (assuming a constant failure rate during the useful product lifetime) is more informative than the mean time to failure. Due to the nature of statistical sampling, there is also a confidence level typically associated with the median time to failure specification.

FIT Rate

The failure in time (FIT) rate is the reliability metric that is more commonly used, as it is numerically straightforward to apply it to a large SoC product volume with the power-on-hours lifetime specification. The FIT value is an estimate of the number of failing parts in 10**9 hours of operation accumulated across the entire part population. The 10**9 hours is a de facto standard for reference. Mathematically, the FIT value and MTTF are related, as follows.

Assume a constant failure rate, h(t), over the useful life of the population, neglecting the wearout region. The FIT rate is equal to ((10**9) * h(t)). For example, if the estimated SoC failure rate is h(t) = 3.5 * (10** − 8) units/hour, the FIT rate for the part is 35. (Note that a single constant failure rate assumes that the part is consistently operating with a device junction temperature equal to T_max; if the temperature profile over the operating lifetime is known to differ from T_max, a composite calculation using multiple failure rates may be more appropriate.)

For a constant failure rate, the surviving function R(t) is a very slowly decaying exponential. The R(t) and MTTF are illustrated in Figure 15.4.

The motivation for the discussion of both failure rate and MTTF is that the key electromigration mechanism is described in terms of MTTF, whereas SoC specifications commonly use the FIT value. Product developers add the FIT rates of individual components to calculate the overall expected failures.

Note that there are additional reliability metrics used when referring to a (repairable) end product outside the field of microelectronics. The mean time between failures (MTBF) is a probabilistic estimate of the time between successive failures of a product. The mean time to repair (MTTR) is an estimate of the resources required to return a product to functional use. These metrics are evaluated by product developers when estimating service costs and maintenance (downtime) schedules, including (possibly preventive) replacement strategies for field-repairable units (e.g., swapping an existing printed circuit board with a new replacement). The (non-repairable) SoC MTTF or FIT specifications are incorporated into the overall product MTBF calculation.

These SoC reliability projections are inherently statistical approximations, as the corresponding failure mechanisms are probabilistic in nature; this is certainly the case for electromigration. As discussed in the remainder of this chapter, the goal is to establish current density limits for metal interconnects, vias, and contacts such that the total failure rate for the entire SoC due to electromigration does not exceed the reliability target. SoC electrical data from other flows are analyzed to compare actual current densities against these limits.

15.1.3 Sum of Failure Rates

The typical reliability model used for a large electronic system is the sum of failure rates.^[1] This model is based on the following assumptions:

• Each failure rate is independent (at least up until the first failure occurrence).

• The first failure among the independent mechanisms represents the failure of the system.

The failure rate data measured experimentally by the foundry are based on the testsite population, using elevated current density and temperature to accelerate the electromigration mechanisms. Using a key relationship (i.e., Black’s equation), the measured failures can be scaled to calculate the operational MTTF and FIT with corresponding current density limits. Note that the definition of “a failure” in testsite measurement data subsequently needs to be applied to the analysis of the electrical model of the SoC; this is discussed further in the next section.

15.2.1 Black’s Equation and Blech Length

The study of electromigration in integrated circuits began in the 1960s. Subsequent research has expanded the understanding of the metal migration mechanisms, the influence of bidirectional versus unidirectional current, and the influence of circuit-level device self-heating on the thermal profiles of local metals. The original EM investigations resulted in a model known as Black’s equation for the median time to failure due to electron collisions that has continued to be used in the subsequent decades (see Figure 15.6).

In the equation, the factor A is an empirical constant, j is the current density in the wire, and E_A is the activation energy for metal ion displacement. The exponent n depends on the relative contribution of void nucleation (n ~ 2) followed by void growth (n ~ 1). For AlCu wires, the migration kinetics typically result in using n = 2 as the best fit to Black’s equation; for Cu wires, the kinetics favor n = 1. The key characteristics are the strong dependency of measured failures on current density and temperature. As mentioned in the previous section, this equation enables the fitting of accelerated test measurement data, which can then be applied to operating MTTF targets, as shown in Figure 15.7.

The general modeling assumption is that equation coefficients A and n are independent of temperature; the ratio of the activation energy to kT represents the temperature dependence.

Subsequent experimentation demonstrated that there is a substantial reversal of the metal atom displacement flux due to electron collisions when the wire is subject to a (high-frequency) bidirectional current, as would be the case for signal interconnections with moderate-to-high switching activity. A typical model for the MTTF for wires with bidirectional currents is shown in Figure 15.8.

In this revised model, the healing factor increases the reliability current density for bidirectional currents. As a result, signal interconnects between cells are analyzed using different criteria than are used for unidirectional (power rail and cell internal) metals.

Another experimental observation on EM failures noted a wire-length dependence. For test structure wires below a certain length, the failure rate dropped dramatically. As metal atoms are displaced, compressive stress in the metal is present at the anode, and tensile stress exists at the cathode. For short-length wires, these additional material stresses result in a force on metal atoms that counteracts the electron collision flow. The Blech length relationship is used to define metal segments for which significantly higher current density limits are applied. (The definition of an EM fail is discussed shortly.) The Blech length expression is (j * L_Blech<process_limit), specific to each metal layer. The dielectric materials (and damascene barrier metal layers) influence the Blech length, as these interfaces also contribute to the metal stresses.

15.2.2 J_DC, J_AC, J_RMS, and J_PEAK

The electromigration reliability of wires, contacts, and vias is analyzed using four factors:

• Unidirectional DC (average) current density, j_DC or j_AVG

• Bidirectional current density (with healing), j_AC

• The wire temperature increases due to resistive Joule heating, represented for EM analysis by j_RMS

• Peak current density, j_PEAK

Wire Temperature Increase Due to Resistive Joule Heating

The development of a self-consistent model for the wire j_RMS, the local temperature profile, and EM reliability is difficult due to the interdependencies listed earlier, at the beginning of Section 15.2. A typical approach is to:

1. Estimate the j_RMS current in the wire (as discussed in subsequent sections).

2. Utilize a (pre-characterized) model from the foundry for the wire temperature increase due to j_RMS self-heating for the wire metal layer.

3. Add the thermal contribution from local device power dissipation to the wire temperature.

The pre-characterized foundry model for the temperature increase due to j_RMS is specific to each BEOL metallization stack, with the corresponding metal/dielectric layer thicknesses and thermal resistances.

For FinFET and FD-SOI device technologies, the thermal flow to the substrate is reduced over planar devices; an increasing fraction of the active device thermal energy flows into the metallization stack. The foundry provides the models for the (three-dimensional) temperature increase to neighboring wires due to device dissipation. The EDA vendor providing the EM analysis tool links the circuit-level data from the power dissipation analysis flow to these ΔT tables in the PDK to calculate the wire temperature adder due to device self-heating.

The “steady-state” wire temperature is the sum of the j_RMS Joule self-heating ΔT, the ΔT from device self-heating, and the substrate temperature (e.g., T_substrate = T_{junction_max}). If a more accurate die thermal map is available from the power analysis flow, the values from that map could be used instead of a single substrate temperature when calculating the wire temperature.

The calculated wire temperature would be used to further scale the wire failure rate from the foundry PDK data. This method is depicted in Figure 15.10. The calculated wire temperature combining the self-heating, device dissipation, and die substrate temperature factors would be compared to the foundry PDK reference temperature, and a failure rate multiplier would be determined for the wire using Black’s equation for the wire metal layer.

Note that the j_RMS temperature increase calculation applies to metal layers. The Joule heating contribution in vias is small (assuming that the layout includes sufficient vias to satisfy the j_DC limit).

Peak Current Density

The average, bidirectional, and RMS calculations integrate current waveforms over a longer interval. There is also an EM current limit applicable to a short duration current pulse. Each wire segment has a peak current density limit, j_PEAK. The definition of the peak current measurement is illustrated in Figure 15.11.

This current density limit is intended to avoid excessive Joule heating, which could lead to metal deformation. Exceeding the j_PEAKPDK limit values for a wire or via should be regarded as an absolute failure, which requires design changes, rather than as a contribution to the SoC operating lifetime failure rate.

Also, it should be noted that different interconnect layout topologies may have significant current crowding at the transition between a wire and via or in wire jogs. However, EM analysis uses the extracted parasitic electrical network from the layout and thus is not able to accurately reflect non-uniform current densities in the cross-section of a resistive element. Separate EM-avoidance layout design guidelines are typically added to the PDK design ruleset, especially for via arrays between wide metals.

15.2.3 Definition of an EM Failure

The foundry’s process development and PDK design enablement teams fabricate a set of testsites to measure EM failure rates, consistent with Black’s equation (with AC healing) and the Blech length expression. The published j_DC, j_AC, j_RMSΔT, device power ΔT contribution, and j_PEAK data for each layer are referenced to a specific failure rate and temperature. For example, (except for j_PEAK, which is absolute) the current limits for each wire, via, and contact could be defined as follows:

The CAD team collaborates with the EDA tool vendor on the software utilities required to submit the wire current density and temperature results from the electromigration analysis flow to Black’s equation. This calculation with the actual current and temperature scales the published PDK FIT rate for each wire, via, and contact. The full-chip SoC reliability evaluation applies the sum-of-failure rates assumption to the entire population of wires, vias, and contacts to provide an overall FIT estimate.

However, it is also crucial for the SoC methodology team to review the testsite measurement criteria that denote failure. Metal atom flux results in the formation of voids, originating from the nucleation of metal lattice vacancies. The focus of accelerated testing at the foundry is the resistance increase in the wire or via due to the growth of voids. A “failure” is recorded when the starting resistance of a testsite structure increases by N%—typically N = 10%, or ΔR = (R_stress / R) = 1.1. A scattergram of ΔR versus current density is plotted for the resistance data measured after stress testing for each structure on the testsite wafers. This plot is analyzed to select the current density limit for each metal, via, and contact layer, corresponding to the reference FIT for that layer published in the PDK.

Although a wire segment resistance increase is reported as an EM failure, the SoC design may be sufficiently robust to maintain functionality. For example, the grid topology of the power/ground distribution may still be able to maintain an adequate voltage drop in the presence of (multiple) EM failures. The contribution of a “failing” power grid segment to the FIT calculation may be overstated. The EM analysis flow targeting the power grids integrates the voltage drop analysis algorithm described in Chapter 14, “Power Rail Voltage Drop Analysis,” with a modified conductance matrix due to high-resistance segment(s)—perhaps even removing the conductance of the failing EM segment altogether. If the power grid is still adequate, the FIT value merits correction.

The methodology for EM analysis for a signal wire in the presence of current density failures is more complex. The robustness of a static timing or noise path may remain in the presence of wire segment resistance increases of N%. Conversely, a critical path may fail static timing analysis if the resistive element(s) in the interconnect model are increased by N%.

The SoC methodology team is faced with multiple options in response to the results from the sigEM flow:

• First, any j_PEAK limit failures must be resolved.

• Design ECOs may be required to address any “high FIT” wires/vias. If a signal wire has a high FIT due to its current density, this may be indicative of a physical layout mismatch between cell drive strength, wire widths, and capacitive load. Min/max signal slew limit checks applied to the static timing analysis results would have previously identified appropriate design changes and hopefully reduce the mismatch resulting in the high current density. Reference 15.2 compares the current density from a “matched” driver and interconnect to typical process technology j_AC EM limits. If a signal via has a high FIT contribution, multiple vias (on wider wires) are warranted. If the ΔT temperature adder is a significant factor in the FIT value, more significant layout changes are required to increase the distance from power dissipation sources.

• Additional performance margin for EM resistance increases over the SoC lifetime may be appropriate, in addition to BTI and HCI device parameter drift mechanisms. This is an unattractive option, to be sure.

• The static timing analysis slack results for the paths corresponding to signal wires with high FIT are evaluated and an assessment is made to determine whether a potential increase in interconnect delay has sufficient positive slack to warrant reducing the FIT value.

Reference 15.3 presents an algorithm to correlate the wire EM failure probability density function, f(t), to a probability distribution for the increase in wire resistance. Then Monte Carlo-sampled circuit simulations are used to evaluate probabilistic path delay increases over time (e.g., 5 to 20 years). The SoC and CAD teams may opt to deploy a similar flow to assess the sensitivity of timing paths with high-FIT wires to the resistance increase as a function of operating lifetime.

15.2.4 Extraction Model for Electromigration

To apply the sum-of-failure-rate algorithm for the SoC reliability calculation, it is necessary to evaluate the current densities in a detailed parasitic extraction network without reduction. In addition, the parasitic extraction flow needs to be exercised in verbose mode, where resistive elements include full layout detail to enable current density calculation (see Figure 15.12). The resistor example in the figure includes a thickness parameter. The foundry may provide an analytical model for the chemical-mechanical polishing metal planarization process module. The layout extraction tool from the EDA vendor may include a corresponding CMP analysis algorithm to derive a (non-default) wire thickness estimate. (CMP analysis is also applied to yield prediction models, as any non-planarity of the wafer surface affects lithographic exposure accuracy due to depth-of-focus limits.)

Electromigration models and the related failure rate calculations are complex probabilistic relationships that utilize an empirical fit of testsite data to the model of Black’s equation. As mentioned earlier in this section, the kinetics for atom displacement are unique for unidirectional and bidirectional currents. As a result, EM analysis is divided into power and ground rail (powerEM) and switching interconnect (sigEM) flows, discussed next.

15.4.1 Cell-Level EM Analysis

The development of a cell IP library for release to SoC designers requires analysis of the FIT rates associated with the wires, vias, and contacts within the cell layout. The cell contains a mix of unidirectional and bidirectional wire currents, necessitating calculation of both j_AVG and j_AC current densities during the cell characterization circuit simulations.

The library developer needs to ensure a very low FIT rate for each cell, across a wide range of characterization and usage conditions. The calculation of j_PEAK, j_AVG, j_RMS, and j_AC for each metal segment in the extracted model requires a conservative (high) estimate for the assumed circuit-switching activity. The current density calculations need to use the maximum values measured during characterization for any of the pin-to-pin delay arcs and the range of input pin slews and output loads.

There are several electromigration concerns specific to cell-based analysis, as illustrated in Figure 15.15:

• The proximity to device self-heating results in a significant ΔT contribution, in addition to the j_RMS wire self-heating.

• The availability of local-interconnect metal layers in a process technology results in both horizontal and vertical current density in the metal, with different PDK EM limits for the M0 layout for the two current directions.

• The introduction of area pins enables the router to select among multiple wiring tracks; the specific pin location selected modifies the unidirectional and bidirectional current profiles; a worst-case pin selection EM analysis is required.

These same EM analysis considerations apply to the reliability estimates for larger IP macros, as well. The SoC methodology team needs to review the algorithms used by the IP vendor when evaluating the library IP FIT rate specification.

15.4.2 EM Analysis for Clocks

The design of clock repowering grids and H-trees requires focus on optimal sizing of clock buffers and interconnects. Early EM analysis of clock j_AC and j_RMS is encouraged, as soon as the (global) clock distribution is available, to confirm the buffer and wire design assumptions.

Like the device-level BTI and HCI parameter drift mechanisms, the evolution of resistance increase in clock wires contributes to arrival skew variation at clock distribution endpoints. The previous section references an algorithm to correlate interconnect electromigration (void growth) data with a probability distribution model for resistance increase; this model would be applicable in clock simulations to develop a consolidated BTI/HCI/EM lifetime skew margin to adopt in static timing analysis.

15.4.3 SigEM Current Density Calculation

The sigEM analysis flow for IP library cells measures the current densities of interest using the circuit simulation data from cell characterization. For (block and global) signals between cells, a different method for current density calculations for sigEM is required.

The static timing analysis flow provides a model for the driving current source on each cell output for both RDLY and FDLY transitions (for each STA mode/corner). Although there are different current source profiles for different input pin-to-output pin arcs, STA propagates a single arc for path delay analysis. Assuming that this arc represents the greatest sensitivity to an increase in the interconnect resistance, using the STA-propagated driver current profile for sigEM analysis is appropriate.

The circuit simulation of each interconnect tree to determine j_AC, j_RMS, and j_PEAK would be computationally expensive. Reference 15.4 describes an alternative approach, which involves solving a matrix-based formulation to calculate these currents. The translation of the interconnect model into a linear matrix is based on evaluating the total charge delivered to the network from the driving current at the cell output, as depicted in Figure 15.16.

The matrix equations for the signal interconnect RC trees are similar to those developed for the dynamic power voltage drop flow using Kirchhoff’s current law, as described in Section 14.3:

In Equation 15.3, G is the interconnect conductance matrix of dimensionality (N x N), where there are N nodes in the interconnect tree (including a ground reference node), and g_ij is the conductance between nodes i and j. For the case of an extracted signal interconnect, this conductance matrix is very sparse (and there is no conductance between any extracted node and ground). C is the network capacitance matrix, and v is the vector of interconnect node voltages. The vector s describes the current sources into the network. For sigEM analysis, it is assumed that the only current source is from the driver node; no other side currents are injected into the interconnect network during the cell output transient (thus neglecting aggressor noise-coupled transients).

Integration of both sides of Equation 15.3 from t = 0 to t = T provides the following equivalent relationship:

The integral of the vector v' results in two simple vectors for the node voltages at t = 0 and t = T. For the case of a signal interconnect, assume that the initial and final values of all (capacitive storage) node voltages are known (e.g., v₀ = [ 0 ] and v_T = [ VDD ] for a RDLY transition). The integral of the current source vector s provides a vector representing the total charge delivered by the driving current source, Q_D. This vector is nonzero only at the cell output node. The total driver charge can be easily calculated: It is equal to the charge delivered to all the network capacitances during the transition, (C_total * VDD). The vector w is the voltage integral at each node as a result of the driver transient, and it is the vector to be solved in the matrix equation.

Solving for the vector w also provides the total charge through each interconnect resistor as a result of the driver transient: q_ij = g_ij * |w_j−w_i |, where g_ij is the conductance (1/R) between nodes i and j. The j_AC for each resistive element in the signal interconnect can thus be determined from the total charge calculation, as shown in Figure 15.17.

The calculation of j_RMS and j_PEAK for a signal interconnect element requires waveform detail. To avoid the computational demand of circuit simulation, Reference 15.4 also proposes an approximation for these waveforms, leveraging the earlier matrix solution for the total charge through each resistive element during a transition. Referring to Figure 15.18, assume that the current waveform through each resistive element is (roughly) triangular. The total charge delivered for the transition, combined with a (minimum) transition time for the signal from static timing analysis results, defines the approximate current waveform and the subsequent j_RMS and j_PEAK values for the sigEM FIT calculation.

With the estimated values for j_AC, j_RMS, j_PEAK, device self-heating ΔT, and duty cycle for each resistive element, the foundry PDK limits and FIT scaling factors can be calculated.

The sigEM FIT results at block, core, and full-chip hierarchy levels require review by the SoC methodology team to determine whether significant FIT contributions by resistive elements require physical design updates or further simulation analysis to assess the sensitivity of the (probabilistic) resistance increase to overall functionality.

Flowcharts for EM Analysis with Data from Other Flows

This chapter highlights algorithms used for powerEM and sigEM analysis of the FIT rate and the data required from other flows to enable this analysis; however, the chapter discussion lacks visual descriptions. Develop comprehensive flowcharts for EM reliability analysis, including:

• powerEM

  • The (non-reduced) model from parasitic extraction

  • The required data from the power rail voltage drop analysis flow

  • j_AVG, j_RMS, and j_PEAK calculations

  • Scaling of the foundry FIT data for the calculated current density of each power and ground resistive segment

  • Power rail voltage drop analysis with modified g_ij elements for high-FIT segments

• sigEM

  • The model from parasitic extraction

  • The required data from the STA flow for the output driver current for each signal net

  • The switching activity data from (stressmark) simulation testcases

  • The j_AC, j_RMS, and j_PEAK calculations (with healing factor)

  • Scaling of the foundry FIT data for the calculated current density of each RC interconnect segment

  • Additional path timing analysis options for high-FIT interconnect segments

Electromigration and Wire/Via/Contact Metallurgy (Advanced)

Process development engineers are continually evaluating new metallurgies for wires and contacts/vias. These engineering teams assess the resistivity and electromigration parameters versus the difficulty in material deposition and patterning.

Research and describe the (temperature-dependent) resistivity and electromigration activation (Black’s equation) for metals used in SoC fabrication (e.g., Al, Cu, Co, W, Ti).

Describe the process development techniques used to increase grain size and/or orient grain boundaries to minimize atom displacement.

Electromigration “Resistive” Fails

The discussion in this chapter proposes addressing EM failures with additional analysis using increased resistance values in the conductance model of the power grid or the RC interconnect model for a timing path delay. The intent is to justify the specification of a lower overall FIT rate for SoC reliability. However, the nucleation and growth rate of voids in a metal wire leading to a resistance increase is a non-linear function, increasing over time.

Research and describe the rate of resistance increase in a metal wire subject to high current densities and void growth for various metallurgies. Describe the rate of change in the resistivity after an increase of N~10%.

Describe the risks associated with the justification of reducing the contribution from high-FIT segments, based on subsequent power rail voltage drop and path timing analysis with modified (R + 10%) elements.

Blech Length (Advanced)

For efficiency, the SoC methodology team may opt to skip the current density and FIT rate calculation altogether for wire segments less than the Blech length.

Research and describe the Blech length and MTTF correction factor for metals (and surrounding dielectric materials) in advanced process nodes. Determine a strategy for optimizing EM flow runtime for segments less than the Blech length.