6
POWER-FACTOR-CORRECTION (PFC) CIRCUITS AND DESIGNING THE FEEDBACK CONTROLLER

In diode rectifiers discussed in Chapter 5, power is drawn by means of highly distorted currents, which have a deleterious effect on the power quality of the utility source. In single-phase diode-rectifier systems, a corrective action such as that described in this chapter is often taken. This discussion is also useful in the learning process since it shows a real-world application of DC-DC converters discussed in Chapter 3 and their control in Chapter 4.

6.1 INTRODUCTION

Technical solutions to the problem of distortion in the input current have been known for a long time. However, only recently has the concern about the deleterious effects of harmonics led to the formulation of guidelines and standards, which in turn have focused attention on ways of limiting current distortion.

In the following sections, power-factor-corrected (PFC) interface, as they are often called, are briefly examined for single-phase rectification, where it is assumed that the power needs to flow only in one direction, such as in DC power supplies. The three-phase front-ends in motor-drives applications may require bi-directional power flow capability. Such front-ends, which also allow unity power factor of operation, are discussed in Chapter 12.

6.2 OPERATING PRINCIPLE OF SINGLE-PHASE PFCS

The operating principle of a commonly used single-phase PFC is shown in Figure 6.1a, where, between the utility supply and the DC-bus capacitor, a boost DC-DC converter is introduced. This boost converter consists of a MOSFET, a diode, and a small inductor upper L Subscript d. By pulse-width-modulating the MOSFET at a constant switching frequency, the current i Subscript upper L through the inductor upper L Subscript d is shaped to have the full-wave-rectified waveform ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With caret Subscript upper L Baseline StartAbsoluteValue sine omega t EndAbsoluteValue, similar to StartAbsoluteValue v Subscript s Baseline left-parenthesis t right-parenthesis zero width space EndAbsoluteValue, as shown in Figure 6.1b.

FIGURE 6.1 PFC circuit and waveforms.

The inductor current contains a high switching-frequency ripple, which is removed by a small filter.

The input current i Subscript s in the circuit of Figure 6.1a becomes sinusoidal and in phase with the supply voltage. In the boost converter, it is essential that the DC-bus voltage upper V Subscript d be greater than the peak of the supply voltage ModifyingAbove upper V With caret Subscript s:

upper V Subscript d Baseline greater-than ModifyingAbove upper V With caret Subscript s Baseline period (6.1)

Figure 6.2a shows the average model of the boost converter in the continuous-conduction mode (CCM) with i Subscript upper L Baseline greater-than 0 at all times. Neglecting a small voltage drop across the inductor and assuming the voltage across the capacitor to be a pure DC, in a boost converter, the voltage transfer ratio is

FIGURE 6.2 Average model in CCM (Average model in CCM (

StartFraction upper V Subscript d Baseline Over StartAbsoluteValue v Subscript s Baseline EndAbsoluteValue EndFraction equals StartFraction 1 Over 1 minus d left-parenthesis t right-parenthesis EndFraction comma(6.2)

and thus,

1 minus d left-parenthesis t right-parenthesis equals StartFraction ModifyingAbove upper V With caret Subscript s Baseline StartAbsoluteValue sine omega t EndAbsoluteValue Over upper V Subscript d Baseline EndFraction(6.3a)

and

d left-parenthesis t right-parenthesis equals 1 minus StartFraction ModifyingAbove upper V With caret Subscript s Baseline StartAbsoluteValue sine omega t EndAbsoluteValue Over upper V Subscript d Baseline EndFraction period(6.3b)

Equation (6.3) shows that 1 minus d left-parenthesis t right-parenthesis of the switch varies sinusoidally during each half-cycle of the fundamental frequency, independent of the value of the inductor current, provided it is greater than zero. The switch duty ratio from Equation (6.3b) is plotted in Figure 6.2b.

The inductor current is shaped to be ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With caret Subscript upper L Baseline StartAbsoluteValue sine omega t EndAbsoluteValue. Therefore, the current ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis can be calculated from the turns ratio of the ideal transformer in Figure 6.2a as

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals left-parenthesis 1 minus d right-parenthesis ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis equals left-parenthesis 1 minus d right-parenthesis ModifyingAbove upper I With caret Subscript upper L Baseline StartAbsoluteValue sine omega t EndAbsoluteValue period(6.4a)

Substituting for left-parenthesis 1 minus d right-parenthesis from Equation (6.3) in Equation (6.4),

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals StartFraction ModifyingAbove upper V With caret Subscript s Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript upper L Baseline StartAbsoluteValue sine omega t EndAbsoluteValue squared period(6.4b)

Recognizing that in Equation (6.4), StartAbsoluteValue sine omega t EndAbsoluteValue squared equals sine squared omega t equals one-half minus one-half cosine 2 omega t:

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals ModifyingBelow one-half StartFraction ModifyingAbove upper V With caret Subscript s Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript upper L Baseline With presentation form for vertical right-brace Underscript upper I Subscript d Baseline Endscripts minus ModifyingBelow one-half StartFraction ModifyingAbove upper V With caret Overscript zero width space Endscripts Subscript s Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript upper L Baseline cosine 2 omega t With presentation form for vertical right-brace Underscript i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis Endscripts period(6.5)

Equation (6.5) shows that the average current to the output stage consists of a DC component upper I Subscript d and a component i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis at the second-harmonic frequency.

Example 6.1

Derive ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis in Equation (6.5) by equating input and output powers.

Solution Assume that v Subscript s Baseline equals ModifyingAbove upper V With caret Subscript zero width space s Baseline sine omega t and i Subscript s Baseline equals ModifyingAbove upper I With caret Subscript s Baseline sine omega t. Therefore, the input power upper P Subscript i n Baseline left-parenthesis t right-parenthesis equals v Subscript s Baseline i Subscript s Baseline equals ModifyingAbove upper V With caret Subscript zero width space s Baseline ModifyingAbove upper I With caret Subscript s Baseline sine squared omega t. Recognizing that sine squared omega t equals one-half minus one-half cosine 2 omega t, the input power is upper P Subscript i n Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper V With caret Subscript zero width space s Baseline ModifyingAbove upper I With caret Subscript s Baseline sine squared omega t equals one-half zero width space ModifyingAbove upper V With caret Subscript s Baseline ModifyingAbove upper I With caret Subscript s Baseline minus one-half zero width space ModifyingAbove upper V With caret Subscript zero width space s Baseline ModifyingAbove upper I With caret Subscript s Baseline cosine 2 omega t. The output power p Subscript o Baseline left-parenthesis t right-parenthesis equals upper V Subscript d Baseline i overbar Subscript d. Equating p Subscript i n Baseline left-parenthesis t right-parenthesis equals p Subscript o Baseline left-parenthesis t right-parenthesis, and recognizing that ModifyingAbove upper I With caret Subscript s Baseline equals ModifyingAbove upper I With caret Subscript upper L

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals ModifyingBelow one-half StartFraction ModifyingAbove upper V With caret Subscript s Baseline ModifyingAbove upper I With caret Subscript upper L Baseline Over upper V Subscript d Baseline EndFraction With presentation form for vertical right-brace Underscript upper I Subscript d Baseline Endscripts minus ModifyingBelow one-half StartFraction ModifyingAbove upper V With caret Subscript s Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript upper L Baseline cosine 2 omega t With presentation form for vertical right-brace Underscript i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis Endscripts comma(6.6)

which is the same as Equation (6.5).

The output stage of the PFC is shown in Figure 6.3, where the DC component upper I Subscript d of i overbar Subscript d flows through the load-equivalent resistor. In PFCs, the capacitor in the output stage is quite large, such that it is justifiable to approximate that the second-harmonic frequency component i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis flows entirely through the output capacitor and none through the load-equivalent resistor. The peak value of i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis is

ModifyingAbove upper I With caret Subscript d Baseline 2 Baseline equals zero width space one-half StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript upper L Baseline period(6.7)

FIGURE 6.3 Current division in the output stage.

Based on the assumption that i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis flows entirely through the output capacitor, the peak value of the second-harmonic frequency ripple in the output voltage can be calculated as follows, where the reactance of the capacitor at twice the line frequency is 1 zero width space slash zero width space left-parenthesis 2 omega upper C right-parenthesis:

ModifyingAbove upper V With caret Subscript d Baseline 2 Baseline left-parenthesis StartFraction 1 Over 2 omega upper C EndFraction right-parenthesis ModifyingAbove upper I With caret Subscript d Baseline 2 Baseline equals StartFraction ModifyingAbove upper I With caret Subscript upper L Baseline Over 4 omega upper C EndFraction StartFraction ModifyingAbove upper V With caret Subscript s Baseline Over upper V Subscript d Baseline EndFraction period(6.8)

ModifyingAbove upper V With ⌢ Subscript zero width space d Baseline 2 depends inversely on the output capacitance upper C, and therefore, an appropriate value of upper C must be chosen to minimize this ripple.

Example 6.2

Calculate ModifyingAbove upper V With caret Subscript zero width space d Baseline 2 at full-load and the nominal input voltage for the parameters and operating values of a PFC given in Table 6.1 later on. Ignore the capacitor ESR.

Solution Assuming the PFC to be lossless, upper V Subscript s Baseline upper I Subscript s Baseline equals upper P Subscript o. Therefore, using the values given in Table 6.1, ModifyingAbove upper I With caret Subscript upper L Baseline equals ModifyingAbove upper I With caret Subscript s Baseline equals StartRoot 2 EndRoot StartFraction upper P Subscript o Baseline Over upper V Subscript s Baseline EndFraction equals 2.946 normal upper A. ModifyingAbove upper V With caret Subscript zero width space s Baseline equals StartRoot 2 EndRoot times 120 equals 169.7 upper V. Therefore, from Equation (6.8), the peak value of the second-harmonic frequency voltage is

ModifyingAbove upper V With caret Subscript zero width space d Baseline 2 Baseline equals StartFraction ModifyingAbove upper I With caret Subscript upper L Baseline Over 4 omega upper C EndFraction StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript d Baseline EndFraction 6 normal upper V zero width space period

TABLE 6.1  Parameters and operating values.

Nominal input AC source voltage, upper V Subscript s comma r m s120 V
Line frequency, f60 Hz
Output voltage, upper V Subscript d250 V(DC)
Maximum power output250 W
Switching frequency, f Subscript s100 kHz
Output filter capacitor, upper C220 normal mu normal upper F
ESR of the capacitor, r100 normal m normal upper Omega
Inductor, upper L Subscript d1 mH
Full-load equivalent resistance, upper R250 normal upper Omega

6.3 CONTROL OF PFCS

Figure 6.4 shows the PFC power circuit along with its control circuit in a block-diagram form. In controlling a PFC, the main objective is to draw a sinusoidal current in-phase with the utility voltage. The reference inductor current i Subscript upper L Superscript asterisk Baseline left-parenthesis t right-parenthesis is of the full-wave rectified form, similar to that in Figure 6.1b. The requirements on the form and the amplitude of the inductor current lead to two control loops, as shown in Figure 6.4, to pulse-width modulate the switch of the boost converter.

  • The average inner current control loop ensures the form of i Subscript upper L Superscript asterisk Baseline left-parenthesis t right-parenthesis based on the template sine StartAbsoluteValue omega t EndAbsoluteValue provided by measuring the rectifier output voltage StartAbsoluteValue v Subscript s Baseline left-parenthesis t right-parenthesis EndAbsoluteValue.
  • The outer voltage control loop determines the amplitude ModifyingAbove upper I With caret Subscript upper L of i Subscript upper L Superscript asterisk Baseline left-parenthesis t right-parenthesis based on the output voltage feedback. If the inductor current is insufficient for a given load supplied by the PFC, the output voltage will drop below its preselected reference value upper V Subscript d Superscript asterisk. By measuring the output voltage and using it as the feedback signal, the voltage control loop adjusts the inductor current amplitude to bring the output voltage to its reference value. In addition to determining the inductor current amplitude, this voltage feedback control acts to regulate the output voltage of the PFC to the preselected DC voltage.

FIGURE 6.4 PFC control loops.

In Figure 6.4, the inner current-control loop is required to have a very high bandwidth compared to the outer voltage-control loop. Hence, each loop can be designed separately, similar to the approach taken in the peak-current-mode control discussed in Chapter 4.

6.4 DESIGNING THE INNER AVERAGE-CURRENT-CONTROL LOOP

The inner current control loop is shown within the inner dotted box in Figure 6.4. In order to follow the reference with as little THD as possible, an average-current-mode control is used with a high bandwidth, where the error between the reference i Subscript upper L Superscript asterisk Baseline left-parenthesis t right-parenthesis and the measured inductor current i Subscript upper L Baseline left-parenthesis t right-parenthesis is amplified by a current controller to produce the control voltage v Subscript c Baseline left-parenthesis t right-parenthesis. This control voltage is compared with a ramp signal v Subscript r Baseline left-parenthesis t right-parenthesis, with a peak of ModifyingAbove upper V With caret Subscript r at the switching frequency f Subscript s in the PWM controller IC [1], to produce the switching signal q left-parenthesis t right-parenthesis.

Just the inner current control loop of Figure 6.4 can be simplified, as shown in Figure 6.5a. The reference input i Subscript upper L Superscript asterisk Baseline left-parenthesis t right-parenthesis varies with time, as shown in Figure 6.2b, where the corresponding StartAbsoluteValue v Subscript s Baseline left-parenthesis t right-parenthesis zero width space EndAbsoluteValue and d left-parenthesis t right-parenthesis waveforms are also plotted. However, these quantities vary much more slowly compared to the current control-loop bandwidth, approximately 10 kHz in the numerical example considered later on. Therefore, at each instant of time, for example at t 1 in Figure 6.2b, the circuit of Figure 6.2a can be considered in a “DC” steady-state with the associated variables having values of i Subscript upper L Baseline left-parenthesis t 1 right-parenthesis, StartAbsoluteValue v Subscript s Baseline left-parenthesis t 1 right-parenthesis zero width space EndAbsoluteValue and d left-parenthesis t 1 right-parenthesis. This equilibrium condition varies slowly with time compared to the current-control-loop bandwidth, which is designed to be much larger. In the Laplace domain, this current loop is shown in Figure 6.5b, as discussed below, where the tilde “~” on top represents small signal perturbations at very high frequencies in the range of the current-control-loop bandwidth, for example, 10 kHz.

FIGURE 6.5 PFC current loop.

6.4.1 d˜(s)/v˜c(s) for the PWM Controller

If ModifyingAbove upper V With caret Subscript r is the difference between the peak and the valley of the ramp voltage in the PWM-IC, then the small-signal transfer function of the PWM controller, as discussed in Chapter 4, is

StartLayout 1st Row 1st Column PWM Controller Transfer Function 2nd Column zero width space StartFraction ModifyingAbove d With tilde left-parenthesis s right-parenthesis Over ModifyingAbove v With tilde Subscript c Baseline left-parenthesis s right-parenthesis EndFraction EndLayout zero width space equals zero width space StartFraction 1 Over ModifyingAbove upper V With caret Subscript r Baseline EndFraction period(6.9)

6.4.2 i˜L(s)/d˜(s) for the Boost Converter in the Power Stage

In spite of the varying DC steady-state operating point, the transfer function in the boost converter simplifies as follows at high frequencies at which the current-control-loop bandwidth is designed:

StartFraction ModifyingAbove i With tilde Subscript upper L Baseline left-parenthesis s right-parenthesis Over ModifyingAbove d With tilde left-parenthesis s right-parenthesis EndFraction StartFraction upper V Subscript d Baseline Over s upper L Subscript d Baseline EndFraction period(6.10)

This can be observed from the small-signal circuit for the boost converters in Figure 4.7b of Chapter 4, where at high frequencies, the capacitor acts as a short circuit, resulting in the above transfer function (ignoring capacitor ESR, and noting that upper V Subscript o in Chapter 4 is upper V Subscript d in this chapter). This conclusion can be confirmed by LTspice simulations that show that in the boost converter of a PFC, all the curves corresponding to various input voltages and the associated duty ratios merge at high frequencies to yield results similar to that of the transfer function in Equation (6.10).

6.4.3 Designing the Current Controller Gi(s)

The transfer function in Equation (6.10) is an approximation valid at high frequencies and not a pure integrator. Therefore, to have a high loop DC gain and a zero DC steady-state error in Figure 6.5b, the current controller transfer function upper G Subscript i Baseline left-parenthesis s right-parenthesis must have a pole at the origin. In the loop in Figure 6.5b, the phase due to the pole at origin in upper G Subscript i Baseline left-parenthesis s right-parenthesis and that of the power-stage transfer function (Equation 6.10) add up tominus 180 Superscript ring. Hence, upper G Subscript i Baseline left-parenthesis s right-parenthesis, as in the peak-current mode control discussed in Chapter 4, includes a pole-zero pair that provides a phase boost, and hence the specified phase margin, for example 60 Superscript ring at the loop crossover frequency:

upper G Subscript i Baseline left-parenthesis s right-parenthesis equals StartFraction k Subscript c Baseline Over s EndFraction StartFraction 1 plus s slash omega Subscript z Baseline Over 1 plus s slash omega Subscript p Baseline EndFraction comma(6.11)

where k Subscript cis the controller gain. Knowing the phase boost, phi Subscript b o o s t, we can calculate the pole-zero locations to provide the necessary phase boost, as discussed in Chapter 4:

upper K Subscript b o o s t Baseline equals tangent left-parenthesis 45 Superscript degree Baseline plus StartFraction phi Subscript b o o s t Baseline Over 2 EndFraction right-parenthesis(6.12)
f Subscript z Baseline equals StartFraction f Subscript c i Baseline Over upper K Subscript b o o s t Baseline EndFraction(6.13)
f Subscript p Baseline equals upper K Subscript b o o s t Baseline f Subscript c i Baseline comma(6.14)

where f Subscript c i is the crossover frequency of the current loop transfer function.

6.5 DESIGNING THE OUTER VOLTAGE-CONTROL LOOP

As mentioned earlier, the outer voltage-control loop is needed to determine the peak, ModifyingAbove upper I With caret Subscript upper L, of the inductor current. In this voltage loop, the bandwidth is limited to approximately 15 Hz. The reason has to do with the fact that the output voltage across the capacitor contains a component v Subscript d Baseline 2 as derived in Equation (6.8) at twice the line-frequency (at 120 Hz in 60-Hz line-frequency systems). This output voltage ripple must not be corrected by the voltage loop; otherwise, it will lead to a third-harmonic distortion in the input current, as explained in Appendix 6A at the end of this chapter.

In view of such a low bandwidth of the voltage-control loop (approximately three orders of magnitude below the current-loop bandwidth of ~10 kHz), it is perfectly reasonable to assume the current loop to be ideal at low frequencies around 15 Hz. Therefore, in the voltage-control block diagram shown in Figure 6.6a, the current closed-loop produces ModifyingAbove upper I With caret Subscript upper L equal to its reference valueModifyingAbove upper I With caret Subscript upper L Superscript asterisk. In addition to a large DC component, ModifyingAbove upper I With caret Subscript upper L Superscript asterisk contains an unwanted second-harmonic frequency component ModifyingAbove upper I With caret Subscript upper L Baseline 2 due to v Subscript d Baseline 2 in the input to the voltage controller. ModifyingAbove upper I With caret Subscript upper L Baseline 2 at the second-harmonic frequency results in a third-harmonic frequency distortion in the current drawn from the utility, as explained in Appendix 6A. Therefore, in the output of the voltage controller block in Figure 6.6a, ModifyingAbove upper I With caret Subscript upper L Baseline 2 is limited to approximately 1.5% of the DC component in ModifyingAbove upper I With caret Subscript upper L Superscript asterisk.

FIGURE 6.6 Voltage control loop.

The voltage control loop for low-frequency perturbations, in the range of the voltage-loop bandwidth of approximately 15 Hz, is shown in Figure 6.6b. As derived in Appendix 6B, the transfer function of the power stage in Figure 6.6b at these low perturbation frequencies (ignoring the capacitor ESR) is:

StartFraction ModifyingAbove v With tilde Subscript d Baseline left-parenthesis s right-parenthesis Over ModifyingAbove i With tilde Subscript upper L Baseline left-parenthesis s right-parenthesis EndFraction equals one-half StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript d Baseline EndFraction StartFraction upper R slash 2 Over 1 plus s left-parenthesis upper R slash 2 right-parenthesis upper C EndFraction period(6.15)

To achieve a zero steady-state error, the voltage-controller transfer function should have a pole at the origin. However, since the PFC circuit is often a pre-regulator (not a strict regulator), this requirement is waived, which otherwise would make the voltage controller design much more complicated. The following simple transfer function is often used for the voltage controller in Figure 6.6b, where a pole is placed at the voltage-loop crossover frequency omega Subscript c v (yet to be determined) below 15 Hz,

upper G Subscript v Baseline left-parenthesis s right-parenthesis equals StartFraction k Subscript v Baseline Over 1 plus s slash omega Subscript c v Baseline EndFraction period(6.16)

At full load, the power stage transfer function given by Equation (6.15) has a pole at a very low frequency, for example, of the order of one or two Hz, which introduces a phase lag approaching 90° much beyond the frequency at which this pole occurs. The transfer function of the controller given by Equation (6.16) introduces a lag of 45° at the loop crossover frequency. Therefore, the sum of these two phase lags adds to tilde 135 degree at the crossover frequency and results in a satisfactory phase margin of 45 degree. Using Equations (6.15) and (6.16), by definition, at the crossover frequency f Subscript c v, the loop transfer function in Figure 6.6b has a magnitude equal to unity:

StartAbsoluteValue StartFraction k Subscript v Baseline Over 1 plus s slash omega Subscript c v Baseline EndFraction one-half StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript d Baseline EndFraction StartFraction upper R slash 2 Over 1 plus s left-parenthesis upper R slash 2 right-parenthesis upper C EndFraction EndAbsoluteValue Subscript s equals j left-parenthesis 2 pi times f Sub Subscript c v Subscript right-parenthesis Baseline equals 1 period(6.17)

In the voltage controller of Figure 6.6b and Equation (6.16), the input ModifyingAbove upper V With caret Subscript d Baseline 2 results in an output ModifyingAbove upper I With caret Subscript upper L Baseline 2. Therefore, at the second-harmonic frequency in the voltage controller of Equation (6.16),

StartAbsoluteValue StartFraction k Subscript v Baseline Over 1 plus s slash omega Subscript c v Baseline EndFraction EndAbsoluteValue Subscript s equals j left-parenthesis 2 pi times 120 right-parenthesis Baseline equals StartFraction ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline Over ModifyingAbove upper V With caret Subscript d Baseline 2 Baseline EndFraction period(6.18)

From Equations (6.17) and (6.18), the two unknowns k Subscript v and omega Subscript c v in the voltage controller transfer function of Equation (6.16) can be calculated, as described by a numerical example.

6.6 EXAMPLE OF SINGLE-PHASE PFC SYSTEMS

The operation and control of a PFC are demonstrated by means of an example, where the parameters are as shown in Table 6.1, and the total harmonic distortion in the input line current is required to be less than 3% [1, 2]:

6.6.1 Design of the Current-Control Loop

In Equation (6.9), assume that ModifyingAbove upper V With caret Subscript r Baseline equals 1. Following the procedure described in Chapter 4 for the peak-current-mode control of DC-DC converters, for the loop crossover frequency of 10 kHz(omega Subscript c i Baseline equals 2 pi times 10 Superscript 4 Baseline rad slash normal s) and the phase margin of 60 degree, the parameters in the current controller of Equation (6.11) are as follows:

StartLayout 1st Row k Subscript c Baseline equals 4212 2nd Row omega Subscript z Baseline equals 1.68 times 10 Superscript 4 Baseline rad slash normal s 3rd Row omega Subscript p Baseline equals 2.35 times 10 Superscript 5 Baseline rad slash normal s EndLayout period(6.19)

Based on these parameter values given in Equation (6.19) of the transfer function upper G Subscript i Baseline left-parenthesis s right-parenthesis in Equation (6.11), the op-amp circuit is similar to that in Figure 4.19 in Chapter 4 with the following values for a chosen value of upper R 1 equals 100 normal k normal upper Omega:

StartLayout 1st Row upper C 2 0.17 nF 2nd Row upper C 1 2.2 nF 3rd Row upper R 2 27 normal k normal upper Omega EndLayout period(6.20)

6.6.2 Design of the Voltage-Control Loop

In this example, at full load, the plant transfer function given by Equation (6.15) has a pole at the frequency of 36.36 rad/s (5.79 Hz). At full load, ModifyingAbove upper I With caret Subscript upper L Baseline equals 2.946 upper A, and in Equation (6.8), ModifyingAbove upper V With caret Subscript d Baseline 2 Baseline equals 6.029 normal upper V. Based on the previous discussion, the second-harmonic component is limited to 1.5% of ModifyingAbove upper I With caret Subscript upper L, such that ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline equals 0.0442 normal upper A. Using these values, from Equations (6.17) and (6.18), the parameters in the voltage controller transfer function of Equation (6.16) are calculated: k Subscript v Baseline equals 0.0754, and omega Subscript c v Baseline equals 73.7 rad slash normal s (11.73 Hz). This transfer function is realized by an op-amp circuit shown in Figure 6.7, where

StartLayout 1st Row upper R 1 equals 100 k upper Omega 2nd Row upper R 2 equals 7.54 k upper Omega 3rd Row upper C 1 equals 1.8 mu upper F EndLayout period(6.21)

FIGURE 6.7 Op-amp circuit to implement transfer function Gv(s).

6.7 SIMULATION RESULTS

The LTspice-based simulation of the PFC system is shown in Figure 6.8, where the input voltage and the full-bridge rectifier are combined for simplification purposes. The output load is decreased as a step at 100 ms. The resulting waveforms for the voltage and the inductor current are shown in Figure 6.9.

FIGURE 6.8 LTspice simulation diagram (the load is decreased at 100 ms); for a better resolution, execute the LTspice Schematic on the accompanying website.

FIGURE 6.9 Simulation results: output voltage and inductor current.

6.8 FEEDFORWARD OF THE INPUT VOLTAGE

The input voltage is fed forward, as shown in Figure 6.10. In a system with a PFC interface, the output is nearly constant, independent of the changes in the RMS value of the input voltage from the utility. Therefore, an increase in the utility voltage ModifyingAbove upper V With caret Subscript zero width space s causes a decrease in ModifyingAbove upper I With caret Subscript upper L, and vice versa. To avoid propagating the input voltage disturbance through the PFC feedback loops, the input voltage peak is fed forward, as shown in Figure 6.10, in determining ModifyingAbove upper I With caret Subscript upper L Superscript asterisk.

FIGURE 6.10 Feedforward of the input voltage.

6.9 OTHER CONTROL METHODS FOR PFCS

In this book, an average-current-control method is described for controlling PFCs. There are other methods, such as a single-cycle control. The reader is referred to References 4 and 5 for further exploration.

REFERENCES

  1. 1. Philip C. Todd, “UC3854 Controlled Power Factor Correction Circuit Design,” Unitrode Application Note U-134.
  2. 2. Lyod Dixon, “High Power Factor Switching Pre-Regulator Design Optimization,” Unitrode Design Application Manual.

PROBLEMS

  • 6.1 In a single phase, 60-Hz power factor correction circuit, upper V Subscript s Baseline equals 120 upper V left-parenthesis r m s right-parenthesis, upper V Subscript d Baseline equals 250 upper V, and the output power is 300 W. Calculate and draw the following waveforms, synchronized to v Subscript s waveform: ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis, d left-parenthesis t right-parenthesis, and the average current i overbar Subscript d through the output diode.
  • 6.2 In the numerical example given in this chapter, calculate the RMS input current if the utility voltage is 110 upper V left-parenthesis rms right-parenthesis, and compare it with its nominal value when upper V Subscript s Baseline equals 120 normal upper V left-parenthesis r m s right-parenthesis.
  • 6.3 In problem 6.1, calculate the second-harmonic peak voltage in the capacitor if upper C equals 690 normal mu normal upper F.
  • 6.4 In the numerical example given in this chapter, calculate the maximum peak-peak ripple current in the inductor.
  • 6.5 Repeat the design of the current loop in the given numerical example in this chapter if the loop crossover frequency is 25 kHz.
  • 6.6 Repeat the design of the outer voltage loop in the numerical example given in this chapter if the output capacitance upper C equals 690 normal mu normal upper F.

Simulation Problem

  • 6.7 In the simulation diagram of Figure 6.8:
    • Observe the input voltage to the boost converter (output of the diode-rectifier bridge, not modeled here), the inductor current, and the voltage across the load.
    • List the harmonic components of the inductor current i Subscript upper L and the capacitor current i Subscript upper C.
    • Confirm the validity of Equation (6.5) for the current into the output stage of the PFC.

APPENDIX 6A Proof that StartFraction ModifyingAbove upper I With caret Subscript s Baseline 3 Baseline Over ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline EndFraction equals one-half

The output of the voltage regulator upper G Subscript v in Figure 6.6b in steady state is

output of upper G Subscript v Baseline equals ModifyingAbove upper I With caret Subscript upper L Baseline minus ModifyingAbove upper I With caret Subscript upper L comma 2 Baseline cosine 2 omega t comma(6A.1)

in which ModifyingAbove upper I With caret Subscript upper L Baseline 2, by a proper controller design is much smaller than ModifyingAbove upper I With caret Subscript upper L, for example, less than 1.5%. The above expression is multiplied by StartAbsoluteValue sine omega t EndAbsoluteValue to establish the reference for the inductor current. The second-harmonic distortion in Equation (6A.1) results in a third-harmonic distortion in the input AC current. This can be proven by multiplying the second-harmonic component in Equation (6A.1) with sine omega t, in order to see the distortion in the input AC current, as follows:

left-parenthesis minus ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline cosine 2 omega t right-parenthesis sine omega t equals one-half ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline sine omega t minus ModifyingBelow one-half ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline With presentation form for vertical right-brace Underscript ModifyingAbove upper I With caret Subscript s Baseline 3 Baseline Endscripts sine 3 omega t period(6A.2)

In Equation (6A.2), the fundamental-frequency component, due to the second-harmonic distortion, is compensated by the voltage-loop controller. However, the second-harmonic distortion with a peak ModifyingAbove upper I With caret Subscript upper L Baseline 2 results in a third-harmonic frequency distortion with one-half the amplitude. Therefore,

StartFraction ModifyingAbove upper I With caret Subscript s Baseline 3 Baseline Over ModifyingAbove upper I With caret Subscript upper L Baseline 2 Baseline EndFraction equals one-half period(6A.3)

APPENDIX 6B Proof that StartFraction v overTilde Subscript d Baseline Over i overTilde Subscript upper L Baseline EndFraction left-parenthesis s right-parenthesis equals one-half StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript zero width space d Baseline EndFraction StartFraction upper R slash 2 Over 1 plus s left-parenthesis upper R slash 2 right-parenthesis upper C EndFraction

In designing the controller, the output of upper G Subscript v Baseline left-parenthesis s right-parenthesis in Figure 6.6b under dynamic conditions has a strong DC component, a second harmonic frequency component i Subscript upper L Baseline 2, and a low-frequency (less than 15 Hz) perturbation term:

Output of the voltage regulator equals ModifyingAbove upper I With caret Subscript upper L Baseline plus i Subscript upper L Baseline 2 Baseline plus i overTilde Subscript upper L Baseline period(6B.1)

Multiplying the reference current peak in Equation (6B.1) with StartAbsoluteValue sine omega t EndAbsoluteValue, the inductor current is

ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis equals left-parenthesis ModifyingAbove upper I With caret Subscript upper L Baseline plus i Subscript upper L Baseline 2 Baseline plus i overTilde Subscript upper L Baseline right-parenthesis StartAbsoluteValue sine omega t EndAbsoluteValue period(6B.2)

In the circuit of Figure 6.2, assuming that the voltage drop across upper L Subscript d is negligible,

StartAbsoluteValue v Subscript s Baseline left-parenthesis t right-parenthesis EndAbsoluteValue ModifyingAbove i With bar Subscript upper L Baseline left-parenthesis t right-parenthesis equals left-parenthesis upper V Subscript d Baseline plus v Subscript d Baseline 2 Baseline plus v overTilde Subscript d Baseline right-parenthesis left-parenthesis upper I Subscript d Baseline plus i Subscript d Baseline 2 Baseline plus i overTilde Subscript d Baseline right-parenthesis period(6B.3)

Substituting into Equation (6B.3) StartAbsoluteValue v Subscript s Baseline left-parenthesis t right-parenthesis EndAbsoluteValue equals ModifyingAbove upper V With caret Subscript s Baseline StartAbsoluteValue sine omega t EndAbsoluteValue and the inductor current from Equation (6B.2),

ModifyingAbove upper V With caret Subscript zero width space s Baseline StartAbsoluteValue sine omega t EndAbsoluteValue left-parenthesis ModifyingAbove upper I With caret Subscript upper L Baseline plus i Subscript upper L Baseline 2 Baseline plus i overTilde Subscript upper L Baseline right-parenthesis StartAbsoluteValue sine omega t EndAbsoluteValue equals left-parenthesis upper V Subscript d Baseline plus v Subscript d Baseline 2 Baseline plus v overTilde Subscript d Baseline right-parenthesis left-parenthesis upper I Subscript d Baseline plus i Subscript d Baseline 2 Baseline plus i overTilde Subscript d Baseline right-parenthesis period(6B.4)

Noting that StartAbsoluteValue sine omega t EndAbsoluteValue squared equals sine squared omega t equals one-half minus one-half cosine 2 omega t and neglecting the product of v overTilde Subscript d and i overTilde Subscript d,

StartLayout 1st Row StartLayout 1st Row one-half ModifyingAbove upper V With caret Subscript zero width space s Baseline ModifyingAbove upper I With caret Subscript upper L plus one-half ModifyingAbove upper V With caret Subscript zero width space s Baseline i Subscript upper L Baseline 2 plus one-half ModifyingAbove upper V With caret Subscript zero width space s Baseline i overTilde Subscript upper L minus StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over 2 EndFraction left-parenthesis ModifyingAbove upper I With caret Subscript upper L Baseline plus i Subscript upper L Baseline 2 Baseline plus i overTilde Subscript upper L Baseline right-parenthesis cosine left-parenthesis 2 omega t right-parenthesis 2nd Row almost-equals v Subscript d Baseline left-parenthesis upper I Subscript d Baseline plus i Subscript d Baseline 2 Baseline right-parenthesis plus v Subscript d Baseline 2 Baseline left-parenthesis upper I Subscript d Baseline plus upper I Subscript d Baseline 2 Baseline plus i overTilde Subscript d Baseline right-parenthesis plus v overTilde Subscript d Baseline i Subscript d Baseline 2 Baseline plus i overTilde Subscript d Baseline upper V Subscript d Baseline plus v overTilde Subscript d Baseline upper I Subscript d Baseline period EndLayout EndLayout(6B.5)

Equating the perturbation frequency terms on the two sides of the above equation,

i overTilde Subscript d Baseline upper V Subscript d Baseline plus v overTilde Subscript d Baseline upper I Subscript d Baseline equals one-half ModifyingAbove upper V With caret Subscript zero width space s Baseline i overTilde Subscript upper L Baseline period(6B.6)

Recognizing that in the PFC of Figure 6.1a, upper I Subscript d Baseline equals upper V Subscript d Baseline slash upper R. Therefore in Equation (6B.6),

left-parenthesis i overTilde Subscript d Baseline plus StartFraction v overTilde Subscript d Baseline Over upper R EndFraction right-parenthesis upper V Subscript d Baseline equals one-half ModifyingAbove upper V With caret Subscript zero width space s Baseline i overTilde Subscript upper L Baseline period(6B.7)

In the PFC output stage of Figure 6.1a, the voltage and the current are related as

i overTilde Subscript d Baseline equals StartFraction 1 plus s upper R upper C Over upper R EndFraction v overTilde Subscript d Baseline period(6B.8)

Substituting Equation (6B.8) into Equation (6B.7),

StartFraction v overTilde Subscript d Baseline Over i overTilde Subscript upper L Baseline EndFraction left-parenthesis s right-parenthesis equals one-half StartFraction ModifyingAbove upper V With caret Subscript zero width space s Baseline Over upper V Subscript d Baseline EndFraction StartFraction upper R slash 2 Over 1 plus s left-parenthesis upper R slash 2 right-parenthesis upper C EndFraction period(6B.9)
..................Content has been hidden....................

You can't read the all page of ebook, please click here login for view all page.
Reset