Figure A.2 shows the display of three-phase power system consisting of an unbalanced source and two loads in star: balanced nonlinear load and unbalanced linear load.

Figure A.3 shows the balanced nonlinear load. It consists of three bridge rectifiers connected in a star with an RC branch in the dc side (for it has been used as a Universal Bridge block of SimPowerSystems). Figure A.4 shows unbalanced linear load consisting of three star RL branches.

Figures A.5 and A.6 show block diagrams for computing the sum of the squares of the rms values of the harmonics of the phase-to-neutral voltages, line-to-line voltages, line currents and neutral current. We used buffer blocks (to store the signal samples), magnitude FFT (to compute the absolute value of the DFT), submatrix (to extract the values of interest in the results matrix), and matrix sum (to sum the elements of row/column/all elements of the input array) of the signal processing blockset.

From the results of the block diagrams of Figures A.5 and A.6 effective values of voltage and current are determined by the Std. IEEE 1459, Figure A.7.

Finally, Figure A.8 shows the block diagrams that determine the power terms; blocks 3-phase sequence analyzer of SimPowerSystem for the positive sequence components of the voltage and current are used.

The simulation model of an ac–ac converter, and block diagrams for obtaining compensation currents are included in Chapter 3, Figures 3.11 and 3.12. The block diagram of Figure 3.12 uses the dot product block of Simulink to determine the different power variables.

Figure A.11 shows block diagrams of the subsystems that perform transformation of phases coordinates to 0αβ coordinates (left figure) and 0αβ coordinates to phases coordinates (right figure). The Simulink blocks are used: matrix concatenate input signals to create a contiguous output signals, and product to perform the matrix multiplications.

Figure A.12 presents the calculation of the instantaneous power variables indicated in Figure 3.34, Chapter 3; The Simulink block and transfer Fcn were reused to simulate a low-pass filter of second order to determine the oscillatory component of the instantaneous power.

Simulink blocks, permute dimensions, and matrix concatenate, provide different current components as shown in Figure 3.34 of Chapter 3 to get the compensation voltage, Figure A.13.

Figure A.15 shows how to obtain reference currents; the real power is determined from a Butterworth low-pass filter of fourth order from analog filter design block of signal processing blockset.

Data-type conversion, logical operator, and relay blocks of Simulink, and analog filter design of signal processing blockset as in Example 4.1, are used to model the control circuit of static compensator, Figure A.17.

Figure A.18 shows the general arrangement of the MATLAB–Simulink file used for Example 4.5. The APF block contains the power circuit of the active conditioner, including the passive components and the measuring elements (signals grouped in the buses medV, medI). The block Supply contains the voltage sources and the equivalent line impedance of the supply network; and the block Load contains the unbalanced nonlinear load. The block APF Control calculates the control references and sets the gate signals for the power transistors of the converter (bus Dp).

Figure A.19 shows the components that model the supply network, with unbalanced voltages, as well as its equivalent impedances. Figure A.20 shows the load used in Example 4.5.

Figure A.21 presents the power circuit of the APF, with the passive components and coupling transformers, as well as the measuring elements. The simulation model of Example 4.5 has been implemented to model approximately the experimental prototype described in Section 4.6 and Appendix II. The coupling transformers T_P have a turn ratio of 1:2 to adapt the voltage levels between the dc and ac sides of the converter. So, the reference voltage of each dc side capacitor is set to 250 V, and the entire set works with low voltage levels. The model of the transformers includes the short circuit and magnetizing impedances, as well as the L_P inductance and its dc resistance. On the other side, the measurements are grouped in the buses medI and medV. The bus medI contains the supply currents i_Sabcn, load currents i_Labcn and compensation currents before, i_CPabc, and after, i_C2abc, the coupling transformers T_P. The bus medV contains the supply voltages, v_Sabc, and those of the dc capacitors, v_dc1 and v_dc2. The incoming signal bus Dps contains the logic switching signals for the six power transistors of the converter.

Figure A.22 shows the structure of the general control block of the APF. A sample and hold, ZOH, of 50 μs is applied to the input signals to model the effect of the DSP board used in the calculation of this control. Afterwards, the signals are divided by their nominal values to set the later calculations in per unit values. Block voltage refs PU calculates the balanced sinusoidal voltage references vLref that are used in Example 4.5b. Block currents refs PU calculates the compensating current references, iCref, of the converter; including the regulation of the dc side voltages. Finally, the block switching signals sets the gate logic signals for the power transistors, with the periodical sampling, PS, current control described in Section 4.3.2.

Figure A.23 shows the structure of the voltage refs PU block. It calculates the balanced fundamental and amplitude regulated component of the supply voltage measurements. In the first stage the signal v+, that contains the balanced fundamental component of the voltages, is obtained with the set of phase shift filters. The rest of components are filtered in a second stage with a band pass filter, and its amplitude is regulated to the nominal value. In the third stage the three-phase signal v1 + PU is built, also with the use of a phase shift filter and with null instantaneous zero-sequence component.

Figure A.24 shows the modeling of the trigger circuit of the converter, that in the experimental setup is made with an external circuit that compares directly the measured compensating current, iCmed, with the corresponding reference, iCref, provided by the DSP board; with a previous sample and hold, ZOH, to model the sampling and the corresponding delay, 1/z, of the digital board. The initial scale factor 2 is due to the turns ratio of the coupling transformers T_P. The second ZOH models the PS sampling of the external circuit, and the logic gates set the complementary trigger signals for each branch of the converter, as well as the validation through the RUN signal to run/stop the APF.

Figure A.25 shows the control block to calculate the current references iCref. The power balance of the APF is in the upper part of the figure, and calculates the compensating current references iCL due to the load currents. The block v_dcreg calculates the additional active component to compensate the internal power losses of the conditioner to regulate the dc-side voltages. On the other part, the selector iCbal that appears in the upper part of the power balance allows us to use the measured value of i_C in this balance, when the APF is working. The values of i_C can differ substantially from their reference over relatively long time periods, and this way the estimation of the internal power balanced is enhanced, reducing possible power fluctuations. Thus, the i_dcreg component is excluded from this balance, assumed that it has a low dependence on the active/desired component of the load currents. Finally, the saturation block Sat2PU limits the compensating currents at the output of the converter, to avoid instantaneous values of these currents higher than those assigned to the physical devices.

Figure A.26 shows the implemented control for the regulation of the dc side voltages. The three-phase signal I_dc3F has the same waveform as the voltage reference vLref used, and an amplitude proportional to the difference between the total voltage of both capacitors and its reference V_dcREF. A low-pass filter is applied to this signal to allow the oscillating component of the instantaneous power that is being compensated to be provided by the APF, considering that the dc side capacitances had been dimensioned for this task. A small dc component, i_dcdif, proportional to the difference between both capacitor voltages, is added to this signal to balance them. When zero-sequence currents are to be compensated, it produces differences between both voltages. The low-pass filter selects the dc component to be compensated, which has an accumulative effect, and so as to maintain this difference in acceptable values.

Finally, Figure A.27 shows the control block Currents refs PU, which is used to calculate the current references for the case 4.5b, where the compensated currents are aimed to be proportional to the balanced fundamental component of the voltages. The difference with figure A1.8 is in the construction of the signal i_aL with the voltage reference v_Lref.

The nonlinear load is modeled with the block “Universal bridge” of the library SymPowerSystem from Simulink. Figure A.29 shows the Simulink scheme used.

Furthermore, the block labeled “PWM” generates trigger pulses of the IGBTs from the comparison reference signal and the output signal of the inverter. This includes a D flip-flop, which limits the switching frequency below the clock frequency. Figure A.30 shows the scheme in Simulink in this block.

The “Reference calculation” block has as output signal the reference voltage that the active filter must generate. Their scheme in Simulink is shown in Figure A.31. The fundamental component of the input signal is obtained by the block labeled “Fundamental.” This block has been developed using the scheme shown in Figure A.32. The K_v and K values are adjusted depending on the selected control strategy, by detecting the current source, by detection of the load voltage and hybrid strategy.

An HCS-type load is used, which is composed of a three-phase noncontrolled rectifier with an inductance and resistor connected in series at the dc side. Figure A.35 shows the scheme of the model used.

The other blocks included in the scheme in Figure A.34 are the same as Examples 5.1, 5.2 and 5.3, according to the compensation strategy applied to the active filter.

Figure A.37 shows the components that model the supply network, with unbalanced and harmonic voltages, as well as its equivalent impedances. Figure A.38 shows the load used in Example 7.1, including the ideal switch to produce the load change in the last stage of the simulation.

Figure A.39 presents the power circuit of the UPQC, with the passive components and coupling transformers, as well as the measuring elements. The simulation model of Example 7.1 has been implemented to model approximately the experimental prototype described in Section 7.3 and Appendix II. The shunt coupling transformers T_P have a turn ratio of 1:2 to adapt the voltage levels between the dc and ac sides of the converter. So, the reference voltage of each dc side capacitor is set to 250 V, and the entire set works with low voltage levels. The model of the transformers includes the short circuit and magnetizing impedances. The series coupling transformers T_S have a turn ratio of 1:1. The R_SC_S series branch explained in Section 7.2.3 is included as the snubber circuit of the bypass ideal switches below the series transformers. Inductance L_S2 corresponds to the leakage inductance of these transformers. On the other side, the measurements are grouped in the buses medI and medV. The bus medI contains the supply currents i_Sabcn, load currents i_Labcn and compensation currents before, i_CPabc, and after, i_C2abc, the coupling transformers T_P. The bus medV contains the supply voltages, v_Sabc, load voltages, v_Labc, and those of the DC capacitors, v_dc1 and v_dc2. The incoming signal bus Dps contains the logic switching signals for the twelve power transistors of the converter.

Figure A.40 shows the structure of the general control block of the UPQC. A sample and hold, ZOH, of 50 μs is applied to the input signals to model the effect of the DSP board used in the calculation of this control. Afterwards, the signals are divided by their nominal values to set the later calculations in per unit values. Block voltage refs PU calculates the references associated with the control of the series converter, like the load voltage reference vLref and the compensating voltages for the series filter, vCref. These signals are used in the block Gen_As, along with the values of the dc side voltages, to calculate the pulse widths, As, for the power transistors of the series converter in each sampling period. Block currents refs PU calculates the compensating current references, iCref, of the shunt converter; including the regulation of the dc side voltages. It also calculates the corrective signal REis (proportional to the tracking error of the supply currents i_S), to be included in the control of the series converter. Finally, the block switching signals sets the gate logic signals for the power transistors, modeling the control methods implemented in each converter, as described in Section 7.2.1.

Figure A.41 shows the structure of the voltage refs PU block. It calculates the balanced fundamental and amplitude regulated component of the supply voltages v_Sabc, to be used as reference for the load voltage vLref (This control block is the same as that used in Example 4.5, (see Figure A.23). With this signal and the prefiltered value of v_S sets the main component of the series compensating voltages, vCref; afterwards, the corrective signal REis is added. The saturation block, Sat ± 0.3 pu, limits these compensating voltages to adequate values, according to the turn ratio of the series transformers, the assigned values for the dc-side capacitors, as well as the taking into consideration the dimensions of the equipment and the targets of the compensation.

Figure A.42 shows the calculation of the duty ratios, As, for the three branches of the series converter. They use the last measured values of the dc side voltages to set accurate values of the average applied series voltages in each sampling period. Some saturation blocks are used to prevent divisions by zero (Saturation 3), and to limit the output signals As between 0 and 1.

Figure A.43 shows the modeling of the trigger circuits of the converters. The As signals for the series converter are compared with a triangular wave that defines the commutation frequency at 20 kHz, with a previous sample and hold, ZOH, to model the sampling and the corresponding delay, 1/z, of the DSP board. The trigger control of the shunt converter is made with an external circuit in the experimental setup, that compares directly the measured compensating currents, i_Cmed, with the corresponding references, iCref, provided by the DSP board; with the previous sample and hold and corresponding delay. The initial scale factor 2 is due to the turns ratio of the coupling transformers T_P. The second ZOH models the PS sampling of the external circuit, and the logic gates set the complementary trigger signals for each branch of the converter, as well as the validation through the RUN signal to run/stop the APF.

Figure A.44 shows the control block to calculate the current references. The power balance of the UPQC is in the upper part of the figure, and calculates the compensating current references iCL due to the load currents and supply voltage distortions. The block vdcreg calculates the additional active component to compensate the internal power losses of the conditioner to regulate the dc side voltages. This block vdcreg is the same as that implemented for the shunt APF (See Example 4.5, Figure A.26). The Dev block calculates the corrective component for damping the load voltage deviations; and the Dis block calculates the corrective component for the supply current deviations, that is sent to the control of the series converter. On the other part, the selector iCbal that appears in the upper part of the power balance allows to use the measured value of i_C in this balance, when the APF is working. The values of i_C can differ substantially from their references during relatively long time periods, and this way the estimation of the internal power balanced is enhanced, reducing possible power fluctuations. Thus, the idcreg component is excluded from this balance, assumed that it has a low dependence with the active/desired component of the load currents, and/or a more ideal series compensation. Finally, the saturation block Sat2PU limits the compensating currents at the output of the converter, to avoid instantaneous values of these currents higher than those assigned to the physical devices.

Figures A.45 and A.46 show the calculation of the corrective components GEvL and REiS, as well as their corresponding activation only when the UPQC is working.

Figure A.48 shows the structure of the general control block of the UPLC. A sample and hold, ZOH, of 50 μs is applied to the input signals to model the effect of the DSP board used in the calculation of this control. Afterwards, the signals are divided by their nominal values to set the later calculations in per unit values. Block voltage refs PU calculates the references associated with the control of the series converter, like the load voltage reference vLref and the compensating voltages for the series filter, vCref. These signals are used in the block Gen_As, in the way as in Example 7.1 (see Figures 7.1 and A.42). Block currents refs PU calculates the compensating current references, iCref, of the shunt converter; including the regulation of the dc side voltages. Finally, the block gate signals sets the gate logic signals for the power transistors, modeling the control methods implemented in each converter, in the same way as in Example 7.1 (see Figures 7.1 and A.43).

Figure A.49 shows the structure of the Voltage refs PU block. It calculates the balanced fundamental and amplitude regulated component of the supply voltages v_Sabc, to be used as reference for the load voltage vLref. This control block is the same as that used in Example 4.5 (see Figure A.23), but this time including the calculation of the quadrature signal V_q, according to expression (7.36). The block Fund. Comp. calculates the fundamental components of the load voltages, vLf, to be used in the voltage correcting terms at the control of the shunt converter. The references for the series compensating voltages, vCref, are built with the difference between the prefiltered value of v_S and the reference for the load voltages, to isolate the load side from the distortions and unbalances of the supply 1 side; as well as the necessary values for the Power Flow Control through the series converter explained in Section 7.4.2 and implemented in the block UPFC refs. This block also calculates the current reference, iCregV, for the voltage control in the load side; that is set to the current refs PU block and the shunt converter. Finally, the saturation block, Sat ± 0.3 pu, limits the series compensating voltages to adequate values, according to the design considerations of the UPLC/UPQC.

Figure A.50 shows the calculation of the fundamental components of the load side voltages. It uses the signals vPabc and vQabc, which come from the block vLref, to obtain the unitary sine and cosine signals. These signals multiply the instantaneous values of the voltages of each phase, which are filtered to obtain the main component. With a closed integral control loop, these magnitudes are set with zero steady state error and allow to build the fundamental component of each phase voltage in approximately two and a half cycles.

Figure A.51 shows the scheme of the UPFC refs block. It calculates the references for the series converter in the vCrefPQ block, and the references for the shunt converter in the iCregQ block.

Figure A.52 shows the calculation of the UPFC references for the series converter, according to the equations (7.37)–(7.44). The step blocks Pref and Qref set the references of the active and reactive powers, to define the current references, iREFp and iREFq, as well as the voltage signals references vCd and vCq of the power flow controller. The signals E_p, E_q are obtained from the block vLref, and are used to calculate the magnitudes in the d–q frame.

Figure A.53 calculates the additional current reference iCregV for the shunt converter. In the first stage it obtains the filtered rms value of the aggregate value of the load voltages, to set the reactive current component according to expression (7.35).

Figure A.54 shows the control block to calculate the current references. It has the same structure as that implemented in Example 7.1, with the addition of the current reference iQVref of the UPFC features, and the use of the fundamental components of the load voltages VLf to reduce the damping term GEv at that frequency in the block Dev.

Finally, Figure A.55 shows the calculation of the corrective component GEv. This damping term is reduced for the fundamental components of the voltage; and this signal is included in the internal power balance of the conditioner, so it actuates on a net basis only in the transient states.

To solve the load flow problem a tool included specifically in the SimPowerSystems library from MATLAB–Simulink has been used. To use this tool the Simulink model of the network shown in Figure A.56 must be built. Each of the nodes must be defined by type. Thus, node 1 will be the swing node, nodes 2 and 4 are PQ type and node 3 is PV type.

The distribution grid is modeled by means of a programmable three-phase source of infinite power. This source allows inclusion of imbalances and harmonics in the voltage.

The “PWM” block generates trigger pulses for the IGBT bridge from the reference signal and the output of the inverter dc/ac. This block is the same as the one used in Example 5.2.

The reference signal is calculated by means of the “Reference” block. Since the active power is injected into the grid and the voltage vector at the point of connection, VDG, the reference current signal to be generated by the inverter is determined. Figure A.58 shows control scheme in Simulink. The “u^2” block calculates the instantaneous norm.

The “Direct” block determines the positive-sequence component of the network voltage. Its scheme is shown in Figure A.60; a and a² operator are implemented with all-pass filters defined in Simulink using its transfer function.

The “Fundamental” block determines the fundamental component of the input signal. Its scheme is the same as described in Example 5.1.

The “Inv Transformation” block performs the inverse transformation, whereby the direct-sequence voltage vector of the fundamental harmonic is obtained. Figure A.61 shows its scheme.

The control strategy is implemented in “Reference” block. The scheme of this block is shown in Figure A.63. Used blocks have been defined in the previous Examples, except the “Power” block, which calculates the average power of the load from the product of the voltage vector at the point of common connection and the load current vector.

For other simulation examples presented, the only block having something new is called “Reference Calculation”. This block determines the reference signal to achieve the proposed control objective. The scheme is shown in Figure A.65. In this scheme, “Direct” and “Inv Transformation” blocks are the same used in Example 8.3. Figure A.66 shows “0-Component” block scheme.