Figure B.1 shows the general scheme of the laboratory prototype. Each of its components are highlighted. Hereinafter, the main characteristics of the devices used in the prototypes designed for this purpose are presented.

Model 4500-iL from California Instruments has been used as a power supply. It is a programmable three-phase source, which can supply from 4.5 kVA to 10 A in a voltage range from 0 V to 150 V and upto 5 A when the range is selected as 0–300 V. This source allows programming of the voltage signals required for testing Electromagnetic compatibility according to IEC 61000. It has an RS-232 connection that together with the CGUI32 software allows programming (Figure B.2) through a PC. In series with the voltage source is connected an inductance of 2.34 mH with a resistance of 1.3 Ω. These elements allow us to consider the effect of grid impedance on the laboratory prototype.

Two types of nonlinear three-phase loads have been used for different essays. They are based on a noncontrolled three-phase rectifier. The first load at the dc side is connected a high inductance in series with a resistor and the second load a capacitor in parallel with a resistor are connected at its dc side.

A three-phase rectifier configuration is composed by a 36MT60 module from International Rectifier. The maximum permissible current at the dc side of this device is 35 A and the maximum voltage repetitive peak is 600 V. For quick load setup, the rectifier module is installed in a box with an inductance of 55 mH and a capacitor of 2200 μF, as it is shown in Figure B.3. A switch allows choice of two load settings, inductance in series or capacitor in parallel. An external variable resistor completes the load.

The second configuration is based on the GBPC2510 rectifier module from International Rectifier. It is a single-phase bridge rectifier which supports a maximum current at the dc side of 25 A and a repetitive peak maximum voltage of 1000 V. Similarly as in the previous configuration was assembled in a box that enables easy setup with an inductance of 55 mH and a capacitor of 2200 μF at the dc side of each rectifier. Figure B.4 shows the load formed by the three single-phase rectifier and the switches that allow selecting energy storage elements at the dc side of each rectifier.

On the other hand, the active filter is composed of three SKM50GB123 IGBT modules from Semikron. Each module is formed by two IGBTs connected with their respective antiparallel diodes as shown in Figure B.5. The main features include the maximum collector-emitter voltage (V_CE) of 1200 V, the collector current (I_C) can be up to 50 A and gate-emitter voltage (V_GE) must be between ±15 V. Modules are mounted on a heat sink of anodized aluminum which would have included a fan, allowing cooling of the set.

For gating drivers, three SKHI 22A from Semikron are used. These devices allow control of two IGBTs connected in half-bridge. The setup has additional features such as short-circuit protection, monitoring V_CE voltage, transformer isolation between the control circuit and gate, blocking simultaneous firing of the two IGBTs. For gating pulses, an additional circuit is designed to adapt the output 5 V generated by the PWM circuit and input 15 V of the trigger drivers of the transistors. The inverter set is shown in Figure B.6.

At the dc side of the inverter are connected in series two capacitors of 2200 μF and 700 V, allowing, at the midpoint have a fourth conductor for those topologies that require it.

Coupling to the network is performed with three single-phase transformers 1 kVA of 1:1 ratio. Figure B.7 shows an image of the transformer used.

On the other hand, the inverter output has a ripple filter whose function is to remove ripples formed due to high-frequency components, present in the compensation voltage generated by the active filter, Figure B.8. The ripple filter is composed of an inductance of 0.13 mH and capacitor of 50 μF.

In the configuration of hybrid filter, two LC branches tuned at the 5th order harmonic and 7th order harmonic are used. Figure B.9 shows the two passive filters. The branch for the 5th harmonic is formed by an inductance of 13.1 mH and a capacitor of 30 μF. Furthermore, the branch tuned to 7th harmonic is composed of an inductance of 6.5 mH and a capacitor of 30 μF. Two switches allow connection/disconnection of each LC branch.

Different control strategies have been implemented in a modular system that integrates PPC 1005 DS board from dSpace. It has a PowerPC 750GX processor running at 1GHz. Figure B.10 shows this card and Figure B.11 its block diagram. The input-output cards are connected to the DS1005 via a high-speed bus (PHS bus, peripheral high-speed) of 32 bits and a transfer rate of 22 MB/s.

As input, the DS 2004 board is used, Figure B.12. It has 16 differential input channels, each with an A/D with a resolution of 16 bits. The converter performs A/D conversion at 800 ns. Each channel has a buffer of up to 16384 values. To convert the measured data it offers two modes: continuous and events mode. In the first, when the conversion is complete, it automatically starts the next. In the second, the conversion begins when an event is received (by software or trigger). Figure B.13 shows its block diagram. Connection with DS PPC 1005 is performed by means of the PHS bus.

As output card the DS 5101 DWO board is used, Figure B.12b. This card allows generation of a TTL pulse pattern upto 16 channels. These pulses can be defined by programming. Figure B.14 shows the block diagram.

The set of three cards are connected into an expansion box that includes a communication card for connection to the PC. In this design, the communication is done through an Ethernet card. The computer just shows the user interface: the real-time calculation is performed by the DS 1005 PPC board. There are two connector panels where the input signals from sensors and TTL output signals were connected; the latter are responsible for generating the gating pulse train required for inverter gate. Figure B.15 shows elements of the configuration of the control system.

All cards can be configured and programmed graphically using MATLAB–Simulink. The link between software and hardware is the real-time interface RTI (Real Time Interface) from dSpace. So, when you have a model in MATLAB–Simulink block libraries, RTI allows connection of the cards with Simulink blocks. The RTI block library enables parameterization of the inputs and outputs of the cards. Once connected and configured the inputs and outputs to the model, the C code is generated through the toolbox Real Time Workshop (RTW) from MATLAB. The real-time model is compiled and read, and starts to run automatically in real-time hardware.

Alternatively, there is another tool called ControlDesk from dSpace that can interact with the system in real time. With this it is possible to monitor the variable set of interest, turning your PC into a virtual instrument that allows the user to control the designed system in real-time. Figure B.16 shows the main screen of the applications that have been done in this work.

The input signals to the control system are voltages and currents. The LV-25-P sensor from LEM is used for the voltage signals, Figure B.17. It is a voltage transducer of the Hall effect. It is a closed loop type, which reduces the effect of magnetic hysteresis, providing an almost linear characteristic with high accuracy. It also provides galvanic isolation between primary and secondary, being able to connect their primary voltage up to 1600 V. The voltage ratio depends on the resistance that is connected to the transducer secondary which should be within a range specified by the manufacturer. In this design, it has chosen a resistance value of 100 Ω, whereby the voltage ratio is 1:240.

Respect to the current sensor has been used the LA35-NP from LEM (Figure B.18). It is a Hall effect sensor of closed loop, with a configurable current ratio. Depending on the type of connection of the pins can achieve until five different relationships. The choice is 1/1000, with a primary nominal current of 35 A.

The voltage and current sensors are grouped for easy feeding their internal circuitry. Figure B.19 shows a stack composed of 16 current sensor and 9 voltage sensor.

For measures that are included in the different tests that appear in this work has been used a three-phase network analyzer, Fluke 434. This instrument measures virtually every power system parameter, such as voltage, current, power, energy, unbalance, flicker, harmonics, and interharmonics. It has four channels in which the voltage and current of all three phases and neutral are measured simultaneously. This device offers a voltage accuracy of 0.1% and meets all the requirements of IEC 61000-4-30 Class A. Figure B.20 shows an image of the measuring equipment.

On the other hand, a four channel digital oscilloscope is used, exactly the WaveSurfer 424 from Lecroy, Figure B.21. Among its features are a bandwidth of 200 MHz and a sampling rate of 2 GS/s. It has a vertical resolution of 8 bits and a vertical sensitivity of 1 mV/div. This oscilloscope can display and capture instantaneous signals in an easy and practical way, offering different colors for different channels. The waveforms shown as experimental results have been captured with this oscilloscope.

The calculation of the current reference is developed in Simulink. The “Build” tool allows the program to run in the microprocessor built into the DS1005 PPC board from dSpace. Throughout the previous chapters were described the strategies employed, here, Simulink schemes that are designed for different experimental prototypes are described.

In Figure B.22, general scheme in Simulink is shown. The input channels used with DS 2004 board have been included. This scheme has been used for all experimental prototypes developed in Chapters 5 and 6. In some of them has only been necessary measuring the source current or the voltage at the load side, it would be sufficient to cancel in the control scheme the corresponding channels (1–3 for voltage and 5–7 for current). Each input includes a scale factor of 240 to the voltage signals and 1.9644 for the current signals. The main difference between the prototypes to another is the block labeled as “Reference calculation”.

Channels 13 and 14 of DS 2004 board are assigned to measure the voltage across the terminals of the capacitors connected to the dc side of the inverter. These values along with the source currents are the inputs of the block that is designated as “secondary control”. This block has been implemented control strategy for regulating the voltage on the capacitors. Figure B.23 shows the design of this block, where the reference voltage is 100 V.

Figure B.23 shows the “Direct” block, which determines the positive sequence component of the input vector, in this case the source current vector. Figure B.24 shows the structure of the block, where the operator “a” and “a²” are configured with all-pass filters through their transfer functions.

On the other hand, Figure B.23 includes “Fundamental” block, inside which the computation of the fundamental component of the input signal is developed. Figure B.25 shows its internal structure.

The block labeled “Inv transformation” is the one responsible for obtaining the inverse transformation of Fortescue from the positive sequence fundamental component. Figure B.26 shows block scheme, where “a” and “a2” operators are included, which are developed in the same way as the block “Direct”.

The “PWM output” block is common for all practical developments. In it the gating pulses applied to the different IGBTs are generated. Figure B.27 shows the contents of this block. This in turn has a subsystem designated “PWM”, which is what makes the comparison between the reference signal and the output signal of the compensation device. On the other hand, there is another subsystem which will activate or deactivate the active filter from a “stop” signal. Finally, the chosen outputs of DS 5101 DWO board are shown.

In the experimental prototype control strategies have been applied as follows: detection of the source current, detection of the load voltage, and a hybrid strategy, which combines source current and load voltage detection. The block labeled as “Reference calculation” in Figure B.22 includes the scheme shown in Figure B.28. Here, the “Fundamental” block has the same configuration as that shown in Figure B.25. The gain block designated by “K” is used to select the value of the suitable proportionality constant of the source current in the strategies, by detection of the current source and hybrid or cancel source current with K = 0 for strategy by detection of the load voltage. Similarly “K_v” is set to “−1” for strategies by detection the load voltage and hybrid. K_v will be “0” for the strategy by the detection of the source current.

The configuration of the experimental platform is made with a connector panel, whose front view is shown in Figure B.30. The series and shunt inverters can be included with panel selectors, between the supply side and load side measurements; and provides for up to four three-phase or single-phase loads to be preconnected. The panel also allows selection between two power sources: directly with the laboratory network or through a variable autotransformer. Figure B.31 shows the back view of the configuration panel with the wiring to the different components of the experimental platform.

The power supply used for the experimental cases is a three-phase variable autotransformer, composed by three single-phase units of 0–230 V, 50 Hz, 25 A, with star connection. The fundamental phase to neutral voltages can be set independently, and the harmonic distortion introduced is the existing in the supply network of the laboratory. Figure B.32 shows the autotransformer set, with the manual cursors and voltage indicators for each phase.

The three-phase unbalanced nonlinear load is similar to those applied in the simulation cases (see Figure 4.30): a single-phase bridge diode rectifier with inductive load on the dc side, DLR load, for phase 1; a single-phase bridge diode rectifier with capacitive load on the dc side, DCR load, in phase 2; and a linear resistor in phase 3. Figure B.33 shows the general arrangement of this load, and the right side picture of the figure shows in detail the connection of the diode bridges, smoothing inductances, and the snubber circuit of the DLR load. The diode bridges are made with a GBPC2510 rectifier module which supports a maximum current at the dc side of 25 A and a maximum repetitive peak voltage of 1000 V. The main linear components have been taken from the selectable impedance boxes shown in the figure. The resistances box has a nominal power of 1200 W per phase, and 900 VAr for the inductors and the capacitors box. This modular set allows to easily configure different load compositions, to produce load changes, etc.

The experimental platform has two three-phase IGBT converters (Semikron SKM50GB123D) that are connected back to back, with a common dc link composed by two electrolytic capacitors, C_dc+ and C_dc– of 2200 μF, 400 V each one. The middle point of the dc link is connected with the neutral wire of the three-phase line. Figure B.34 shows the arrangement of both inverters. The shunt converter is at the left side of the picture and provides the dc side capacitors; and the series converter is at the right side. The IGBTs of the converters are commanded by SKHI 22A gate drivers that works with input signals of 0–15 V. The series converter has an additional circuit to adapt the 5 V pulses of the DSP board to the voltages levels of the gate drivers, including a validation input to run/stop the gate signals from the control program. The voltage level adaptation for the shunt converter is made in the external circuit that provides the PS current control (see Figure B.45).

The coupling of the shunt converter to the network is made with three single-phase transformers of 4 kVA, with a turn relation of 1:2; to set the reference values of the dc side capacitors at 250 V each. Figure B.35 shows the arrangement of the coupling transformers.

Figure B.36 show the inductors L_P (50 mH) used at the output of the shunt converter. The smaller inductors that appear in the lower part of the picture (5 mH) form part of the flexible configuration system of the general platform to test different compositions for the passive components of shunt APFs; as well as the manual switches that appear at the left side.

Figure B.37 shows the R_PC_P branch used for the shunt APF experimental case, with capacitors of 1 μF, 250 Vac; and resistances of 22 Ω. Figure B.38 shows the R_PC_P branch for the UPQC case, with capacitors of 15 μF, 300 Vac; and resistances of 2.5 Ω.

Figures B.39 and B.40 show the series coupling transformers T_S and smoothing inductors L_S applied at the output of the series converter. The coupling transformers have a nominal power of 4 kVA and a turn relation 1:1; and the series inductors are of 25 mH.

The voltage and current sensors used in the platform are the same as those described in Section B.1 (see Figures B.17 and B.18); but the current transducers are configured for a range of 14 A and therefore the ratio between the measured current and the voltage output signal is 2 A/V. Figure B.41 shows the arrangement of the sensors for the whole platform, in a stack of three trays with four current and three voltage measurements each.

Both converters are controlled with the DSP board DS1103 from dSPACE. It has similar features to the DS1005 system explained in Section B.1, but it works with a single board design (see Figure B.42). The DS1103 board has a main processor, PowerPC 604e that runs at 400 MHz and executes the real-time applications. The board is connected with the host PC via an ISA bus and a host interface communications protocol, where the host PC acts only as a user interface; although some control variables can be set from the ControlDesk applications. The Master PPC provides up to 20 analog input channels and 8 analog output channels with a voltage range of ± 10V. Four analog input channels have their own A/D converter and a resolution of 12 bits, and the remaining 16 inputs have a resolution of 16 bits and share the A/D converters in groups of four multiplexed channels; while the analog outputs have a resolution of 14 bits. It also has several configurable I/O bit channels with TTL voltage range, which in this case are used as status signals from external circuits. The board also has a slave DSP (TMS320F240) that runs at 20 MHz, with its own inputs and outputs, focused in PWM pattern generation.

The DS1103 board is connected in a 19″-rack industrial PC, see Figure B.43, where the MATLAB–Simulink and dSPACE–ControlDesk applications are installed to design and develop the control and monitoring programs. The input/output signals are plugged through the connector panel CP1103 shown in Figure B.44. The BNC connectors of the left side correspond to the analog input and output signals of the main processor, while at the right side there are various pin connectors for digital input/output, or the concentrated signals of the slave processor that goes to the series converter.

Figure B.45 shows the external circuit for the realization of the Periodic Sampling current control for the shunt converter. It receives the signals from the i_CPabc LEM current sensors and their references generated by the DS1103 board through BNC cables. In the first stage these signals are compared with fast voltage comparators (LM311) to generate a trigger signal per phase. These signals are retained in “D”-type flip-flop circuits (CD4013) that are activated with the rising edge of a clock signal that defines the commutation frequency (20 kHz). These circuits also generate the direct and complementary signals for the gates of each phase branch. In the final stage these six signals are validated, through AND logic gates (SN74LS08N) with an additional digital output generated by the DS1103 board to start/stop the shunt converter.

Figure B.46 shows the external circuit for checking the series converter currents i_CSabc. It checks that these currents are under admissible values for the physical components (±14 A). The analog signals provided by the LEM transducers for these currents come through three BNC connectors. In a first stage, these three voltage signals are compared with preset references (±7 V) to check that they are within the acceptable range. This stage is made with differential comparators (LM741) and in the second stage the voltage levels are adapted to the TTL standards. Finally, with AND logic gates (SN74LS08N) a final status signal is derived, with 0 V level as alarm condition. This output signal goes through the fourth BNC connector to a digital input of the connector panel CP1103 (see Figure B.36), where it acts as a validation signal for the activation of the power converters of the UPQC.

Finally, as mentioned in the description of the experimental platform, the control programs can be developed in the Simulink environment; where they are compiled and sent to the DSP board for real-time execution. On the following, the programs used in the experimental cases of this section will be described.

Figure B.47 shows the general arrangement of the MATLAB–Simulink file used to obtain the experimental results of the UPQC case. The block “Medidas” takes the signals of the voltage and current LEM sensors, and scale them to their real values. The block “Control” calculates the internal references of the conditioner in the way exposed in Chapter 7, and determines the values of the compensating currents i_CPref of the shunt converter and the duty cycles As of the series converter. The block “Trigger signals” uses the calculated references to set the outputs of the DSP board. The block “Safety” checks that the internal variables of the active conditioner (v_dc, i_CP, i_CS) are under the limits admitted by their physical components, and sets the variable RUN to allow the activation of the converters. This variable also activates some parts of the calculation of the control references.

Figure B.48 shows the components of the block “Medidas”, with the acquisition, scaling and conditioning of the input signals. The analog signals of voltages and currents of the supply and load sides are acquired through the multiplexed A/D converters CON1 to CON3. Each multiplexer is devoted to the measurements of one phase. After the corresponding scaling, they are rearranged in three-phase buses by magnitude. The dSPACE DS1103 board has four input channels with their own A/D converter, that is used for the measurement of the shunt converter currents, i_CPabc, and for the total voltage of the dc side capacitors, V_dctot. One channel of the fourth multiplexed A/D converter is used for the measurement of the voltage of the upper dc side capacitor, V_dc1. Finally, the currents that flow through the series converter, i_CSabc, are also measured with LEM transducers and the results are checked in an external circuit to be under limits. The digital input Ics_ok is the output of this circuit and is used to validate the activation of the converters (see Figure B.46).

The outputs of the control program are located in the block “Trigger signals”, shown in Figure B.49. The current references for the shunt converter are scaled and sent to their respective D/A converters, for the external circuit that makes the PS current control (see Figure B.45). The duty cycles A_S are sent to the slave processor of the DSP board, where it generates the PWM patterns with a switching frequency defined in this control block (20 kHz). The signal RUN is sent as a digital output to validate the gate signals of the power transistors. The signal sent with the main processor is the validation signal for the PS current control circuit (see Figure B.45), and the signal sent with the slave processor goes to the circuit that adapts the TTL voltage levels of the DSP outputs to the CMOS levels needed by the IGBT drivers of the series converter (see Figure B.34).

Figures B.50–B.54 show the checks made in the Safety block. The blocks “Cond_Icp” check that the shunt converter currents are below 14 A, in absolute value. When this condition is not satisfied the block “Memory” retains this situation and inhibits the activation of the RUN signal. This condition can be monitorized in the ControlDesk application, and it must be reset manually to activate the power converters again. The block “Cond_Ics_ok” acts only as an interlock for the corresponding signal. The minimum and maximum conditions for the voltage of the dc side capacitors are checked separately to monitorize the condition that has inhibited the gate signals. Finally, the constant Manual_RUN is used to activate manually the start/stop of the UPQC, through the ControlDesk application.

Figure B.55 shows the structure of the block “Control”. The internal power balance is in the upper part of the figure, with a similar implementation to that explained in the simulation models (see Figure A.9), and sets the main shunt converter current reference IcpL. The block “Vs_fund” obtains the balanced, sinusoidal, regulated load voltage reference VL_REF. The block “Comp_FS” calculates the reference for the series compensating voltage, and the block “Refs_FS” calculates the duty ratios for the three branches of the series converter, considering the actual values of the dc side voltages. The block “Reg_Vdc” obtains the additional current to regulate the dc side voltages, the block GEv calculates the voltage error damping term, and the block “IL_filt” obtains the pre filtered load currents. Figures B.56–B.61 show the details of this blocks, that are very similar to those explained in the simulation model. There are only small arranging differences, like the concentration of the series converter references in the block “Comp_FS”, including the calculation of the current damping term REis or the estimation of the instantaneous power Ps of the series converter for the internal power balance.

Everything stated so far corresponds to the file used for the UPQC experimental case. For the experimental case with the shunt APF included in Chapter 4, a simplified version of this file has been used, eliminating the unnecessary components. The block “Medidas” does not include the measurements of the supply side voltages V_S and currents I_S in the multiplexed ADC converters, nor the validation bit ics_ok; making faster the acquisition stage of the control program. The block “Trigger signals” does not use the PWM3 generator nor the validation bit of the slave processor. Finally, in the block “Control”, the blocks “Comp_FS”, “Refs_FS,” and “GEv” are removed. And the load currents iL are directly included in the power balance, without the previous filtering. These simplifications give a reduced real time control program for the DSP board, that allows to set a sampling period of 50 μs for the shunt APF experimental case.