Preface

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You’ll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in optimal time and with an optimal cost. This book adopts a practical approach to help you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using acceleration techniques, and finally, build an RTOS-based software application for an advanced SoC design.

Beginning with an introduction to the FPGA SoC technology fundamentals and their associated development design tools, this book will guide you in building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and it covers advanced applications such as communications, security, and coherent hardware acceleration.

By the end of this book, you’ll have learned the concepts underlying FPGA SoC advanced features and you’ll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.

Who this book is for

This book is intended for FPGA and ASIC hardware and firmware developers, IoT engineers, SoC architects, and anyone interested in understanding the process of developing a complex SoC, including all aspects of the hardware design and the associated firmware design. Prior knowledge of digital electronics and some experience in coding in Very High-Speed Design Language (VHDL) or Verilog and C, or a similar language suitable for embedded systems, will be required for using this book. A general understanding of FPGA and CPU architecture will be helpful but not mandatory for using this book.

What this book covers

Chapter 1, Introducing FPGA Devices and SoCs, begins by describing the FPGA technology and its evolution since it was first invented by Xilinx in the 1980s. It goes over the electronics industry gap that the FPGA devices cover, their adoption, and their ease of use to implement custom digital hardware functions and systems. It then describes the high-speed SoCs and their evolution since they were introduced as a solution by the major FPGA vendors in the early 2000s. It looks at SoC classification for the targeted applications, specifically for FPGA implementations.

Chapter 2, FPGA Devices and SoC Design Tools, begins by giving an overview of the Xilinx FPGA hardware design flow in general and the tools associated with it. It then highlights the specific tools used when designing an SoC for FPGAs. It also introduces SoC design hardware verification using the available simulation tools. The chapter also covers the software design flow and its different steps and introduces the tools involved in every step of the software design for an FPGA-based SoC.

Chapter 3, Basic and Advanced On-Chip Busses and Interconnects, begins by giving an overview of the busses and interconnects used within an SoC. It introduces the concepts of data sharing and coherency and how to solve their associated challenges. It gives a good introduction to the AMBA and OCP protocols. It also covers data movement within an SoC and the use of DMA engines.

Chapter 4, Connecting High-Speed Devices Using Busses and Interconnects, begins by giving an overview of the busses and interconnects used off-chip to connect an SoC and/or an FPGA to other high-speed devices on the electronics board. It introduces the PCIe interconnect, the Ethernet interconnect, and the emerging Gen-Z protocol. It also introduces the emerging CCIX interconnect protocol and the concept of extending data coherency off-chip by adding protocol layers to manage it.

Chapter 5, Basic and Advanced SoC Interfaces, begins by defining an SoC interface for a given function. It classifies the SoC interfaces and lists their associated controller services. Then, the chapter covers processor caches and their organizations with a focus on ARMv7 architecture. It also introduces the processor memory management unit and its role in virtual-to-physical address translation and in implementing address space management and protection. It delves into the different memory and storage interfaces for on-chip and off-chip memories, their topologies and architectural features, and the criteria for choosing a given interface (or a combination of many).

Chapter 6, What Goes Where in a High-Speed SoC Design, teaches you about the SoC architecture definition phase that precedes the design and implementation phases. This phase is very useful to system architects as it translates a certain set of product requirements into a high-level description of the SoC design to accomplish. It details the criteria used during the functional decomposition stage in which a trade-off is reached between what is better suited to be implemented in hardware and what is rather a good target for a software implementation. It gives an overview of SoC system modeling using many available tools and environments.

Chapter 7, FPGA SoC Hardware Design and Verification Flow, delves into building the SoC hardware using all the tools introduced in the previous chapters. This chapter is hands-on, where you will build a simple but complete SoC for a Xilinx FPGA. You are guided through every step of the SoC hardware design phases, from the concept to the FPGA image generation. The chapter will also cover the hardware verification aspects, such as using the available Register Transfer Level (RTL) simulation tools to simulate part of the design and check for potential hardware issues.

Chapter 8, FPGA SoC Software Design Flow, focuses on the steps involved in building the software that will run on the SoC processors. You will first configure the software components needed by this phase of the design process, such as customizing the Board Support Package (BSP), configuring the libraries, and customizing the drivers for a simple application. You will revisit the SoC project built in the previous chapter to learn how to define a distributed software microarchitecture and will go through the steps of building all the project software components using bare-metal software applications targeting the SoC hardware.

Chapter 9, SoC Design Hardware and Software Integration, helps you to download an FPGA binary configuration file to the device and boot the SoC CPU's phase or target an emulation platform if a demo board isn’t available. You will debug the software running on the target platform (real hardware or virtual models) and gain practical familiarity with the available software debugging tools. You will also learn how to evaluate the software performance and understand its associated metrics using the software profiling tools in order to highlight any areas of concern in the designed system.

Chapter 10, Building a Complex SoC Hardware Targeting an FPGA, introduces you to some of the SoC design advanced topics that present many challenges to design engineers given their multidimensional nature. It will continue with the same practical approach as previous chapters by first adding more complex elements to the hardware design. It will now be built to host an embedded operating system as well. You will be introduced to the hardware acceleration techniques to help augment the system performance and equipped with the fundamental knowledge to make this step challenge-free. You will examine the different ways they can be applied and what system aspects need to be considered at the architectural level in the shared data paradigm.

Chapter 11, Addressing the Security Aspects of an FPGA-Based SoC, introduces you to the SoC security aspects and how these aspects are addressed by the FPGA SoC hardware. You will then learn about the security paradigms available in the ARM-based processors within the SoC hardware. The chapter will then introduce the security aspects from a software perspective and how they make use of the previously mentioned hardware security features to build a secure SoC in an FPGA.

Chapter 12, Building a Complex Software with an Embedded Operating System Flow, teaches you about the flow and helps you discover the tools used to build a complex software application to run on the complex FPGA SoC. You will use the design tools available to create the SoC BSP for the targeted embedded operating system, such as FreeRTOS. You will go through the process of generating an embedded bootloader for the target application to be used at runtime when the SoC is powered up or reset.

Chapter 13, Video, Image, and DSP Processing Principles in an FPGA and SoCs, introduces some of the advanced applications implemented in modern FPGAs and SoCs and what makes these devices such powerful compute engines for these types of compute- and bandwidth-demanding applications. It will clarify how parallel processing required by DSP applications in general can be easily implemented in the FPGA logic and how these parallel compute engines can be interfaced internally and externally to wide memories and internally to the powerful CPUs available in the SoCs.

Chapter 14, Communication and Control System Implementation in FPGAs and SoCs, continues introducing more advanced applications implemented in modern FPGAs and SoCs and explains what makes these devices such powerful compute engines for these types of I/O- and bandwidth-demanding applications. It will focus on some of the communication protocols that can make use of the FPGA multi-Gb transceivers, the logic that can perform packet inspections and filtering, and the CPU that can implement algorithms in the SW to manage the communication stack and interface to the user and other onboard devices. It will also cover control applications in the FPGA and SoCs and how they can benefit from all of their available features.

To get the most out of this book

You need to have familiarity with digital electronics in general and, specifically, you need to have some fundamental knowledge of modern logic design at a RTL using a hardware design language such as VHDL, Verilog, or SystemVerilog. You will also need some working knowledge of embedded programming using a high-level language such as C or C++ and have some experience using cross-compilers to build executables for a target embedded processor. The hardware design flow and the embedded software design flow both use tools packaged within the Xilinx Vivado and Vitis environments. You will be guided through their installation processes on your host machine. If you are running a Windows operating system on your host machine, you will be guided through installing VirtualBox, which is an Oracle hypervisor to host a Linux guest operating system to be used as your development host operating system.

Software/hardware covered in the book	Operating system requirements
Xilinx Vivado 2021.2 or a higher version	Windows Enterprise and Professional 10.0 Or Window 10 HE and VirtualBox Or Ubuntu 16.04.5 LTS up to 20.04.1 LTS
Xilinx Vitis	Windows Enterprise and Professional 10.0 Or Window 10 HE and VirtualBox Or Ubuntu 16.04.5 LTS up to 20.04.1 LTS
VirtualBox	Windows 10

All the required installation steps are described in detail in the book using a simple, logical step-by-step approach that will get you up and running with the tools. Simply follow the instructions and don’t skip any steps during the installation process. Also, make sure you perform the required configuration when indicated to do so, so the tools are ready to use without wasting time debugging issues that are sometimes hard to track if a step in the installation or configuration process has been skipped or omitted.

If you are using the digital version of this book, we advise you to type the code yourself or access the code from the book’s GitHub repository (a link is available in the next section). Doing so will help you avoid any potential errors related to the copying and pasting of code.

If you can get hold of a Xilinx Zynq-7000 SoC board, this will be great as you can download the FPGA bitstream and the executable software to the board and perform debugging and profiling on the real hardware. Nevertheless, if you don’t have access to a Xilinx Zynq-7000 SoC board, you can still use a virtual target within the Xilinx tools to debug and interact with the executable software running on the virtual target.

Download the example code files

You can download the example code files for this book from GitHub at https://github.com/PacktPublishing/Architecting-and-Building-High-Speed-SoCs. If there’s an update to the code, it will be updated in the GitHub repository.

We also have other code bundles from our rich catalog of books and videos available at https://github.com/PacktPublishing/. Check them out!

Code in Action

The Code in Action videos for this book can be viewed at http://bit.ly/3NNFkZs.

Download the color images

We also provide a PDF file that has color images of the screenshots and diagrams used in this book. You can download it here: https://packt.link/Hjk2H.

Conventions used

There are a number of text conventions used throughout this book.

Code in text: Indicates code words in text, database table names, folder names, filenames, file extensions, pathnames, dummy URLs, user input, and Twitter handles. Here is an example: “In PM, Vivado Design Suite uses a project file (.xpr) and directory structure to maintain the design source files.”

Bold: Indicates a new term, an important word, or words that you see onscreen. For instance, words in menus or dialog boxes appear in bold. Here is an example: “You first need to launch the Vivado IDE, then on the Vivado launch screen, choose Quick Start, then Create Project.”

Tips or important notes

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