DC loads include linear actuators such as those used on positioning tables, motors, programmable power supplies, outdoor displays, and lighting systems. Large load currents or high voltages characterize some of these loads. DC accuracy is important, because it is related to a series of desired mechanical positions or intensities in the load device.

AC loads include things like audio chains, frequency generators, IF outputs—any load that does not have a DC component.

DACs are available in several types, the most common of which is the resistor ladder type. There are several variations on the resistor ladder technique, with the R/2R configuration being the most common.

In the resistor ladder DAC, a precision voltage reference is divided into 2^N−1 parts in an internal voltage divider, where N is the number of bits specified for the converter. One switch at a time turns on, corresponding to the correct DC level (Figure 18.1).

Unfortunately, the number of resistors and switches doubles for each additional bit of resolution. This means that an 8 bit DAC has 255 resistors and 256 switches, and a 16 bit DAC has 65,535 resistors and 65,536 switches. For this reason, this architecture is almost never used for higher resolution DACs.

The weighted resistor DAC is very similar to the resistor ladder DAC. In this case, however, each resistor in the string is given a value proportional to the binary value of the bit it represents. Currents are then summed from each active bit to achieve the output (Figure 18.2).

The number of resistors and switches are reduced to one per bit, but the range of the resistors is extremely wide for high resolution converters, making it hard to fabricate all of them on the IC. The resistor used for B0 in Figure 18.2 is the limiting factor for power dissipation from V_REF to ground.

This converter architecture is often used to make logarithmic converters. In this case, the R, 2R, 4R, 8R, … resistors are replaced with logarithmically weighted resistors.

This type of converter and the R/2R converter described in the next subsection use a feedback resistor fabricated on the DAC IC itself. This feedback resistor is not an optional convenience for the designer—it is crucial to the accuracy of the DAC. It is fabricated on the same silicon as the resistor ladder. Therefore, it experiences the same thermal drift as the resistor ladder. The gain of the buffer amplifier is fixed, with a full scale output voltage limited to V_REF. If a different full scale DAC output voltage is needed, change V_REF. If the full scale V_OUT must exceed the maximum rating of the DAC reference voltage, use a gain stage after the buffer op amp (see Section 18.7.2).

The op amp must be selected carefully, because it is operated in much less than unity gain mode for some combinations of bits. This is probably one of the main reasons why this architecture is not popular, as well as the requirement for a wide range of resistor values for high precision converters.

An R/2R network can be used to make a DAC that has none of the disadvantages of the types mentioned previously (Figure 18.3).

For a given reference voltage, V_REF, a current I flows through resistor R. If two resistors, each the same value (2R) are connected from V_REF to ground, a current I/2 flows through each leg of the circuit. But the same current flows if one leg is made up of two resistors, each with the value of R. If two resistors in parallel whose value is 2R replace the bottom resistor, the parallel combination is still R. I/4 flows through both legs, adding to I/2. Extending the network for 4 bits as shown on the right, the total current on the bottom leg is I/4 plus I/8 plus I/16 plus I/16 in the resistor to ground. Kirchhoff's current law is satisfied and convenient tap points have been established to construct a DAC (Figure 18.4).

This converter architecture has advantages over the types previously mentioned. The number of resistors has doubled from the number required for the current summing type, but there are only two values. Usually, the 2R resistors are composed of two resistors in series, each with a value of R. The feedback resistor for the buffer amplifier is again fabricated on the converter itself for maximum accuracy. Although the op amp is still not operated in unity gain mode for all combinations of bits, it is much closer to unity gain with this architecture.

The important op amp parameters for all resistor ladder DACs are

The sigma delta DAC takes advantage of the speed of advanced IC processes to do a conversion as a series of approximations summed together. A phase locked loop (PLL) derived sample clock operates at many times the overall conversion frequency; in the case shown in Figure 18.5, it is 128×. The PLL is used to drive an interpolation filter, a digital modulator, and a 1 bit DAC. The conversion is done by using the density ratio of the voltage out of the 1 bit DAC as the analog signal. As the pattern of ones and zeros is presented to the 1 bit converter, their time average at the sample frequency recreates the analog waveform.

Sigma delta converters are popular for audio frequencies, particularly CD players. The primary limiting factor is the sample clock. CD players operate at a sample rate of 44.1 kHz, which means that, according to Nyquist sampling theory, the maximum audio frequency that can be reproduced is 22.05 kHz. If an audio frequency of 23.05 kHz is present in the recorded material, it will alias back into the audio output at 1 kHz, producing an annoying whistle. This places a tremendous constraint on the low pass filter following the DAC in a CD player. It must reject all audio frequencies above 22.05 kHz while passing those up to 20 kHz, the commonly accepted upper limit of human hearing. While this can be done in conventional filter topologies, they are extremely complex (nine or more poles). Inevitably, phase shift and amplitude roll-off or ripple starts far below 20 kHz. The original CD players often sounded a bit “harsh” or “dull” because of this.

The solution was to overclock the sample clock. To keep things simple, designers made it a binary multiple of the original sampling frequency. Today, eight times or even higher oversampling is standard in CD players. Little do the audio enthusiasts know that the primary reason why this was done was to substantially reduce the cost of the CD player. A faster sample clock is very cheap. Nine pole audio filters are not. At eight times oversampling, the CD player needs to achieve maximum roll-off at only 352.8 kHz, a very easy requirement. Instead of the filter having to roll off in a mere 2 kHz of bandwidth, now it has 332 kHz of bandwidth to accomplish the roll-off. The sound of an oversampled CD player really is better, but it comes at the cost of increased radiated RFI, coming from the sample clock.

Sigma delta converters introduce a great deal of noise onto the power rails, because the internal digital circuitry is continually switching to the power supply rails at the sample clock frequency f_S.

It is important for the designer to understand the difference between converter accuracy and converter resolution. The number of bits determines resolution of a converter. Insufficient resolution is not an error—it is a design characteristic of the DAC. If a given converter's resolution is insufficient, use a converter with better resolution (more bits).

Accuracy is the error in the analog output from the theoretical value for a given digital input. Errors are described in the next section. A very common method of compensating for DAC error is to use a converter that has 1 or 2 bits more resolution than the application requires. With the cost of converters coming down and more advanced models being introduced every day, this may be cost effective.

DC applications depend on the value of DC voltage coming out of the converter. THD and signal to noise ratio are not important, because the frequency coming out of the converter is almost DC.

The resolution of a converter is ±½ LSB, where an LSB is defined aswhere

The number of bits in a DC system determines the DC step size that corresponds to a bit. Table 18.1 shows the number of bits and the corresponding voltage step size for three popular voltages.

The bit step size can get critical, especially for portable equipment. There is a requirement to operate off of low voltage to minimize the number of batteries. The buffer amplifier, if it includes gain, uses large resistor values, lowering its noise immunity. Fortunately, the vast majority of DC applications are not portable; they are in an industrial environment.

For example, a converter is used to position a drill on a table used to drill PCB holes. The positions of the holes are specified as 0.001 in., ±0.0003 in. The actuators are centered on the table at 0 V, with full negative position of −12 in. occurring at −5 V, and full positive position of +12 in. occurring at +5 V. There are two actuators, one for vertical, and one for horizontal.

This example has several aspects. The first is that the positioning voltage has to swing both positive and negative. In the real world, it may be necessary to add (or subtract in this case) a fixed offset to the DAC output. The output voltage has to swing over a 10 V range, which may mean that the output of the DAC has to be amplified. The actuators themselves probably operate off of higher current than the DAC is designed to provide. Section 18.7 covers some methods for meeting these requirements.

Assume, for now, that the DAC has the necessary offset and gain. A ±12 in. position is 24 in. total, which corresponds to ±5 V from the DAC circuitry. The 24 in. range must be divided into equal 0.0003 in. steps to meet the resolution requirement, which is 80,000 steps. From Table 18.1, an 18 bit DAC is required. The actual system is able to position with a step size of 0.0000916 in. Two independent conversion systems are needed, one for horizontal and one for vertical.

The error budget for an AC application most likely is specified as total harmonic distortion, dynamic range, or signal to noise ratio. Assuming no internal noise and no noise in the buffer op amp circuitry, the inverse of the dynamic range is the SNR of the DAC. Of course, noise is always present and is measured with all input data set to zero. Noise makes the SNR decrease.

The number of converter bits, however, is the overwhelming factor determining these parameters. Technically, they are not “errors,” because the design of the converter sets them. If the designer cannot live with these design limits, the only choice is to specify a converter with better resolution (more bits).

RF applications are a high frequency subset of AC applications. RF applications may be concerned with the position and relative amplitude of various harmonics. Minimizing one harmonic at the expense of another may be acceptable if the overall RF spectrum is within specified limits.

The following are some DAC DC errors and parameters.

The following are DAC AC errors and parameters.

Current boosters usually use some variation of the class-B push/pull amplifier topology (Figure 18.16).

The circuit in Figure 18.16 has been employed for decades—many resources are available to design exact component values. It boosts current because the output impedance of the op amp has been bypassed and used as the driver for the base of the npn and pnp power transistors. The two diodes compensate for the VBE drop in the transistors, whose bases are biased by two resistors off of the supplies. The output of the booster stage is fed back to the feedback resistor in the DAC to complete the feedback loop. The output impedance of the stage is limited by only the characteristics of the output transistors and small emitter resistors. Modern power transistors have such high frequency response that this circuit may oscillate. The RC snubber network and a small inductor in series with the load can be used to damp the oscillation—or be omitted if oscillation is not a problem. Beware of varying transistor betas, however.

If even more current is needed or the output voltage swing must be more than ±15 V, the booster stage can be operated at voltages higher than the buffer amplifier potentials. A designer might be tempted to try the circuit of Figure 18.17.

Any time there are higher voltage rails on the output section, there are potential hazards. This circuit illustrates a common misapplication:

The problem with this is that the wattage of the resistors increases as the external voltage rail increases. The designer has control over the wattage of the external R_F but no control whatsoever over internal R_F or R_S. Because these resistors are fabricated on the IC, their wattage is limited. Even if the wattage rating of the internal resistors is meticulously observed, they may have undesirable thermal coefficients if allowed to dissipate that wattage. Resistor self-heating changes the resistance according to its rated temperature coefficient (maximum). The external resistor is sure to have a different thermal coefficient from the internal resistors, causing a gain error. The designer may never have encountered the effects of resistor self-heating before, because through hole and surface mount devices have enough bulk to minimize the effect of self-heating. At the geometries present on IC DACs, resistor self-heating is a much more pronounced effect. It produces a nonlinearity error in the DAC output.

This effect is most pronounced in high resolution converters, where the geometry is the smallest. The designer, therefore, must limit the current in the feedback resistor if at all possible. Figure 18.18 shows a method of achieving gain control while keeping the high current path out of the internal feedback resistor.

In Figure 18.18,

If the combination of voltage swing and power ratings cannot be balanced to achieve a working design, the only choice left to the designer is to break the feedback loop and live with the loss of accuracy. For AC applications, this may be acceptable.

The preceding two types of boosters can, of course, be combined to produce more power. In audio applications, for example, a ±15 V power supply limits the output power to 112.5 W, absolute maximum, into an 8 Ω load. To increase the power, the voltage rails must also be increased, with all of the cautions of the previous subsection observed.

A DAC power circuit is not the right place to try to apply single supply design techniques. In audio applications, a single supply design forces a large coupling capacitor, which distorts and limits low frequency response. In DC applications, a DC offset continually drives the load, which has to dissipate the excess voltage through its internal resistance as heat.

Nevertheless, some applications may require a DC offset. The designer is fortunate in that a precision reference is already available in the circuit. The reference drives the resistor network in the DAC and may be external or internal to it. In most cases, an internal reference is brought out to a pin on the device. It is important for the designer not to load the reference excessively, as that directly affects DAC accuracy (Figure 18.19).

In the circuit in Figure 18.19, the output of the buffer amplifier is shifted up in DC level by 1/2 V_REF (not 1/2 V_CC). V_REF is selected because it is much more stable and accurate than V_CC. The four resistors in the level shifter circuit must be highly accurate and matched, or this circuit will contribute to gain and offset errors. Thermal errors, however, cannot be compensated for, because the external resistors are probably going to have a different thermal drift than those on the IC. This technique is limited to applications that will see only a small change in ambient temperature.