8.1. Power Factor Correction Defined

$\text{PF}=\frac{1}{\sqrt{1+{\left(\frac{\text{THD}}{100}\right)}^2}}$

8.2. Typical PFC Boost Circuit

8.3. Boost–Buck Single Switch Circuit

8.4. Boost–Linear Regulator Circuit

8.5. Bi-Bred

The duty cycle of the switching is given by $\frac{V_{\text{o}}}{V_{\text{i}}}=\frac{D}{1-D}$.

Or put another way, $D=\frac{V_{\text{o}}}{V_{\text{i}}+V_{\text{o}}}$. So if V_in = 350 V and V_o = 3.5 V (a typical white LED), $D=\frac{3.5}{350+3.5}=\frac{3.5}{353.5}=0.99\%$. Such a small duty cycle can be difficult to switch properly, as we have seen for a buck converter. This means that a Bi-Bred is not really suitable for driving short LED strings.

8.6. Buck–Boost–Buck

The duty cycle of the switching in a BBB converter is given by $\frac{V_{\text{o}}}{V_{\text{i}}}=\frac{D^2}{1-D}$.

Or put another way, $D=\frac{-V_{\text{o}}\pm \sqrt{V_{\text{o}}^2+4\cdot V_{\text{i}}\cdot V_{\text{o}}}}{2\cdot V_{\text{i}}}$. So if V_in = 350 V and V_o = 3.5 V (a typical white LED), $D=\frac{-3.5\pm 70}{700}=\frac{66.5}{700}=9.5\%$. This is a considerably greater duty cycle than either the Bi-Bred or the buck converter with a similar low-voltage load. This means that the BBB converter is most suitable for driving short LED strings.

8.6.1. Buck–Boost–Buck Design Equations

The HV9931 is a peak current control IC that is designed for controlling the nonisolated single-stage PFC converter (BBB) described earlier. A typical application circuit of the HV9931 was shown in Fig. 8.5, but is redrawn with different component annotation to help with the further description, in Fig. 8.7.

The HV9931 has a built-in high-voltage regulator circuit producing 7.5 V ± 5% at V_DD, hence making the circuit relatively simple because we do not have to consider separately powering the integrated circuit.

As soon the start-up threshold is reached at V_DD, an internal oscillator circuit is enabled. The oscillator circuit is actually three functions: a timer, a latch, and a latch-reset circuit. The timer is a current mirror that charges an internal capacitor; when the threshold of 0.63 V_DD is reached (after R_T × C seconds, where C is the internal capacitor) the latch is triggered. At this time, the timer capacitor is discharged ready for the next cycle. The output signal of the latch turns on the GATE output and switches on the power MOSFET Q1. The oscillator circuit also includes two comparators; if either of these is triggered, the latch is reset and the MOSFET Q1 turns off.

The timer uses a current mirror, with one-half connected to the R_T pin. The current mirror needs a small current to flow to ground (0 V) from the R_T pin, which causes the other half of the mirror to charge an internal timing capacitor. This means that the timer can be programmed with a single resistor connected to R_T for either constant switching frequency or fixed off-time operation.

In the constant frequency mode, a constant timing current is required, so the timing resistor must be connected between the R_T pin and 0 V. In the fixed off-time mode, the timing resistor must be connected between the GATE and R_T pins; current flow (and hence timing) only begins when the GATE pin is at 0 V. Thus the timer will set the latch and turn on the MOSFET after a programmed time period following the turn-off of the GATE output.

The fixed off-time operating mode is preferred because it: (1) reduces the voltage stress at C1, (2) improves input AC ripple rejection, and (3) inherently introduces frequency jitter that can help reduce the size of the input EMI filter required. Hence we will use the fixed off-time mode for the following design.

Connecting the resistor from R_T to GATE programs constant off-time:

$T_{\text{off}}=\alpha \cdot R_{\text{T}}+{\tau }_0$

Where α = 40 pF, τ₀ = 880 ns.

In terms of R_T, this transposes to:

$R_{\text{T}}=\frac{T_{\text{off}}-{\tau }_0}{\alpha }=\frac{T_{\text{off}}-880\text{ns}}{40\cdot {10}^{-12}}$

The input and output feedback comparators are used as current sense inputs, for programming peak currents in L1 and L2. Both comparators use the ground potential (GND) as a reference and can be used to monitor voltage signals of negative polarity with respect to GND. A blanking delay of 215 ns is added to prevent false tripping the comparators due to the circuit parasitic capacitance. The currents i_L1 and i_L2 that trip the comparators can be computed as:

$i_{\text{Lpk}}=\frac{V_{\text{ref}}\cdot R_{\text{cs}}}{R_{\text{ref}}\cdot R_{\text{s}}}$

Where V_ref in this equation is an external reference voltage.

We will use V_ref = V_DD as an example. When either of the feedback comparators detects negative input voltage at its current sense (cs) input, the latch resets, the GATE output becomes low voltage.

We can easily calculate the current in L2, as the output current is more or less constant with some ripple. It is assumed to operate in CCM,

$i_{L2\text{pk}}=i_{L2}+0.5\cdot ∆i_{L2}$

Where i_L2 is the average current and ∆i_L2 is the peak-to-peak current ripple in L2. Thus the constant peak current control used in the HV9931 introduces a peak-to-average error 0.5 × ∆i_L2 that needs to be accounted for when programming the resistor divider R_ref2/R_cs2. Fortunately, this error is nearly constant for any input voltage at fixed T_off and it is relatively small compared to i_L2 (15% typical). The ripple will have a minimal effect on the overall regulation of the output current. The error is however a function of the output voltage variation and the inductance value tolerances of L2.

8.6.1.1. Choice of L1

We need to design the input buck–boost stage to operate in DCM to give a good PF. Operating in DCM at any given line and load condition will ensure low distortion of the input current and stability of the control loop. Therefore, let us assume that the current in L1 becomes critically continuous at full load and at some minimum operating AC line voltage V_AC min. This boundary conduction mode (BCM) condition should normally occur at the peak of each half-wave of the input AC current. If we assume a unity PF (PF = 1), this boundary condition will then coincide with the peak input voltage V_AC min. As both converter stages are in CCM at this point, the ratio between the output and the input voltage can be expressed as:

$\frac{V_{\text{o}}}{V_{\text{AC}\text{min}}\cdot \sqrt{2}}=\frac{D_{\max }\cdot {\eta }_1}{1-D_{\max }}\cdot D_{\max }\cdot {\eta }_2=\frac{D_{\max }^2\cdot \eta }{1-D_{\max }}$

Where η₁ and η₂ are the corresponding efficiencies of the input buck–boost stage and the output buck stage. The overall converter efficiency equals η = η₁ × η₂. The duty ratio D of the switch M1 is the greatest at this condition. (Duty ratio is defined as D = T_on/T_s, where T_on is the on-time of M1, and T_s is the switching period.)

The input AC line current is a ratio of the output power to the input voltage and efficiency:

$i_{\text{AC}}=\frac{V_{\text{o}}\cdot i_{\text{o}}}{V_{\text{AC}}\cdot \eta }$

On the other hand, the peak input current must be equal to the (averaged) peak current through L1:

$i_{\text{AC}}\cdot \sqrt{2}=\frac{D}{2}\cdot i_{L1\text{pk}}$

Where the peak current in L1 (i_L1pk) is dependent on the maximum voltage across L1, the inductance and the on-time:

$i_{L1\text{pk}}=\frac{V_{\text{AC}}\cdot \sqrt{2}\cdot T_{\text{on}}}{L1}$

As we are only considering the constant off-time case, let us express this in terms of T_off = T_on × (1–D)/D.

$i_{L1\text{pk}}=\frac{V_{\text{AC}}\cdot \sqrt{2}\cdot T_{\text{off}}}{L1}\cdot \frac{D}{1-D}$

Combining the equations (using the mean value of V_AC min) and solving for the inductance value gives:

$L1=\frac{V_{\text{AC}\text{min}}\cdot \sqrt{2}\cdot T_{\text{off}}}{4\cdot i_{\text{o}}}$

Note, that the critical inductance L1 in this equation corresponds to the boundary conduction at V_AC min. The value used in practice should be lower than this, to allow for component tolerances and parasitic elements. The inductor value has some tolerance, perhaps 10%, but tolerance in all the other components and switching off-time should be considered too. If the inductance goes above the critical value, CCM will occur and the input waveform will be severely distorted. For these reasons, the value of L1 should be reduced to 63% of its maximum allowed value:

$L1=\frac{0.63\cdot V_{\text{AC}\text{min}}\cdot \sqrt{2}\cdot T_{\text{off}}}{4\cdot i_{\text{o}}}$

The designer must be careful when considering standard inductors for L1 or designing a custom one. As L1 conducts discontinuous current, magnetic flux excursion in the core material can cause heating. Hence the design of L1 is limited by the power dissipation in the magnetic core material rather than by the saturation current of the inductor selected.

8.6.1.2. Choosing C1

Capacitor C1 is usually an electrolytic capacitor because of the required high-capacitance value and high-voltage rating. This is sometimes a cause for concern about reliability. However, the lifetime rating of electrolytic capacitors has improved in recent years and lifetime ratings of 10,000 h at 105°C are available from multiple sources. Considering that the lifetime doubles for every 10°C drop in temperature, this equates to 40,000 h at 85°C. So at reasonable temperatures, the lifetime of the electrolytic and the LED are comparable.

Capacitor C1 is the main energy storage element and its capacitance value significantly affects the distortion of input current. The minimum capacitance value of C1 is determined by the input harmonics limits required for a specific application. Lighting products are sold in large quantities, and thus these high-volume products can potentially have a high impact on the low-voltage public supply system. The European EN 61000-3-2 class C limits are applicable to lighting products and are comparable to the limits imposed by ANSI C82.77 standards in the US market. These restrict THD to approximately 33%. Both, the class C and ANSI standards limit the third harmonic current of lighting products to ∼30%. The regulations for LED-based traffic signal heads are generally stricter and require THD to be less than 20% (ITE VTCSH Part 2).

The main component of the AC ripple voltage across C1 is the second AC line harmonic. This ripple causes modulation of the duty cycle, D(t), given by the following equation:

$D(t)=\frac{V_{\text{o}}}{{\eta }_2\cdot V_{\text{C}}(t)}$

Where V_C(t) is voltage across C1 at any time t.

Combining the equations developed in Section 8.6.1.1, we have an equation for the input AC current:

$i_{\text{AC}}=\frac{D}{2\sqrt{2}}\cdot \frac{V_{\text{AC}}\cdot \sqrt{2}\cdot T_{\text{off}}}{L1}\cdot \frac{D}{1-D}$

In terms of a sinusoidal waveform, this becomes:

$i_{\text{AC}}(t)=\frac{V_{\text{AC}}\cdot \sqrt{2}\cdot T_{\text{off}}}{2\cdot L1}\cdot \frac{D^2(t)}{1-D(t)}\cdot \sin (2\pi \cdot f_{\text{AC}}\cdot t)$

Where f_AC is the AC line frequency (50 or 60 Hz).

Assume that a small second harmonic ripple voltage V_C exists across C1, i.e. 100 or 120 Hz, so that the voltage at C1 can be written as:

$V_{\text{C}}(t)=V_{\text{C}}-{\nu }_{\text{C}}\cdot \sin (4\pi \cdot f_{\text{AC}}\cdot t)$

Where i_C/V_C << 1. By substituting across these last three equations we will produce a displaced fundamental term and a third harmonic term in the AC line current. It can be shown from the resulting equation that the third harmonic distortion of the input AC line current for a given relative second harmonic ripple K_C = i_C/V_C << 1 is:

$K_3=\frac{∆i_3}{i_{\text{AC}}}\approx 0.5\cdot K_{\text{C}}\cdot \frac{2-D}{1-D}$

Thus every 1% of second harmonic ripple at C1 will generate at least 1% of third harmonic component in the AC line current even when the duty cycle is small.

Now we can find the capacitance value of C1 needed to limit the third harmonic distortion to some given constant K₃. Equations used to find L1 can now be used to solve for the duty cycle D at any V_AC within the operating range.

$D=\frac{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}{V_{\text{AC}}^2\cdot T_{\text{off}}\cdot \eta }\cdot \left(\sqrt{1+\frac{2\cdot V_{\text{AC}}^2\cdot T_{\text{off}}\cdot \eta }{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}}-1\right)$

This is a bit unwieldy, so let us introduce a parameter δ as follows:

$\delta =\frac{2\cdot V_{\text{AC}}^2\cdot T_{\text{off}}\cdot \eta }{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}$

Now the equation for the duty cycle looks much simpler:

$D=\frac{2\cdot \left(\sqrt{1+\delta }-1\right)}{\delta }$

We can rewrite the equation for the third harmonic ripple K₃ as:

$K_3=K_{\text{C}}\cdot \frac{1}{1-\frac{1}{\sqrt{1+\delta }}}$

Recalling that D = V_o/(η₂ × V_C) and using D = 2 (√(1+δ)−1)/δ from above, we can determine the voltage at C1 for a given V_AC:

$V_{\text{C}}=\frac{V_{\text{o}}}{2\cdot {\eta }_2}\cdot \left(1+\sqrt{1+\delta }\right)$

We have assumed that K_C = i_C/V_C << 1. This condition is met if the value of capacitor C1 large enough, so that the AC ripple voltage across C1 is low. Therefore, C1 decouples the bulk of the AC ripple current at the output of the input converter stage. Averaged over a switching cycle, this current can be written as:

$i_2(t)=\frac{V_{\text{AC}}(t)\cdot i_{\text{AC}}(t)\cdot {\eta }_1}{V_{\text{C}}}$

The AC line current i_AC(t) has been given by a previous equation. Based on the assumptions made earlier, the AC component of i₂(t) contains second harmonic current only. This AC current in C1 can be expressed as:

$i_{\text{C}}(t)=-\frac{V_{\text{AC}}^2\cdot {\eta }_1\cdot T_{\text{off}}}{2\cdot L1\cdot V_{\text{C}}}\cdot \frac{D^2}{1-D}\cdot \cos (4\pi \cdot f_{\text{AC}}\cdot t)$

Substituting D and V_C (using δ from the condensed equations earlier) gives:

$i_{\text{C}}(t)=-\frac{2\cdot i_{\text{o}}}{1+\sqrt{1+\delta }}\cdot \cos (4\pi \cdot f_{\text{AC}}\cdot t)$

Relative ripple voltage at C1 can be calculated as K_C = i_Cpk × Z_C/V_C, where i_Cpk is the amplitude of i_C(t) and Z_C = 1 /(4π × f_AC × C1) is the impedance of C1 at 2 × f_AC. Substituting V_C we obtain:

$K_{\text{C}}=\frac{1}{{\left(1+\sqrt{1+\delta }\right)}^2}\cdot \frac{{\eta }_2\cdot i_{\text{o}}}{\pi \cdot f_{\text{AC}}\cdot C1\cdot V_{\text{o}}}$

Solving this equation for C1 and substituting for K_C we get:

$C1=\frac{1}{\delta \cdot \left(1+\frac{1}{\sqrt{1+\delta }}\right)}\cdot \frac{{\eta }_2\cdot i_{\text{o}}}{\pi \cdot f_{\text{AC}}\cdot K_3\cdot V_{\text{o}}}$

The RMS value of the switching current in C1 can be calculated using the following equation:

$i_{\text{C}\text{SW}}=i_{\text{o}}\cdot \sqrt{\frac{64}{9\cdot \pi \cdot \eta \cdot {\eta }_1}\cdot \frac{V_{\text{o}}}{V_{\text{AC}}\cdot \sqrt{2}}+D}$

The RMS value of the second AC line harmonic is:

$i_{\text{C}\text{line}}=\frac{\sqrt{2}\cdot i_{\text{o}}}{1+\sqrt{1+\delta }}$

8.6.1.3. Calculating L2

Calculating the value of the output filter inductor L2 is simple. The designer must decide on the allowable amount of switching ripple current in L2. Then:

$L2=\frac{V_{\text{o}}\cdot T_{\text{off}}}{∆i_{L2}\cdot {\eta }_2}$

Where ∆i_L2 is the peak-to-peak current ripple in L2. Larger values of L2 will produce smaller ripple ∆i_L2, and therefore smaller peak-to-average error in the output current control loop. However, low-amplitude feedback signals would also make the output current sense comparator more susceptible to noise. It is a good practice to design L2 for ∆i_L2 = 20–30%. The reason for having moderate inductor current ripple is to allow a sufficiently high-feedback signal for the current sense comparator. An output capacitor connected across the LED load can be added, to reduce the output ripple current further, if needed.

Unlike the design of input inductor L1, the design of L2 is typically limited by the saturation flux of its magnetic material. However, power dissipation due to the core loss may also need to be considered. The saturation current rating of the inductor must satisfy:

$i_{\text{sat}}>i_{\text{o}}+0.5\cdot ∆i_{L2}$

8.6.1.4. Power semiconductor components

Now we can calculate the voltage and the current ratings of the MOSFET M1 and the rectifiers D1–D4.

8.6.1.4.1. MOSFET M1

The current in M1 is composed from the currents in the inductors L1 and L2. Hence, the RMS current in M1 can be computed as:

$i_{\text{D}\text{M1}}=\sqrt{\frac{D_{\max }\cdot i_{L1\text{pk}}^2}{6}+D_{\max }\cdot i_{\text{o}}^2}$

Where i_L1pk and D_max are calculated at V_AC min. We can disregard the ripple current in L2, as we want the average current. The drain voltage rating of M1 can be determined as:

$V_{\text{DS}\text{M1}}=V_{\text{AC}\max }\cdot \sqrt{2}+V_{\text{C}\max }\cdot \left(1+K_{\text{C}}\right)$

Where V_C max and K_C are calculated at V_AC max.

For the power MOSFET M1, it is very important to find a good balance between the total gate charge Q_g and the on resistance RDS (ON). Using a MOSFET with low RDS (ON) will not necessarily achieve greater efficiency. The gate drive current from the HV9931 is limited, so a large-gate charge will slow down the switching time and thus increase switching losses.

In addition to the slow turn-on speed generating higher-switching power loss, MOSFETs with high Q_g will require more current from the HV9931’s internal voltage regulator. When a MOSFET is being switched, the average current required by the gate driver is given by: i_g = Q_g × f_SW. So, if we have a MOSFET with 30-nC gate charge being switched at 50 kHz, the average gate driver current is 1.5 mA. A small-additional current is required by the HV9931 internal bias circuits, so we could have 2 mA drawn from the internal high-voltage regulator, while dropping 300 V or so. The HV9931 gate driving capability is therefore also limited by the package power dissipation. Being a linear regulator, the power dissipated will be i_in × (V_in – V_DD). Thus nonoptimal selection of M1 may cause the HV9931 to overheat.

8.6.1.4.2. Diodes D1–D4

The highest currents in D1–D4 averaged over the AC line cycle can be calculated as:

$\begin{array}{l}{i}_{\text{D}1}=\frac{4\cdot \sqrt{2}}{\pi }\cdot \frac{i_{\text{o}}}{{\eta }_1\cdot \left(1+\sqrt{1+{\delta }_{\min }}\right)}\\ i_{\text{D}2}=D_{\max }\cdot i_{\text{o}}=\frac{2\cdot \left(\sqrt{1+{\delta }_{\min }}-1\right)}{{\delta }_{\min }}\cdot i_{\text{o}}\\ i_{\text{D}3}=\left(1-D_{\min }\right)\cdot i_{\text{o}}=\frac{{\left(\sqrt{1+{\delta }_{\max }}-1\right)}^2}{{\delta }_{\max }}\cdot i_{\text{o}}\\ i_{\text{D}4}=\frac{4\cdot \sqrt{2}}{\pi }\cdot \left(\frac{2\cdot \sqrt{2}}{{\delta }_{\min }}+\frac{1}{{\eta }_1\cdot \left(1+\sqrt{1+{\delta }_{\min }}\right)}\right)\cdot i_{\text{o}}\end{array}$

Where δ_max and δ_min are calculated from our definition of δ given in Section 8.6.1.2, at V_AC max and V_AC min correspondingly. Peak currents in D1 and D4 equal to i_L1pk are calculated using the value of δ at V_AC min. Peak currents in D2 and D3 are computed as i_o + 0.5 × ∆i_L2.

The voltage ratings for D1–D3 are given as:

$\begin{array}{l}{V}_{\text{R}\text{D1}}=V_{\text{AC}\max }\cdot \sqrt{2}+V_{\text{C}}\cdot \left(1+K_{\text{C}}\right)\\ V_{\text{R}\text{D2}}=V_{\text{AC}\max }\cdot \sqrt{2}\\ V_{\text{R}\text{D3}}=V_{\text{C}}\cdot \left(1+K_{\text{C}}\right)\end{array}$

Using ultrafast recovery rectifiers for D2 and D3 is essential for good efficiency of the LED driver. Both diodes operate at high current and are subjected to fast transitions and high-reverse voltage.

The required reverse voltage rating of D4 depends on several factors. During the dead time, there could be a significant postconduction resonance. The LC tank is formed by L1 and the parasitic capacitance of D1, D4, and M1. The resonant period can be estimated as:

$T_{\text{R}}=2\cdot \pi \cdot \sqrt{\frac{L1\cdot C_{\text{JD}4}\cdot \left(C_{\text{OSS}}+C_{\text{JD1}}\right)}{C_{\text{OSS}}+C_{\text{JD1}}+C_{\text{JD4}}}}$

Where C_OSS is the output capacitance of M1, and C_JD1 and C_JD4 are reverse-biased junction capacitances of D1 and D4 correspondingly.

Due to a finite reverse recovery time of D1, the input inductor L1 develops a certain reverse current in the beginning of the dead time. As L1 runs in DCM, the reverse recovery time of D1 has negligible effect from the overall power efficiency point of view. However, even a small reverse current in L1 can cause a very high-voltage spike across D4, when both diodes stop conducting. Thus, ultrafast recovery diode is recommended for D1.

As C_JD4 << C_OSS typically, the postconduction oscillation occurs mainly across D4. The drain voltage of M1 will remain almost unchanged throughout the dead time. Besides causing the high-voltage stress across D4, this oscillation may affect the EMI performance of the circuit. Thus, adding an RC snubber circuit across D4 is recommended. If the snubber capacitance value is greater than (C_OSS + C_JD1), the reverse voltage rating of D4 can be reduced significantly.

The snubber capacitor can be selected as (approximately)

$C_{\text{D}}=10\cdot C_{\text{OSS}}$

And the snubber resistor

$R_{\text{D}}=\frac{0.33}{C_{\text{D}}\cdot 2\cdot \pi \cdot f_{\text{s}}}$

The snubber resistor should be rated at 0.5 or even 1 W, and 500 V breakdown. The minimum voltage rating for D4 will then be:

$V_{\text{R}\text{D4}}=V_{\text{AC}\text{max}}\cdot \sqrt{2}$

Thus in theory a fast 400-V diode can be used for D4 in a universal 90–260 V AC LED driver. In practice a fast diode rated at 600 V is normally used.

8.6.1.5. Output open circuit and input undervoltage protection

The BBB circuit is a constant output current source. Hence it can generate destructive voltage at its output in the case of an open circuit condition. A simple circuit shown in Fig. 8.8 protects the HV9931 LED driver from the output overvoltage.

Zener voltage of D12 greater than the maximum output voltage must be selected. Resistor R_ov is typically 100–200 Ω. However, it will affect the output current divider ratio and needs to be included in the calculations by replacing R_cs2 by (R_cs2 + R_ov).

Note, that the open circuit condition can create an overvoltage across C1. This voltage stress can be limited by connecting a Zener diode or TVS across C1 limiting the voltage to some acceptable level greater than V_C max. The power dissipation in this voltage clamp device is usually small, as the HV9931 operates at minimum duty cycle during the open circuit condition.

The HV9931 inherently protects the LED driver from an input undervoltage condition by limiting the input current. However, increased input current may generate excessive power dissipation in L1, D4, M1, and R_cs1. Additional protection is recommended by connecting a Zener diode in series with the V_in pin of the HV9931, as shown in Fig. 8.9. When the input voltage drops so that the Zener diode stops conducting, the HV9931 no longer has power and turns off.

In addition, an improved input undervoltage protection circuit is shown in Fig. 8.9, which can achieve better performance compared to the simple fixed input current limiting. The reference for the CS1 comparator is derived from the input rectified AC waveform. The voltage divider ratio of R1:R_ref1 is programmed such that the Zener diode Z_ref1 clamps the divider voltage at any input greater than V_AC min, that is:

$R_1=R_{\text{ref1}}\cdot \frac{V_{\text{AC}\min }\cdot \sqrt{2}-V_{{\text{Z}}_{\text{ref1}}}}{V_{{\text{Z}}_{\text{ref1}}}}$

$V_{\text{ref}}=V_{{\text{Z}}_{\text{ref1}}}$ should be used in the earlier equations to find the peak current limit for L1, within the normal operating input AC voltage range.

When the input voltage falls below V_AC min, the reference voltage will reduce too, preventing the inductor L1 from entering CCM. Operating L1 in CCM can cause undesirable LED flickering, audible noise, and excessive heat dissipation due to the loop oscillation. R_bias creates a positive offset voltage to maintain the reference above 0 V during the AC line voltage zero crossings and thus prevents interruptions of the output current.

8.6.1.6. Surge immunity and EMI considerations

High-voltage surges occur on the AC power mains as a result of switching operations in the power grid and from nearby lightning strikes. LED lighting and signal equipment may be subjected to surge immunity compliance testing in accordance with various standards (EN61000-4-5, NEMA TS-2 2.1.8, etc.) to ensure its continued reliable operation if subjected to realistic levels of surge voltages. The BBB LED driver circuit relies mainly on the transient suppressors (MOV and TVS) to protect it from the input AC line surge. There is little capacitance available at the AC input of the LED driver to absorb high-surge energy, although the EMI filter inductors do slow down any fast transient edges. Thus a transient suppressor needs to be connected across the AC input terminals.

As with all switching converters, selection of the input filter is critical to obtaining good EMI. The HV9931 solution using fixed off-time switching provides an inherent advantage of the frequency dither (spread spectrum). Hence less filtering may be needed, resulting in a smaller EMI filter.

Some important guidelines for PCB design must be followed for optimal EMI performance of the BBB power converter. The area of the fast-switching current loops must be minimized. The first loop including of M1, C1, D2, and D3 can significantly degrade the overall EMI performance due to the reverse recovery current in D3. Using a very fast diode is recommended for D3. The second loop consists of C_in, D1, C1, M1, and R_s1. As the input buck–boost stage runs in DCM, the reverse recovery current in D1 is insignificant. However, charging its junction capacitance can generate fast-current transients. The large physical dimensions of C1 can complicate optimal routing of these loops.

Optimal routing of the HV9931 gate drive output loop can be important for EMI performance, as well as for preventing destructive oscillations of the M1 gate voltage. Adding a 100R resistor in series with the gate will help to dampen any oscillations caused by parasitic inductance and capacitance. The gate driver loop area must be minimized to keep the inductance low and to reduce the emissions from the loop antenna created. The PCB trace connecting the source terminal of M1 with the GND pin of the HV9931 must be as short as possible to reduce inductance. The V_DD bypass capacitor, C_DD, provides the current for the MOSFET gate drive signal; it must have low ESR and located close to the V_DD pin of the HV9931.

Postconduction oscillation across D4 during the dead time of L1 can be another substantial source of RF emission. Adding a snubber circuit (R_d and C_d) can help significantly. In addition, this snubber is needed to reduce the voltage stress at D4 as discussed in Section 8.6.1.4.

The outside case of an electrolytic capacitor is connected to its negative terminal and in a traditional power supply this terminal is normally connected to the ground (0 V) rail to provide a degree of shielding. However, in the BBB circuit, this is not possible because the central energy storage capacitor C1 in this circuit is “floating” (not connected to circuit ground). It will behave like a radio frequency antenna. Placing the whole circuit into a shielded enclosure of some type is most likely necessary in the majority of applications.

8.7. LED Driver Design Example Using the BBB Circuit

$R_{\text{T}}=\frac{T_{\text{off}}-880\text{ns}}{40\cdot {10}^{-12}}=\frac{1.412\mu \text{s}}{40\cdot {10}^{-12}}=353\text{k}\Omega$

$i_{L\text{2pk}}=0.4025\text{A.}$

$L2=\frac{V_{\text{o}}\cdot T_{\text{off}}}{∆i_{L2}\cdot {\eta }_2}=\frac{35\cdot 15\cdot {10}^{-6}}{0.105\cdot 0.9}=5.55\text{mH}$

$i_{\text{sat}}>0.4025\text{A.}$

$R_{\text{s}2}=\frac{P}{i_{\text{o}}^2}=\frac{0.25\text{W}}{0.1225}=2.0408\Omega$

$i_{\text{Lpk}}=\frac{V_{\text{ref}}\cdot R_{\text{cs}}}{R_{\text{ref}}\cdot R_{\text{s}}}$, which transforms to

$R_{\text{cs}}=\frac{i_{\text{Lpk}}\cdot R_{\text{ref}}\cdot R_{\text{s}}}{V_{\text{ref}}}=\frac{0.4025\cdot 100\cdot {10}^3\cdot 1}{7.5}=5.366\text{k}\Omega$

$L1=\frac{0.63\cdot V_{\text{AC}\text{min}}\cdot \sqrt{2}\cdot T_{\text{off}}}{4\cdot i_{\text{o}}}=\frac{56.7\cdot \sqrt{2}\cdot 15\cdot {10}^{-6}}{1.4}=859\mu \text{H}$

$\begin{array}{l}{\delta }_{\min }=\frac{2\cdot V_{\text{AC}\min }^2\cdot T_{\text{off}}\cdot \eta }{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}=\frac{2\cdot 6400\cdot 15\mu \cdot 0.85}{35\cdot 0.35\cdot 700\mu }=19\\ D=\frac{2\cdot \left(\sqrt{1+\delta }-1\right)}{\delta }=0.365\end{array}$

$\begin{array}{l}{\delta }_{\max }=\frac{2\cdot V_{\text{AC}\max }^2\cdot T_{\text{off}}\cdot \eta }{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}=\frac{2\cdot \mathrm{67,600}\cdot 15\mu \cdot 0.85}{35\cdot 0.35\cdot 700\mu }=201\\ D=\frac{2\cdot \left(\sqrt{1+\delta }-1\right)}{\delta }=0.131\end{array}$

$\begin{array}{l}\delta =\frac{2\cdot V_{\text{AC}}^2\cdot T_{\text{off}}\cdot \eta }{V_{\text{o}}\cdot i_{\text{o}}\cdot L1}=\frac{2\cdot 14,400\cdot 15 \mu \cdot 0.85}{35\cdot 0.35\cdot 700\hspace{0.17em}\mu }=42.82\\ D=\frac{2\cdot \left(\sqrt{1+\delta }-1\right)}{\delta }=0.262\end{array}$

$\begin{array}{l}{i}_{L1\text{pk}\max }=\frac{V_{\text{AC}\min }\cdot \sqrt{2}\cdot T_{\text{off}}}{L1}\cdot \frac{D}{1-D}\\ i_{L1\text{pk}}=1.394\text{A}\end{array}$

$P_{{\text{R}}_{\text{s1}}}=0.1=\frac{D_{\max }\cdot i_{L1\text{pk}}^2\cdot R_{\text{s}1}}{6}$

$R_{\text{s}1}=\frac{0.6}{D_{\max }\cdot i_{L1\text{pk}}^2}=\frac{0.6}{0.365\cdot 1.394}=1.179\Omega$

$R_{\text{cs}}=\frac{i_{\text{Lpk}}\cdot R_{\text{ref}}\cdot R_{\text{s}}}{V_{\text{ref}}}=\frac{1.394\cdot 100\cdot {10}^3\cdot 0.47}{7.5}=8.735\text{k}\Omega$

$R_{\text{cs1}}=10.5\text{k}\Omega (\text{10k}\Omega \text{would}\text{be}\text{suitable})\text{.}$

$\begin{array}{l}C1=\frac{1}{\delta \cdot \left(1+\frac{1}{\sqrt{1+\delta }}\right)}\cdot \frac{{\eta }_2\cdot i_{\text{o}}}{\pi \cdot f_{\text{AC}}\cdot K_3\cdot V_{\text{o}}}\\ C1=\frac{1}{42.82\cdot \left(1.151\right)}\cdot \frac{0.9\cdot 0.35}{\pi \cdot 60\cdot 0.15\cdot 35}=6.458\mu \text{F}\\ C1\approx 10\mu \text{F}\end{array}$

$V_{\text{C}}=\frac{V_{\text{o}}}{2\cdot {\eta }_2}\cdot \left(1+\sqrt{1+\delta }\right)=\frac{35}{2\cdot 0.9}\cdot (1+\sqrt{202})=295.8\text{V}$

$\begin{array}{l}{K}_{\text{C}}=\frac{1}{{\left(1+\sqrt{1+\delta }\right)}^2}\cdot \frac{{\eta }_2\cdot i_{\text{o}}}{\pi \cdot f_{\text{AC}}\cdot C1\cdot V_{\text{o}}}\\ K_{\text{C}\min }=\frac{1}{231}\cdot \frac{0.9\cdot 0.35}{\pi \cdot 60\cdot {10}^{-5}\cdot 35}=24.75\text{mV}\end{array}$

$\begin{array}{l}{i}_{\text{C}\text{SW}}=i_{\text{o}}\cdot \sqrt{\frac{64}{9\cdot \pi \cdot \eta \cdot {\eta }_1}\cdot \frac{V_{\text{o}}}{V_{\text{AC}}\cdot \sqrt{2}}+D}\\ i_{\text{C}\text{SW}}=0.35\cdot \sqrt{\frac{64}{9\cdot \pi \cdot 0.76\cdot 0.85}\cdot \frac{35}{80\cdot \sqrt{2}}+0.365}=0.42\text{A}\end{array}$

$i_{\text{C}\text{line}}=\frac{\sqrt{2}\cdot i_{\text{o}}}{1+\sqrt{1+\delta }}=\frac{0.4949}{5.472}=0.09\text{A}$

$\begin{array}{l}{V}_{\text{DS}\text{M}1}=V_{\text{AC}\max }\cdot \sqrt{2}+V_{\text{C}\max }\cdot \left(1+K_{\text{C}}\right)\\ V_{\text{DS}\text{M}1}=260\cdot \sqrt{2}+300\cdot \left(1+0.025\right)=675.2\text{V}\end{array}$

$P_{\text{reg}}=\left(\frac{2\sqrt{2}\cdot V_{\text{AC}\max }}{\pi }-V_{\text{Z}}\right)\cdot \left(\frac{Q_{\text{g}}\cdot \left(1-D_{\min }\right)}{T_{\text{off}}}+\frac{V_{\text{ref}}}{R_{\text{ref1}}}+\frac{V_{\text{ref2}}}{R_{\text{ref2}}}+1\text{mA}\right)$

$\begin{array}{l}{P}_{\text{reg}}=\left(\frac{2\sqrt{2}\cdot 260}{\pi }-47\right)\cdot \left(\frac{15\cdot {10}^{-9}\cdot \left(1-0.131\right)}{15\cdot {10}^{-6}}+\frac{7.5}{100\cdot {10}^3}+\frac{7.5}{100\cdot {10}^3}+1\text{mA}\right)\\ P_{\text{reg}}=377.5\text{mW}\end{array}$

$i_{\text{D}\text{M1}}=\sqrt{\frac{D_{\max }\cdot i_{L1\text{pk}}^2}{6}+D_{\max }\cdot i_{\text{o}}^2}=\sqrt{\frac{0.365\cdot 1.943}{6}+0.365\cdot 0.1225}=0.404\text{A}$

$i_{L\text{1pk}}+i_{L\text{2pk}}=1.394\text{A}+0\text{.4025}\text{A}=1\text{.797}\text{A}$

$\begin{array}{l}{i}_{\text{D}1}=\frac{4\cdot \sqrt{2}}{\pi }\cdot \frac{i_{\text{o}}}{{\eta }_1\cdot \left(1+\sqrt{1+{\delta }_{\min }}\right)}=\frac{1.98}{14.6125}=0.136\text{A}\\ i_{\text{D}2}=D_{\max }\cdot i_{\text{o}}=0.128\text{A}\\ i_{\text{D}3}=\left(1-D_{\min }\right)\cdot i_{\text{o}}=0.304\text{A}\\ i_{\text{D}4}=\frac{4\cdot \sqrt{2}}{\pi }\cdot \left(\frac{2\cdot \sqrt{2}}{{\delta }_{\min }}+\frac{1}{{\eta }_1\cdot \left(1+\sqrt{1+{\delta }_{\min }}\right)}\right)\cdot i_{\text{o}}=1.8\cdot \left(\frac{2.8284}{19}+\frac{1}{4.6513}\right)=0.655\text{A}\end{array}$

$i_{\text{D1pk}}=i_{\text{D4pk}}=i_{L\text{1pk}}=1\text{.394}\text{A.}$

$\begin{array}{l}{V}_{\text{R}\text{D1}}=V_{\text{AC}\max }\cdot \sqrt{2}+V_{\text{C}}\cdot \left(1+K_{\text{C}}\right)=670.89\text{V}\\ V_{\text{R}\text{D2}}=V_{\text{AC}\max }\cdot \sqrt{2}=367.7\text{V}\\ V_{\text{R}\text{D3}}=V_{\text{C}}\cdot \left(1+K_{\text{C}}\right)=303.2\text{V}\end{array}$

$V_{\text{R}\text{D4}}=V_{\text{AC}\max }\cdot \sqrt{2}=367.7\text{V}$

$C_{\text{D}}=10\cdot C_{\text{OSS}}=220\text{pF}$

$R_{\text{D}}=\frac{0.33}{C_{\text{D}}\cdot 2\cdot \pi \cdot f_{\text{s}}}=4.7\text{k}\Omega$

8.8. Buck With PFC

$R_{\text{cs}}=\frac{0.4}{2\cdot i_{\text{av}}}$

$\begin{array}{l}V=L\frac{\text{d}i}{\text{d}t}\\ \text{d}i=i_{\text{pk}}\text{and}\text{d}t=T_{\text{off}}\end{array}$

$L=V\cdot \frac{T_{\text{off}}}{i_{pk}}$

$T_{\text{off}}=L\cdot \frac{i_{\text{pk}}}{V_{\text{LED}}}$

$T_{\text{on}\text{min}}=L\cdot \frac{0.2}{315}=1.4\mu \text{s}$

$\begin{array}{l}{T}_{\text{off}}=2.2\text{mH}\cdot \frac{0.2}{44.8}=9.82\mu \text{s}\\ T_{\text{on}\text{min}}=2.2\text{mH}\cdot \frac{0.2}{330.2}=1.33\mu \text{s}\end{array}$

8.9. Common Mistakes With PFC Circuits

8.10. Conclusions