Part 4: Epilog: Performance, Open Problems
by Sid Touati, Benoit de Dinechin
Advanced Backend Optimization
- Cover
- Contents
- Title Page
- Copyright
- Introduction
- Part 1: Prolog: Optimizing Compilation
- 1 On the Decidability of Phase Ordering in Optimizing Compilation
- 1.1. Introduction to the Phase Ordering Problem
- 1.2. Background on Phase Ordering
- 1.3. Toward a Theoretical Model for the Phase Ordering Problem
- 1.4. Examples of Decidable Simplified Cases
- 1.5. Compiler Optimization Parameter Space Exploration
- 1.6. Conclusion on Phase Ordering in Optimizing Compilation
- 1 On the Decidability of Phase Ordering in Optimizing Compilation
- Part 2: Instruction Scheduling
- 2 Instruction Scheduling Problems and Overview
- 3 Applications of Machine Scheduling to Instruction Scheduling
- 4 Instruction Scheduling Before Register Allocation
- 4.1. Instruction Scheduling for an Ilp Processor: Case of a Vliw Architecture
- 4.2. Large Neighborhood Search for the Resource-Constrained Modulo Scheduling Problem
- 4.3. Resource-Constrained Modulo Scheduling Problem
- 4.4. Time-Indexed Integer Programming Formulations
- 4.5. Large Neighborhood Search Heuristic
- 4.6. Summary and Conclusions
- 5 Instruction Scheduling After Register Allocation
- 6 Dealing in Practice With Memory Hierarchy Effects and Instruction Level Parallelism
- Part 3: Register Optimization
- 7 The Register Need of a Fixed Instruction Schedule
- 8 The Register Saturation
- 9 Spill Code Reduction
- 9.1. Introduction to Register Constraints in Software Pipelining
- 9.2. Related Work in Periodic Register Allocation
- 9.3. Sira: Schedule Independant Register Allocation
- 9.4. Siralina: An Efficient Polynomial Heuristic for Sira
- 9.5. Experimental Results With Sira
- 9.6. Conclusion on Spill Code Reduction
- 10 Exploiting the Register Access Delays Before Instruction Scheduling
- 10.1. Introduction
- 10.2. Problem Description of Ddg Circuits With Non-Positive Distances
- 10.3. Necessary and Sufficient Condition to Avoid Non-Positive Circuits
- 10.4. Application to the Sira Framework
- 10.5. Experimental Results on Eliminating Non-Positive Circuits
- 10.6. Conclusion on Non-Positive Circuit Elimination
- 11 Loop Unrolling Degree Minimization for Periodic Register Allocation
- 11.1. Introduction
- 11.2. Background
- 11.3. Problem Description of Unroll Factor Minimization for Unscheduled Loops
- 11.4. Algorithmic Solution for Unroll Factor Minimization: Single Register Type
- 11.5. Unroll Factor Minimization in the Presence of Multiple Register Types
- 11.6. Unroll Factor Reduction for Already Scheduled Loops
- 11.7. Experimental Results
- 11.8. Related Work
- 11.9. Conclusion on Loop Unroll Degree Minimization
- Part 4: Epilog: Performance, Open Problems
- 12 Statistical Performance Analysis: The Speedup-Test Protocol
- 12.1. Code Performance Variation
- 12.2. Background and Notations
- 12.3. Analyzing the Statistical Significance of the Observed Speedups
- 12.4. The Speedup-Test Software
- 12.5. Evaluating the Proportion of Accelerated Benchmarks by a Confidence Interval
- 12.6. Experiments and Applications
- 12.7. Related Work
- 12.8. Discussion and Conclusion on the Speedup-Test Protocol
- 12 Statistical Performance Analysis: The Speedup-Test Protocol
- Conclusion
- Appendix 1: Presentation of the Benchmarks Used in Our Experiments
- Appendix 2: Register Saturation Computation on Stand-Alone Ddg
- Appendix 3: Efficiency Of Sira on the Benchmarks
- Appendix 4: Efficiency of Non-Positive Circuit Elimination in the Sira Framework
- Appendix 5: Loop Unroll Degree Minimization: Experimental Results
- Appendix 6: Experimental Efficiency of Software Data Preloading and Prefetching for Embedded Vliw
- Appendix 7: Appendix of the Speedup-Test Protocol
- Bibliography
- Lists of Figures, Tables and Algorithms
- Index
PART 4
Epilog: Performance, Open Problems
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