Further Reading
Kopetz [Kop97] provides a thorough introduction to the design of distributed embedded systems. The book by Robert Bosch GmbH [Bos07] discusses automotive electronics in detail. The Digital Aviation Handbook[Spi07] describes the avionics systems of several aircraft. Staunstrup and Wolf’s edited volume [Sta97] surveys hardware/software co-design, including techniques for accelerated systems like those described in this chapter. Gupta and De Micheli [Gup93] and Ernst et al. [Ern93] describe early techniques for co-synthesis of accelerated systems. Callahan et al. [Cal00] describe an on-chip reconfigurable co-processor connected to a CPU. The book DVD Demystified[Tay06] gives a thorough introduction to the DVD.
Questions
Q8-1 Describe an I2C bus at the following OSI-compliant levels of detail:
Q8-2 Describe a 10Base-T Ethernet at the following OSI-compliant levels of detail:
Q8-3 Give examples of the component networks in a federated network for an automobile.
Q8-4 You are designing an embedded system using an Intel Xeon as a host. Does it make sense to add an accelerator to implement the function z = ax + by + c? Explain.
Q8-5 You are designing an embedded system using an embedded processor with no floating-point support as host. Does it make sense to add an accelerator to implement the floating-point function 
? Explain.
Q8-6 You are designing an embedded system using a high-performance embedded processor with floating point as host. Does it make sense to add an accelerator to implement the floating-point function 
? Explain.
Q8-7 You are designing an accelerated system that performs the following function as its main task:
for (i = 0; i < M; i++)
for (j = 0; j < N; j++)
f[i][j] = (pix[i][j – 1] + pix[i – 1][j] + pix[i][j] + pix[i + 1][j] +
pix[i][j + 1])/(5*MAXVAL);
Assume that the accelerator has the entire pix and f arrays in its internal memory during the entire computation—pix is read into the accelerator before the operations begin and f is written out after all computations have been completed.
a. Show a system schedule for the host, accelerator, and bus assuming that the accelerator is inactive during all data transfers. (All data are sent to the accelerator before it starts and data are read from the accelerator after the computations are finished.)
b. Show a system schedule for the host, accelerator, and bus assuming that the accelerator has enough memory for two pix and f arrays and that the host can transfer data for one set of computations while another set is being performed.
Q8-8 Find the longest path through the graph below, using the computation times on the nodes and the communication times on the edges.
Q8-9 Write pseudocode for an algorithm to determine the longest path through a system execution graph. The longest path is to be measured from one designated entry point to one exit point. Each node in the graph is labeled with a number giving the execution time of the process represented by that node.
Lab exercises
L8-1 Build an experimental setup that lets you monitor messages on an embedded network.
L8-2 Determine how much logic in an FPGA must be devoted to a PCI bus interface and how much would be left for an accelerator core.
L8-3 Develop a debugging scheme for an accelerator. Determine how you would easily enter data into the accelerator and easily observe its behavior. You will need to verify the system thoroughly, starting with basic communication and going through algorithmic verification.
L8-4 Develop a generic streaming interface for an accelerator. The interface should allow streaming data to be read by the accelerator from the host’s memory. It should also allow streaming data to be written from the accelerator back to memory. The interface should include a host-side mechanism for filling and draining the streaming data buffers.
1 An open collector uses a bipolar transistor, while an open drain circuit uses an MOS transistor.